/** * @brief SB Cimx entry point sbBeforePciInit wrapper */ static void sb800_enable(device_t dev) { struct southbridge_amd_cimx_sb800_config *sb_chip = (struct southbridge_amd_cimx_sb800_config *)(dev->chip_info); switch (dev->path.pci.devfn) { case (0x11 << 3) | 0: /* 0:11.0 SATA */ if (dev->enabled) { sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_ENABLED; if (1 == sb_chip->boot_switch_sata_ide) sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary. else if (0 == sb_chip->boot_switch_sata_ide) sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary. } else { sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_DISABLED; } break; case (0x14 << 3) | 0: /* 0:14:0 SMBUS */ clear_ioapic(VIO_APIC_VADDR); #if CONFIG_CPU_AMD_AGESA /* Assign the ioapic ID the next available number after the processor core local APIC IDs */ setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS); #else /* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */ #if (CONFIG_APIC_ID_OFFSET == 0 && CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS < 16) /* Assign the ioapic ID the next available number after the processor core local APIC IDs */ setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS); #elif (CONFIG_APIC_ID_OFFSET > 0) /* Assign the ioapic ID the value 0. Processor APIC IDs follow. */ setup_ioapic(VIO_APIC_VADDR, 0); #else #error "The processor APIC IDs must be lifted to make room for the I/O APIC ID" #endif #endif break; case (0x14 << 3) | 1: /* 0:14:1 IDE */ break; case (0x14 << 3) | 2: /* 0:14:2 HDA */ if (dev->enabled) { if (AZALIA_DISABLE == sb_config->AzaliaController) { sb_config->AzaliaController = AZALIA_AUTO; } } else { sb_config->AzaliaController = AZALIA_DISABLE; } break; case (0x14 << 3) | 3: /* 0:14:3 LPC */ /* Initialize the fans */ #if CONFIG_SB800_IMC_FAN_CONTROL init_sb800_IMC_fans(dev); #elif CONFIG_SB800_MANUAL_FAN_CONTROL init_sb800_MANUAL_fans(dev); #endif break; case (0x14 << 3) | 4: /* 0:14:4 PCI */ /* PcibConfig [PM_Reg: EAh], PCIDisable [Bit0] * 'PCIDisable' set to 0 to enable P2P bridge. * 'PCIDisable' set to 1 to disable P2P bridge and enable PCI interface pins * to function as GPIO {GPIO 35:0}. */ if (!sb_chip->disconnect_pcib && dev->enabled) RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, 0); else RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, BIT0); break; case (0x14 << 3) | 6: /* 0:14:6 GEC */ if (dev->enabled) { sb_config->GecConfig = 0; } else { sb_config->GecConfig = 1; } break; case (0x15 << 3) | 0: /* 0:15:0 PCIe PortA */ { device_t device; for (device = dev; device; device = device->next) { if (dev->path.type != DEVICE_PATH_PCI) continue; if ((device->path.pci.devfn & ~7) != PCI_DEVFN(0x15,0)) break; sb_config->PORTCONFIG[device->path.pci.devfn & 3].PortCfg.PortPresent = device->enabled; } /* * GPP_CFGMODE_X4000: PortA Lanes[3:0] * GPP_CFGMODE_X2200: PortA Lanes[1:0], PortB Lanes[3:2] * GPP_CFGMODE_X2110: PortA Lanes[1:0], PortB Lane2, PortC Lane3 * GPP_CFGMODE_X1111: PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3 */ sb_config->GppLinkConfig = sb_chip->gpp_configuration; } break; case (0x12 << 3) | 0: /* 0:12:0 OHCI-USB1 */ sb_config->USBMODE.UsbMode.Ohci1 = dev->enabled; break; case (0x12 << 3) | 2: /* 0:12:2 EHCI-USB1 */ sb_config->USBMODE.UsbMode.Ehci1 = dev->enabled; break; case (0x13 << 3) | 0: /* 0:13:0 OHCI-USB2 */ sb_config->USBMODE.UsbMode.Ohci2 = dev->enabled; break; case (0x13 << 3) | 2: /* 0:13:2 EHCI-USB2 */ sb_config->USBMODE.UsbMode.Ehci2 = dev->enabled; break; case (0x14 << 3) | 5: /* 0:14:5 OHCI-USB4 */ sb_config->USBMODE.UsbMode.Ohci4 = dev->enabled; break; case (0x16 << 3) | 0: /* 0:16:0 OHCI-USB3 */ sb_config->USBMODE.UsbMode.Ohci3 = dev->enabled; break; case (0x16 << 3) | 2: /* 0:16:2 EHCI-USB3 */ sb_config->USBMODE.UsbMode.Ehci3 = dev->enabled; /* call the CIMX entry at the last sb800 device, * so make sure the mainboard devicetree is complete */ if (!acpi_is_wakeup_s3()) sb_Before_Pci_Init(); else sb_Before_Pci_Restore_Init(); break; default: break; } }
/** * @brief SB Cimx entry point sbBeforePciInit wrapper */ static void sb800_enable(device_t dev) { struct southbridge_amd_cimx_sb800_config *sb_chip = (struct southbridge_amd_cimx_sb800_config *)(dev->chip_info); printk(BIOS_DEBUG, "sb800_enable() "); switch (dev->path.pci.devfn) { case (0x11 << 3) | 0: /* 0:11.0 SATA */ /* the first sb800 device */ switch (GPP_CFGMODE) { /* config the GPP PCIe ports */ case GPP_CFGMODE_X2200: abcfg_reg(0xc0, 0x01FF, 0x032); /* x2 Port_0, x2 Port_1 */ break; case GPP_CFGMODE_X2110: abcfg_reg(0xc0, 0x01FF, 0x073); /* x2 Port_0, x1 Port_1&2 */ break; case GPP_CFGMODE_X1111: abcfg_reg(0xc0, 0x01FF, 0x0F4); /* x1 Port_0&1&2&3 */ break; case GPP_CFGMODE_X4000: default: abcfg_reg(0xc0, 0x01FF, 0x010); /* x4 Port_0 */ break; } sb800_cimx_config(sb_config); if (dev->enabled) { sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_ENABLED; if (1 == sb_chip->boot_switch_sata_ide) sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary. else if (0 == sb_chip->boot_switch_sata_ide) sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary. } else { sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_DISABLED; } break; case (0x14 << 3) | 0: /* 0:14:0 SMBUS */ printk(BIOS_INFO, "sm_init().\n"); clear_ioapic(IO_APIC_ADDR); #if CONFIG_CPU_AMD_AGESA /* Assign the ioapic ID the next available number after the processor core local APIC IDs */ setup_ioapic(IO_APIC_ADDR, CONFIG_MAX_CPUS); #else /* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */ #if (CONFIG_APIC_ID_OFFSET == 0 && CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS < 16) /* Assign the ioapic ID the next available number after the processor core local APIC IDs */ setup_ioapic(IO_APIC_ADDR, CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS); #elif (CONFIG_APIC_ID_OFFSET > 0) /* Assign the ioapic ID the value 0. Processor APIC IDs follow. */ setup_ioapic(IO_APIC_ADDR, 0); #else #error "The processor APIC IDs must be lifted to make room for the I/O APIC ID" #endif #endif break; case (0x14 << 3) | 1: /* 0:14:1 IDE */ break; case (0x14 << 3) | 2: /* 0:14:2 HDA */ if (dev->enabled) { if (AZALIA_DISABLE == sb_config->AzaliaController) { sb_config->AzaliaController = AZALIA_AUTO; } printk(BIOS_DEBUG, "hda enabled\n"); } else { sb_config->AzaliaController = AZALIA_DISABLE; printk(BIOS_DEBUG, "hda disabled\n"); } break; case (0x14 << 3) | 3: /* 0:14:3 LPC */ /* Initialize the fans */ #if CONFIG_SB800_IMC_FAN_CONTROL init_sb800_IMC_fans(dev); #elif CONFIG_SB800_MANUAL_FAN_CONTROL init_sb800_MANUAL_fans(dev); #endif break; case (0x14 << 3) | 4: /* 0:14:4 PCI */ break; case (0x14 << 3) | 6: /* 0:14:6 GEC */ if (dev->enabled) { sb_config->GecConfig = 0; printk(BIOS_DEBUG, "gec enabled\n"); } else { sb_config->GecConfig = 1; printk(BIOS_DEBUG, "gec disabled\n"); } break; case (0x15 << 3) | 0: /* 0:15:0 PCIe PortA */ { device_t device; for (device = dev; device; device = device->next) { if (dev->path.type != DEVICE_PATH_PCI) continue; if ((device->path.pci.devfn & ~7) != PCI_DEVFN(0x15,0)) break; sb_config->PORTCONFIG[device->path.pci.devfn & 3].PortCfg.PortPresent = device->enabled; } /* * GPP_CFGMODE_X4000: PortA Lanes[3:0] * GPP_CFGMODE_X2200: PortA Lanes[1:0], PortB Lanes[3:2] * GPP_CFGMODE_X2110: PortA Lanes[1:0], PortB Lane2, PortC Lane3 * GPP_CFGMODE_X1111: PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3 */ sb_config->GppLinkConfig = sb_chip->gpp_configuration; } break; case (0x12 << 3) | 0: /* 0:12:0 OHCI-USB1 */ sb_config->USBMODE.UsbMode.Ohci1 = dev->enabled; break; case (0x12 << 3) | 2: /* 0:12:2 EHCI-USB1 */ sb_config->USBMODE.UsbMode.Ehci1 = dev->enabled; break; case (0x13 << 3) | 0: /* 0:13:0 OHCI-USB2 */ sb_config->USBMODE.UsbMode.Ohci2 = dev->enabled; break; case (0x13 << 3) | 2: /* 0:13:2 EHCI-USB2 */ sb_config->USBMODE.UsbMode.Ehci2 = dev->enabled; break; case (0x14 << 3) | 5: /* 0:14:5 OHCI-USB4 */ sb_config->USBMODE.UsbMode.Ohci4 = dev->enabled; break; case (0x16 << 3) | 0: /* 0:16:0 OHCI-USB3 */ sb_config->USBMODE.UsbMode.Ohci3 = dev->enabled; break; case (0x16 << 3) | 2: /* 0:16:2 EHCI-USB3 */ sb_config->USBMODE.UsbMode.Ehci3 = dev->enabled; /* call the CIMX entry at the last sb800 device, * so make sure the mainboard devicetree is complete */ if (!acpi_is_wakeup_s3()) sb_Before_Pci_Init(); else sb_Before_Pci_Restore_Init(); break; default: break; } }
void init_sb800_IMC_fans(struct device *dev) { AMDSBCFG sb_config; unsigned char *message_ptr; int i; struct southbridge_amd_cimx_sb800_config *sb_chip = (struct southbridge_amd_cimx_sb800_config *)(dev->chip_info); /* * The default I/O address of the IMC configuration register index * port is 0x6E. Change the IMC Config port I/O Address if it * conflicts with other components in the system. * * Device 20, Function 3, Reg 0xA4 * [0]: if 1, the address specified in IMC_PortAddress is used. * [15:1] IMC_PortAddress bits 15:1 (0x17 - address 0x2E) */ pci_write_config16(dev, 0xA4, sb_chip->imc_port_address | 0x01); /* * Do an initial manual setup of the fans for things like polarity * and frequency. */ init_sb800_MANUAL_fans(dev); /* * FLAG for Func 81/83/85/89 support (1=On,0=Off) * Bit0-3 = Func 81 Zone0-Zone3 * Bit4-7 = Func 83 Zone0-Zone3 * Bit8-11 = Func 85 Zone0-Zone3 * Bit12-15 = Func 89 Tempin Channel0-Channel3 */ sb_config.Pecstruct.IMCFUNSupportBitMap = 0; /* ********** Zone 0 ********** */ if (sb_chip->imc_fan_zone0_enabled) { sb_config.Pecstruct.IMCFUNSupportBitMap |= IMC_ENABLE_ZONE0; /* EC LDN9 function 81 zone 0 */ sb_config.Pecstruct.MSGFun81zone0MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun81zone0MSGREG1 = IMC_ZONE0; message_ptr = &sb_config.Pecstruct.MSGFun81zone0MSGREG2; for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++) *(message_ptr + i) = sb_chip->imc_zone0_config_vals[i]; /* EC LDN9 function 83 zone 0 - Temperature Thresholds */ sb_config.Pecstruct.MSGFun83zone0MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun83zone0MSGREG1 = IMC_ZONE0; sb_config.Pecstruct.MSGFun83zone0MSGREGB = 0x00; message_ptr = &sb_config.Pecstruct.MSGFun83zone0MSGREG2; for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++) *(message_ptr + i) = sb_chip->imc_zone0_thresholds[i]; /*EC LDN9 function 85 zone 0 - Fan Speeds */ sb_config.Pecstruct.MSGFun85zone0MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun85zone0MSGREG1 = IMC_ZONE0; message_ptr = &sb_config.Pecstruct.MSGFun85zone0MSGREG2; for (i = 0; i < IMC_FAN_SPEED_COUNT; i++) *(message_ptr + i) = sb_chip->imc_zone0_fanspeeds[i]; } /* ********** Zone 1 ********** */ if (sb_chip->imc_fan_zone1_enabled) { sb_config.Pecstruct.IMCFUNSupportBitMap |= IMC_ENABLE_ZONE1; /* EC LDN9 function 81 zone 1 */ sb_config.Pecstruct.MSGFun81zone1MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun81zone1MSGREG1 = IMC_ZONE1; message_ptr = &sb_config.Pecstruct.MSGFun81zone1MSGREG2; for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++) *(message_ptr + i) = sb_chip->imc_zone1_config_vals[i]; /* EC LDN9 function 83 zone 1 - Temperature Thresholds */ sb_config.Pecstruct.MSGFun83zone1MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun83zone1MSGREG1 = IMC_ZONE1; sb_config.Pecstruct.MSGFun83zone1MSGREGB = 0x00; message_ptr = &sb_config.Pecstruct.MSGFun83zone1MSGREG2; for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++) *(message_ptr + i) = sb_chip->imc_zone1_thresholds[i]; /* EC LDN9 function 85 zone 1 - Fan Speeds */ sb_config.Pecstruct.MSGFun85zone1MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun85zone1MSGREG1 = IMC_ZONE1; message_ptr = &sb_config.Pecstruct.MSGFun85zone1MSGREG2; for (i = 0; i < IMC_FAN_SPEED_COUNT; i++) *(message_ptr + i) = sb_chip->imc_zone1_fanspeeds[i]; } /* ********** Zone 2 ********** */ if (sb_chip->imc_fan_zone2_enabled) { sb_config.Pecstruct.IMCFUNSupportBitMap |= IMC_ENABLE_ZONE2; /* EC LDN9 function 81 zone 2 */ sb_config.Pecstruct.MSGFun81zone2MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun81zone2MSGREG1 = IMC_ZONE2; message_ptr = &sb_config.Pecstruct.MSGFun81zone2MSGREG2; for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++) *(message_ptr + i) = sb_chip->imc_zone2_config_vals[i]; /* EC LDN9 function 83 zone 2 */ sb_config.Pecstruct.MSGFun83zone2MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun83zone2MSGREG1 = IMC_ZONE2; sb_config.Pecstruct.MSGFun83zone2MSGREGB = 0x00; message_ptr = &sb_config.Pecstruct.MSGFun83zone2MSGREG2; for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++) *(message_ptr + i) = sb_chip->imc_zone2_thresholds[i]; /* EC LDN9 function 85 zone 2 */ sb_config.Pecstruct.MSGFun85zone2MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun85zone2MSGREG1 = IMC_ZONE2; message_ptr = &sb_config.Pecstruct.MSGFun85zone2MSGREG2; for (i = 0; i < IMC_FAN_SPEED_COUNT; i++) *(message_ptr + i) = sb_chip->imc_zone2_fanspeeds[i]; } /* ********** Zone 3 ********** */ if (sb_chip->imc_fan_zone3_enabled) { sb_config.Pecstruct.IMCFUNSupportBitMap |= IMC_ENABLE_ZONE3; /* EC LDN9 function 81 zone 3 */ sb_config.Pecstruct.MSGFun81zone3MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun81zone3MSGREG1 = IMC_ZONE3; message_ptr = &sb_config.Pecstruct.MSGFun81zone3MSGREG2; for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++) *(message_ptr + i) = sb_chip->imc_zone3_config_vals[i]; /* EC LDN9 function 83 zone 3 */ sb_config.Pecstruct.MSGFun83zone3MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun83zone3MSGREG1 = IMC_ZONE3; sb_config.Pecstruct.MSGFun83zone3MSGREGB = 0x00; message_ptr = &sb_config.Pecstruct.MSGFun83zone3MSGREG2; for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++) *(message_ptr + i) = sb_chip->imc_zone3_thresholds[i]; /* EC LDN9 function 85 zone 3 */ sb_config.Pecstruct.MSGFun85zone3MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun85zone3MSGREG1 = IMC_ZONE3; message_ptr = &sb_config.Pecstruct.MSGFun85zone3MSGREG2; for (i = 0; i < IMC_FAN_SPEED_COUNT; i++) *(message_ptr + i) = sb_chip->imc_zone3_fanspeeds[i]; } /* * EC LDN9 function 89 - Set HWM TEMPIN Temperature Calculation Parameters * This function provides the critical parameters of the HWM TempIn * sensors, IMC would not perform temperature measurement using those * sensors until the parameters are provided. */ if (sb_chip->imc_tempin0_enabled) { sb_config.Pecstruct.IMCFUNSupportBitMap |= IMC_ENABLE_TEMPIN0; /* EC LDN9 function 89 TEMPIN channel 0 */ sb_config.Pecstruct.MSGFun89zone0MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun89zone0MSGREG1 = 0x00; sb_config.Pecstruct.MSGFun89zone0MSGREG2 = (sb_chip->imc_tempin0_at & 0xff); sb_config.Pecstruct.MSGFun89zone0MSGREG3 = ((sb_chip->imc_tempin0_at >> 8) & 0xff); sb_config.Pecstruct.MSGFun89zone0MSGREG4 = ((sb_chip->imc_tempin0_at >> 16) & 0xff); sb_config.Pecstruct.MSGFun89zone0MSGREG5 = ((sb_chip->imc_tempin0_at >> 24) & 0xff); sb_config.Pecstruct.MSGFun89zone0MSGREG6 = (sb_chip->imc_tempin0_ct & 0xff); sb_config.Pecstruct.MSGFun89zone0MSGREG7 = ((sb_chip->imc_tempin0_ct >> 8) & 0xff); sb_config.Pecstruct.MSGFun89zone0MSGREG8 = ((sb_chip->imc_tempin0_ct >> 16) & 0xff); sb_config.Pecstruct.MSGFun89zone0MSGREG9 = ((sb_chip->imc_tempin0_ct >> 24) & 0xff); sb_config.Pecstruct.MSGFun89zone0MSGREGA = sb_chip->imc_tempin0_tuning_param; }