/** Configuration registers setter & getter */ int rp_LaAcqSetCntConfig(rp_handle_uio_t *handle, rp_la_cfg_regset_t a_reg) { rp_la_cfg_regset_t *regset = (rp_la_cfg_regset_t *) &(((rp_la_acq_regset_t*)handle->regset)->cfg); if(!(inrangeUint32 (a_reg.pre, RP_LA_ACQ_CFG_TRIG_MIN, RP_LA_ACQ_CFG_TRIG_MAX) && inrangeUint32 (a_reg.pst, RP_LA_ACQ_CFG_TRIG_MIN, RP_LA_ACQ_CFG_TRIG_MAX))){ return RP_EOOR; } iowrite32(a_reg.pre, ®set->pre); iowrite32(a_reg.pst, ®set->pst); return RP_OK; }
int rp_LaAcqGetCntStatus(rp_handle_uio_t *handle, uint32_t * trig_addr, uint32_t * pst_length, bool * buf_ovfl) { rp_la_cfg_regset_t *regset = (rp_la_cfg_regset_t *) &(((rp_la_acq_regset_t*)handle->regset)->sts); rp_la_cfg_regset_t reg; reg.pre = ioread32(®set->pre); reg.pst = ioread32(®set->pst); if(*trig_addr>=rp_LaAcqBufLenInSamples(handle)){ *buf_ovfl=true; } else{ *buf_ovfl=false; } *trig_addr=(reg.pre % rp_LaAcqBufLenInSamples(handle)); *pst_length=reg.pst; // calc. real trigger address if(*trig_addr<TRIG_DELAY_SAMPLES){ *trig_addr=rp_LaAcqBufLenInSamples(handle)-TRIG_DELAY_SAMPLES+*trig_addr; } else{ *trig_addr-=TRIG_DELAY_SAMPLES; } if(!(inrangeUint32 (*trig_addr, 0, (rp_LaAcqBufLenInSamples(handle)-1)))){ return RP_EOOR; } return RP_OK; }
RP_STATUS rp_RunBlock(uint32_t noOfPreTriggerSamples, uint32_t noOfPostTriggerSamples, uint32_t timebase, // int16_t oversample, double * timeIndisposedMs, //uint32_t segmentIndex, rpBlockReady rpReady, void * pParameter ) { double timeIntervalNanoseconds; uint32_t maxSamples=rp_LaAcqBufLenInSamples(&la_acq_handle); if(rp_GetTimebase(timebase,0,&timeIntervalNanoseconds,&maxSamples)!=RP_API_OK){ return RP_INVALID_TIMEBASE; } printf("\r\n timeIntervalNanoseconds: %f", timeIntervalNanoseconds); if(!(inrangeUint32 (noOfPreTriggerSamples+noOfPostTriggerSamples, 10, maxSamples))){ return RP_INVALID_PARAMETER; } printf("\r\n max: %d", maxSamples); *timeIndisposedMs=(noOfPreTriggerSamples+noOfPostTriggerSamples)*timeIntervalNanoseconds/10e6; // configure FPGA to start block mode // TODO; sampling rate rp_la_decimation_regset_t dec; dec.dec=timebase; rp_LaAcqSetDecimation(&la_acq_handle, dec); rp_la_cfg_regset_t cfg; cfg.pre=noOfPreTriggerSamples; cfg.pst=noOfPostTriggerSamples; if(rp_LaAcqSetCntConfig(&la_acq_handle, cfg)!=RP_OK){ return RP_INVALID_PARAMETER; } printf("\r\nrp_LaAcqRunAcq"); // start acq. if(rp_LaAcqRunAcq(&la_acq_handle)!=RP_OK){ rp_LaAcqStopAcq(&la_acq_handle); return RP_BLOCK_MODE_FAILED; } //rp_LaAcqFpgaRegDump(&la_acq_handle); // block till acq. is complete printf("\r\nBlocking read"); g_acq_running=true; rp_LaAcqBlockingRead(&la_acq_handle); g_acq_running=false; // make sure acq. is stopped bool isStoped; rp_LaAcqAcqIsStopped(&la_acq_handle, &isStoped); if(!isStoped){ printf("\r\n not stopped!!"); rp_LaAcqStopAcq(&la_acq_handle); return RP_BLOCK_MODE_FAILED; } // rp_DmaMemDump(&la_acq_handle); uint32_t trig_sample; uint32_t last_sample; bool rle; rp_LaAcqIsRLE(&la_acq_handle,&rle); if(rle){ // in the RLE mode we only check which was the last sample where acq. stopped uint32_t current; bool buf_ovfl; rp_LaAcqGetRLEStatus(&la_acq_handle, ¤t, &last_sample, &buf_ovfl); trig_sample=0; } else{ // get trigger position uint32_t pst_length; bool buf_ovfl; if(rp_LaAcqGetCntStatus(&la_acq_handle, &trig_sample, &pst_length, &buf_ovfl)!=RP_OK){ rp_LaAcqStopAcq(&la_acq_handle); return RP_BLOCK_MODE_FAILED; } printf("\r\n trig_sample %d, pst_length %d, buf_ovfl %d", trig_sample, pst_length, buf_ovfl); // acquired number of post samples must match to req if(pst_length!=noOfPostTriggerSamples){ rp_LaAcqStopAcq(&la_acq_handle); return RP_BLOCK_MODE_FAILED; } } // save properties of current acq. acq_data.pre_samples=noOfPreTriggerSamples; acq_data.post_samples=noOfPostTriggerSamples; acq_data.trig_sample=trig_sample; acq_data.last_sample=last_sample; // acquisition is completed -> callback RP_STATUS status=RP_API_OK; (*rpReady)(status,pParameter); rp_LaAcqStopAcq(&la_acq_handle); return RP_API_OK; }