unsigned int PerformFLT(const unsigned int opcode)
{
FPA11 *fpa11 = GET_FPA11();
struct roundingData roundData;
roundData.mode = SetRoundingMode(opcode);
roundData.precision = SetRoundingPrecision(opcode);
roundData.exception = 0;
switch (opcode & MASK_ROUNDING_PRECISION) {
case ROUND_SINGLE:
{
fpa11->fType[getFn(opcode)] = typeSingle;
fpa11->fpreg[getFn(opcode)].fSingle = int32_to_float32(&roundData, readRegister(getRd(opcode)));
}
break;
case ROUND_DOUBLE:
{
fpa11->fType[getFn(opcode)] = typeDouble;
fpa11->fpreg[getFn(opcode)].fDouble = int32_to_float64(readRegister(getRd(opcode)));
}
break;
#ifdef CONFIG_FPE_NWFPE_XP
case ROUND_EXTENDED:
{
fpa11->fType[getFn(opcode)] = typeExtended;
fpa11->fpreg[getFn(opcode)].fExtended = int32_to_floatx80(readRegister(getRd(opcode)));
}
break;
#endif
default:
return 0;
}
if (roundData.exception)
float_raise(roundData.exception);
return 1;
}
/* DB /0 */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::FILD_DWORD_INTEGER(bxInstruction_c *i)
{
#if BX_SUPPORT_FPU
BX_CPU_THIS_PTR prepareFPU(i);
Bit32s load_reg = (Bit32s) read_virtual_dword(i->seg(), RMAddr(i));
clear_C1();
if (! IS_TAG_EMPTY(-1)) {
BX_CPU_THIS_PTR FPU_stack_overflow();
return;
}
floatx80 result = int32_to_floatx80(load_reg);
BX_CPU_THIS_PTR the_i387.FPU_push();
BX_WRITE_FPU_REG(result, 0);
#else
BX_INFO(("FILD_DWORD_INTEGER: required FPU, configure --enable-fpu"));
#endif
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FICOM_WORD_INTEGER(bxInstruction_c *i)
{
BX_CPU_THIS_PTR prepareFPU(i);
int pop_stack = i->nnn() & 1;
RMAddr(i) = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
Bit16s load_reg = (Bit16s) read_virtual_word(i->seg(), RMAddr(i));
BX_CPU_THIS_PTR FPU_update_last_instruction(i);
clear_C1();
if (IS_TAG_EMPTY(0))
{
FPU_exception(FPU_EX_Stack_Underflow);
setcc(FPU_SW_C0|FPU_SW_C2|FPU_SW_C3);
if(BX_CPU_THIS_PTR the_i387.is_IA_masked())
{
if (pop_stack)
BX_CPU_THIS_PTR the_i387.FPU_pop();
}
BX_NEXT_INSTR(i);
}
float_status_t status =
FPU_pre_exception_handling(BX_CPU_THIS_PTR the_i387.get_control_word());
int rc = floatx80_compare(BX_READ_FPU_REG(0),
int32_to_floatx80((Bit32s)(load_reg)), status);
setcc(status_word_flags_fpu_compare(rc));
if (! FPU_exception(status.float_exception_flags)) {
if (pop_stack)
BX_CPU_THIS_PTR the_i387.FPU_pop();
}
BX_NEXT_INSTR(i);
}
/* DB /0 */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FILD_DWORD_INTEGER(bxInstruction_c *i)
{
BX_CPU_THIS_PTR prepareFPU(i);
RMAddr(i) = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
Bit32s load_reg = (Bit32s) read_virtual_dword(i->seg(), RMAddr(i));
FPU_update_last_instruction(i);
clear_C1();
if (! IS_TAG_EMPTY(-1)) {
FPU_stack_overflow();
}
else {
floatx80 result = int32_to_floatx80(load_reg);
BX_CPU_THIS_PTR the_i387.FPU_push();
BX_WRITE_FPU_REG(result, 0);
}
BX_NEXT_INSTR(i);
}
static void fpgen_rm_reg(m68000_base_device *m68k, UINT16 w2)
{
int ea = m68k->ir & 0x3f;
int rm = (w2 >> 14) & 0x1;
int src = (w2 >> 10) & 0x7;
int dst = (w2 >> 7) & 0x7;
int opmode = w2 & 0x7f;
floatx80 source;
// fmovecr #$f, fp0 f200 5c0f
if (rm)
{
switch (src)
{
case 0: // Long-Word Integer
{
INT32 d = READ_EA_32(m68k, ea);
source = int32_to_floatx80(d);
break;
}
case 1: // Single-precision Real
{
UINT32 d = READ_EA_32(m68k, ea);
source = float32_to_floatx80(d);
break;
}
case 2: // Extended-precision Real
{
source = READ_EA_FPE(m68k, ea);
break;
}
case 3: // Packed-decimal Real
{
source = READ_EA_PACK(m68k, ea);
break;
}
case 4: // Word Integer
{
INT16 d = READ_EA_16(m68k, ea);
source = int32_to_floatx80((INT32)d);
break;
}
case 5: // Double-precision Real
{
UINT64 d = READ_EA_64(m68k, ea);
source = float64_to_floatx80(d);
break;
}
case 6: // Byte Integer
{
INT8 d = READ_EA_8(m68k, ea);
source = int32_to_floatx80((INT32)d);
break;
}
case 7: // FMOVECR load from constant ROM
{
switch (w2 & 0x7f)
{
case 0x0: // Pi
source.high = 0x4000;
source.low = U64(0xc90fdaa22168c235);
break;
case 0xb: // log10(2)
source.high = 0x3ffd;
source.low = U64(0x9a209a84fbcff798);
break;
case 0xc: // e
source.high = 0x4000;
source.low = U64(0xadf85458a2bb4a9b);
break;
case 0xd: // log2(e)
source.high = 0x3fff;
source.low = U64(0xb8aa3b295c17f0bc);
break;
case 0xe: // log10(e)
source.high = 0x3ffd;
source.low = U64(0xde5bd8a937287195);
break;
case 0xf: // 0.0
source = int32_to_floatx80((INT32)0);
break;
case 0x30: // ln(2)
source.high = 0x3ffe;
source.low = U64(0xb17217f7d1cf79ac);
break;
case 0x31: // ln(10)
source.high = 0x4000;
source.low = U64(0x935d8dddaaa8ac17);
break;
case 0x32: // 1 (or 100? manuals are unclear, but 1 would make more sense)
source = int32_to_floatx80((INT32)1);
break;
case 0x33: // 10^1
source = int32_to_floatx80((INT32)10);
break;
case 0x34: // 10^2
source = int32_to_floatx80((INT32)10*10);
break;
case 0x35: // 10^4
source = int32_to_floatx80((INT32)1000*10);
break;
case 0x36: // 1.0e8
source = int32_to_floatx80((INT32)10000000*10);
break;
case 0x37: // 1.0e16 - can't get the right precision from INT32 so go "direct" with constants from h/w
source.high = 0x4034;
source.low = U64(0x8e1bc9bf04000000);
break;
case 0x38: // 1.0e32
source.high = 0x4069;
source.low = U64(0x9dc5ada82b70b59e);
break;
case 0x39: // 1.0e64
source.high = 0x40d3;
source.low = U64(0xc2781f49ffcfa6d5);
break;
case 0x3a: // 1.0e128
source.high = 0x41a8;
source.low = U64(0x93ba47c980e98ce0);
break;
case 0x3b: // 1.0e256
source.high = 0x4351;
source.low = U64(0xaa7eebfb9df9de8e);
break;
case 0x3c: // 1.0e512
source.high = 0x46a3;
source.low = U64(0xe319a0aea60e91c7);
break;
case 0x3d: // 1.0e1024
source.high = 0x4d48;
source.low = U64(0xc976758681750c17);
break;
case 0x3e: // 1.0e2048
source.high = 0x5a92;
source.low = U64(0x9e8b3b5dc53d5de5);
break;
case 0x3f: // 1.0e4096
source.high = 0x7525;
source.low = U64(0xc46052028a20979b);
break;
default:
fatalerror("fmove_rm_reg: unknown constant ROM offset %x at %08x\n", w2&0x7f, REG_PC(m68k)-4);
break;
}
// handle it right here, the usual opmode bits aren't valid in the FMOVECR case
REG_FP(m68k)[dst] = source;
m68k->remaining_cycles -= 4;
return;
}
default: fatalerror("fmove_rm_reg: invalid source specifier %x at %08X\n", src, REG_PC(m68k)-4);
}
}
else
{
source = REG_FP(m68k)[src];
}
switch (opmode)
{
case 0x00: // FMOVE
{
REG_FP(m68k)[dst] = source;
SET_CONDITION_CODES(m68k, REG_FP(m68k)[dst]);
m68k->remaining_cycles -= 4;
break;
}
case 0x01: // FINT
{
INT32 temp;
temp = floatx80_to_int32(source);
REG_FP(m68k)[dst] = int32_to_floatx80(temp);
break;
}
case 0x03: // FINTRZ
{
INT32 temp;
temp = floatx80_to_int32_round_to_zero(source);
REG_FP(m68k)[dst] = int32_to_floatx80(temp);
break;
}
case 0x04: // FSQRT
{
REG_FP(m68k)[dst] = floatx80_sqrt(source);
SET_CONDITION_CODES(m68k, REG_FP(m68k)[dst]);
m68k->remaining_cycles -= 109;
break;
}
case 0x06: // FLOGNP1
{
REG_FP(m68k)[dst] = floatx80_flognp1 (source);
SET_CONDITION_CODES(m68k, REG_FP(m68k)[dst]);
m68k->remaining_cycles -= 594; // for MC68881
break;
}
case 0x0e: // FSIN
{
REG_FP(m68k)[dst] = source;
floatx80_fsin(REG_FP(m68k)[dst]);
SET_CONDITION_CODES(m68k, REG_FP(m68k)[dst]);
m68k->remaining_cycles -= 75;
break;
}
case 0x0f: // FTAN
{
REG_FP(m68k)[dst] = source;
floatx80_ftan(REG_FP(m68k)[dst]);
SET_CONDITION_CODES(m68k, REG_FP(m68k)[dst]);
m68k->remaining_cycles -= 75;
break;
}
case 0x14: // FLOGN
{
REG_FP(m68k)[dst] = floatx80_flogn (source);
SET_CONDITION_CODES(m68k, REG_FP(m68k)[dst]);
m68k->remaining_cycles -= 548; // for MC68881
break;
}
case 0x15: // FLOG10
{
REG_FP(m68k)[dst] = floatx80_flog10 (source);
SET_CONDITION_CODES(m68k, REG_FP(m68k)[dst]);
m68k->remaining_cycles -= 604; // for MC68881
break;
}
case 0x16: // FLOG2
{
REG_FP(m68k)[dst] = floatx80_flog2 (source);
SET_CONDITION_CODES(m68k, REG_FP(m68k)[dst]);
m68k->remaining_cycles -= 604; // for MC68881
break;
}
case 0x18: // FABS
{
REG_FP(m68k)[dst] = source;
REG_FP(m68k)[dst].high &= 0x7fff;
SET_CONDITION_CODES(m68k, REG_FP(m68k)[dst]);
m68k->remaining_cycles -= 3;
break;
}
case 0x1a: // FNEG
{
REG_FP(m68k)[dst] = source;
REG_FP(m68k)[dst].high ^= 0x8000;
SET_CONDITION_CODES(m68k, REG_FP(m68k)[dst]);
m68k->remaining_cycles -= 3;
break;
}
case 0x1d: // FCOS
{
REG_FP(m68k)[dst] = source;
floatx80_fcos(REG_FP(m68k)[dst]);
SET_CONDITION_CODES(m68k, REG_FP(m68k)[dst]);
m68k->remaining_cycles -= 75;
break;
}
case 0x1e: // FGETEXP
{
INT16 temp2;
temp2 = source.high; // get the exponent
temp2 -= 0x3fff; // take off the bias
REG_FP(m68k)[dst] = double_to_fx80((double)temp2);
SET_CONDITION_CODES(m68k, REG_FP(m68k)[dst]);
m68k->remaining_cycles -= 6;
break;
}
case 0x20: // FDIV
{
REG_FP(m68k)[dst] = floatx80_div(REG_FP(m68k)[dst], source);
m68k->remaining_cycles -= 43;
break;
}
case 0x22: // FADD
{
REG_FP(m68k)[dst] = floatx80_add(REG_FP(m68k)[dst], source);
SET_CONDITION_CODES(m68k, REG_FP(m68k)[dst]);
m68k->remaining_cycles -= 9;
break;
}
case 0x23: // FMUL
{
REG_FP(m68k)[dst] = floatx80_mul(REG_FP(m68k)[dst], source);
SET_CONDITION_CODES(m68k, REG_FP(m68k)[dst]);
m68k->remaining_cycles -= 11;
break;
}
case 0x24: // FSGLDIV
{
float32 a = floatx80_to_float32( REG_FP(m68k)[dst] );
float32 b = floatx80_to_float32( source );
REG_FP(m68k)[dst] = float32_to_floatx80( float32_div(a, b) );
m68k->remaining_cycles -= 43; // // ? (value is from FDIV)
break;
}
case 0x25: // FREM
{
REG_FP(m68k)[dst] = floatx80_rem(REG_FP(m68k)[dst], source);
SET_CONDITION_CODES(m68k, REG_FP(m68k)[dst]);
m68k->remaining_cycles -= 43; // guess
break;
}
case 0x27: // FSGLMUL
{
float32 a = floatx80_to_float32( REG_FP(m68k)[dst] );
float32 b = floatx80_to_float32( source );
REG_FP(m68k)[dst] = float32_to_floatx80( float32_mul(a, b) );
SET_CONDITION_CODES(m68k, REG_FP(m68k)[dst]);
m68k->remaining_cycles -= 11; // ? (value is from FMUL)
break;
}
case 0x28: // FSUB
{
REG_FP(m68k)[dst] = floatx80_sub(REG_FP(m68k)[dst], source);
SET_CONDITION_CODES(m68k, REG_FP(m68k)[dst]);
m68k->remaining_cycles -= 9;
break;
}
case 0x38: // FCMP
{
floatx80 res;
res = floatx80_sub(REG_FP(m68k)[dst], source);
SET_CONDITION_CODES(m68k, res);
m68k->remaining_cycles -= 7;
break;
}
case 0x3a: // FTST
{
floatx80 res;
res = source;
SET_CONDITION_CODES(m68k, res);
m68k->remaining_cycles -= 7;
break;
}
default: fatalerror("fpgen_rm_reg: unimplemented opmode %02X at %08X\n", opmode, REG_PPC(m68k));
}
}
static void fpgen_rm_reg(m68ki_cpu_core *m68k, UINT16 w2)
{
int ea = m68k->ir & 0x3f;
int rm = (w2 >> 14) & 0x1;
int src = (w2 >> 10) & 0x7;
int dst = (w2 >> 7) & 0x7;
int opmode = w2 & 0x7f;
floatx80 source;
// fmovecr #$f, fp0 f200 5c0f
if (rm)
{
switch (src)
{
case 0: // Long-Word Integer
{
INT32 d = READ_EA_32(m68k, ea);
source = int32_to_floatx80(d);
break;
}
case 1: // Single-precision Real
{
UINT32 d = READ_EA_32(m68k, ea);
source = float32_to_floatx80(d);
break;
}
case 2: // Extended-precision Real
{
source = READ_EA_FPE(m68k, ea);
break;
}
case 3: // Packed-decimal Real
{
source = READ_EA_PACK(m68k, ea);
break;
}
case 4: // Word Integer
{
INT16 d = READ_EA_16(m68k, ea);
source = int32_to_floatx80((INT32)d);
break;
}
case 5: // Double-precision Real
{
UINT64 d = READ_EA_64(m68k, ea);
source = float64_to_floatx80(d);
break;
}
case 6: // Byte Integer
{
INT8 d = READ_EA_8(m68k, ea);
source = int32_to_floatx80((INT32)d);
break;
}
case 7: // FMOVECR load from constant ROM
{
switch (w2 & 0x7f)
{
case 0x0: // Pi
source.high = 0x4000;
source.low = U64(0xc90fdaa22168c235);
break;
case 0xb: // log10(2)
source.high = 0x3ffd;
source.low = U64(0x9a209a84fbcff798);
break;
case 0xc: // e
source.high = 0x4000;
source.low = U64(0xadf85458a2bb4a9b);
break;
case 0xd: // log2(e)
source.high = 0x3fff;
source.low = U64(0xb8aa3b295c17f0bc);
break;
case 0xe: // log10(e)
source.high = 0x3ffd;
source.low = U64(0xde5bd8a937287195);
break;
case 0xf: // 0.0
source = int32_to_floatx80((INT32)0);
break;
case 0x30: // ln(2)
source.high = 0x3ffe;
source.low = U64(0xb17217f7d1cf79ac);
break;
case 0x31: // ln(10)
source.high = 0x4000;
source.low = U64(0x935d8dddaaa8ac17);
break;
case 0x32: // 1 (or 100? manuals are unclear, but 1 would make more sense)
source = int32_to_floatx80((INT32)1);
break;
case 0x33: // 10^1
source = int32_to_floatx80((INT32)10);
break;
case 0x34: // 10^2
source = int32_to_floatx80((INT32)10*10);
break;
default:
fatalerror("fmove_rm_reg: unknown constant ROM offset %x at %08x\n", w2&0x7f, REG_PC(m68k)-4);
break;
}
// handle it right here, the usual opmode bits aren't valid in the FMOVECR case
REG_FP(m68k)[dst] = source;
m68k->remaining_cycles -= 4;
return;
}
default: fatalerror("fmove_rm_reg: invalid source specifier %x at %08X\n", src, REG_PC(m68k)-4);
}
}
else
{
source = REG_FP(m68k)[src];
}
switch (opmode)
{
case 0x00: // FMOVE
{
REG_FP(m68k)[dst] = source;
SET_CONDITION_CODES(m68k, REG_FP(m68k)[dst]);
m68k->remaining_cycles -= 4;
break;
}
case 0x01: // FINT
{
INT32 temp;
temp = floatx80_to_int32(source);
REG_FP(m68k)[dst] = int32_to_floatx80(temp);
break;
}
case 0x03: // FINTRZ
{
INT32 temp;
temp = floatx80_to_int32_round_to_zero(source);
REG_FP(m68k)[dst] = int32_to_floatx80(temp);
break;
}
case 0x04: // FSQRT
{
REG_FP(m68k)[dst] = floatx80_sqrt(source);
SET_CONDITION_CODES(m68k, REG_FP(m68k)[dst]);
m68k->remaining_cycles -= 109;
break;
}
case 0x0e: // FSIN
{
REG_FP(m68k)[dst] = source;
floatx80_fsin(REG_FP(m68k)[dst]);
SET_CONDITION_CODES(m68k, REG_FP(m68k)[dst]);
m68k->remaining_cycles -= 75;
break;
}
case 0x0f: // FTAN
{
REG_FP(m68k)[dst] = source;
floatx80_ftan(REG_FP(m68k)[dst]);
SET_CONDITION_CODES(m68k, REG_FP(m68k)[dst]);
m68k->remaining_cycles -= 75;
break;
}
case 0x18: // FABS
{
REG_FP(m68k)[dst] = source;
REG_FP(m68k)[dst].high &= 0x7fff;
SET_CONDITION_CODES(m68k, REG_FP(m68k)[dst]);
m68k->remaining_cycles -= 3;
break;
}
case 0x1a: // FNEG
{
REG_FP(m68k)[dst] = source;
REG_FP(m68k)[dst].high ^= 0x8000;
SET_CONDITION_CODES(m68k, REG_FP(m68k)[dst]);
m68k->remaining_cycles -= 3;
break;
}
case 0x1d: // FCOS
{
REG_FP(m68k)[dst] = source;
floatx80_fcos(REG_FP(m68k)[dst]);
SET_CONDITION_CODES(m68k, REG_FP(m68k)[dst]);
m68k->remaining_cycles -= 75;
break;
}
case 0x1e: // FGETEXP
{
INT16 temp2;
temp2 = source.high; // get the exponent
temp2 -= 0x3fff; // take off the bias
REG_FP(m68k)[dst] = double_to_fx80((double)temp2);
SET_CONDITION_CODES(m68k, REG_FP(m68k)[dst]);
m68k->remaining_cycles -= 6;
}
case 0x20: // FDIV
{
REG_FP(m68k)[dst] = floatx80_div(REG_FP(m68k)[dst], source);
m68k->remaining_cycles -= 43;
break;
}
case 0x22: // FADD
{
REG_FP(m68k)[dst] = floatx80_add(REG_FP(m68k)[dst], source);
SET_CONDITION_CODES(m68k, REG_FP(m68k)[dst]);
m68k->remaining_cycles -= 9;
break;
}
case 0x23: // FMUL
{
REG_FP(m68k)[dst] = floatx80_mul(REG_FP(m68k)[dst], source);
SET_CONDITION_CODES(m68k, REG_FP(m68k)[dst]);
m68k->remaining_cycles -= 11;
break;
}
case 0x24: // FSGLDIV
{
REG_FP(m68k)[dst] = floatx80_div(REG_FP(m68k)[dst], source);
m68k->remaining_cycles -= 43; // // ? (value is from FDIV)
break;
}
case 0x25: // FREM
{
REG_FP(m68k)[dst] = floatx80_rem(REG_FP(m68k)[dst], source);
SET_CONDITION_CODES(m68k, REG_FP(m68k)[dst]);
m68k->remaining_cycles -= 43; // guess
break;
}
case 0x27: // FSGLMUL
{
REG_FP(m68k)[dst] = floatx80_mul(REG_FP(m68k)[dst], source);
SET_CONDITION_CODES(m68k, REG_FP(m68k)[dst]);
m68k->remaining_cycles -= 11; // ? (value is from FMUL)
break;
}
case 0x28: // FSUB
{
REG_FP(m68k)[dst] = floatx80_sub(REG_FP(m68k)[dst], source);
SET_CONDITION_CODES(m68k, REG_FP(m68k)[dst]);
m68k->remaining_cycles -= 9;
break;
}
case 0x38: // FCMP
{
floatx80 res;
res = floatx80_sub(REG_FP(m68k)[dst], source);
SET_CONDITION_CODES(m68k, res);
m68k->remaining_cycles -= 7;
break;
}
case 0x3a: // FTST
{
floatx80 res;
res = source;
SET_CONDITION_CODES(m68k, res);
m68k->remaining_cycles -= 7;
break;
}
default: fatalerror("fpgen_rm_reg: unimplemented opmode %02X at %08X\n", opmode, REG_PPC(m68k));
}
}