struct hw_context * gen6_enc_hw_context_init(VADriverContextP ctx, VAProfile profile) { struct intel_driver_data *intel = intel_driver_data(ctx); struct gen6_encoder_context *gen6_encoder_context = calloc(1, sizeof(struct gen6_encoder_context)); gen6_encoder_context->base.destroy = gen6_encoder_context_destroy; gen6_encoder_context->base.run = gen6_encoder_end_picture; gen6_encoder_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER, 0); gen6_vme_context_init(ctx, &gen6_encoder_context->vme_context); gen6_mfc_context_init(ctx, &gen6_encoder_context->mfc_context); return (struct hw_context *)gen6_encoder_context; }
static struct hw_context * intel_enc_hw_context_init(VADriverContextP ctx, struct object_config *obj_config, hw_init_func vme_context_init, hw_init_func mfc_context_init) { struct intel_driver_data *intel = intel_driver_data(ctx); struct intel_encoder_context *encoder_context = calloc(1, sizeof(struct intel_encoder_context)); int i; encoder_context->base.destroy = intel_encoder_context_destroy; encoder_context->base.run = intel_encoder_end_picture; encoder_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER, 0); encoder_context->input_yuv_surface = VA_INVALID_SURFACE; encoder_context->is_tmp_id = 0; encoder_context->rate_control_mode = VA_RC_NONE; switch (obj_config->profile) { case VAProfileMPEG2Simple: case VAProfileMPEG2Main: encoder_context->codec = CODEC_MPEG2; break; case VAProfileH264ConstrainedBaseline: case VAProfileH264Main: case VAProfileH264High: encoder_context->codec = CODEC_H264; break; case VAProfileH264StereoHigh: case VAProfileH264MultiviewHigh: encoder_context->codec = CODEC_H264_MVC; break; default: /* Never get here */ assert(0); break; } for (i = 0; i < obj_config->num_attribs; i++) { if (obj_config->attrib_list[i].type == VAConfigAttribRateControl) { encoder_context->rate_control_mode = obj_config->attrib_list[i].value; if (encoder_context->codec == CODEC_MPEG2 && encoder_context->rate_control_mode & VA_RC_CBR) { WARN_ONCE("Don't support CBR for MPEG-2 encoding\n"); encoder_context->rate_control_mode &= ~VA_RC_CBR; } break; } } vme_context_init(ctx, encoder_context); assert(encoder_context->vme_context); assert(encoder_context->vme_context_destroy); assert(encoder_context->vme_pipeline); mfc_context_init(ctx, encoder_context); assert(encoder_context->mfc_context); assert(encoder_context->mfc_context_destroy); assert(encoder_context->mfc_pipeline); return (struct hw_context *)encoder_context; }