static int __devinit agp_intel_probe(struct pci_dev *pdev, const struct pci_device_id *ent) { struct agp_bridge_data *bridge; u8 cap_ptr = 0; struct resource *r; int i, err; cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); bridge = agp_alloc_bridge(); if (!bridge) return -ENOMEM; bridge->capndx = cap_ptr; if (intel_gmch_probe(pdev, bridge)) goto found_gmch; for (i = 0; intel_agp_chipsets[i].name != NULL; i++) { /* In case that multiple models of gfx chip may stand on same host bridge type, this can be sure we detect the right IGD. */ if (pdev->device == intel_agp_chipsets[i].chip_id) { bridge->driver = intel_agp_chipsets[i].driver; break; } } if (intel_agp_chipsets[i].name == NULL) { if (cap_ptr) dev_warn(&pdev->dev, "unsupported Intel chipset [%04x/%04x]\n", pdev->vendor, pdev->device); agp_put_bridge(bridge); return -ENODEV; } if (!bridge->driver) { if (cap_ptr) dev_warn(&pdev->dev, "can't find bridge device (chip_id: %04x)\n", intel_agp_chipsets[i].gmch_chip_id); agp_put_bridge(bridge); return -ENODEV; } bridge->dev = pdev; bridge->dev_private_data = NULL; dev_info(&pdev->dev, "Intel %s Chipset\n", intel_agp_chipsets[i].name); /* * If the device has not been properly setup, the following will catch * the problem and should stop the system from crashing. * 20030610 - [email protected] */ if (pci_enable_device(pdev)) { dev_err(&pdev->dev, "can't enable PCI device\n"); agp_put_bridge(bridge); return -ENODEV; } /* * The following fixes the case where the BIOS has "forgotten" to * provide an address range for the GART. * 20030610 - [email protected] */ r = &pdev->resource[0]; if (!r->start && r->end) { if (pci_assign_resource(pdev, 0)) { dev_err(&pdev->dev, "can't assign resource 0\n"); agp_put_bridge(bridge); return -ENODEV; } } /* Fill in the mode register */ if (cap_ptr) { pci_read_config_dword(pdev, bridge->capndx+PCI_AGP_STATUS, &bridge->mode); } found_gmch: pci_set_drvdata(pdev, bridge); err = agp_add_bridge(bridge); if (!err) intel_agp_enabled = 1; return err; }
static int __devinit agp_intel_probe(struct pci_dev *pdev, const struct pci_device_id *ent) { struct agp_bridge_data *bridge; u8 cap_ptr = 0; struct resource *r; int i, err; cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); bridge = agp_alloc_bridge(); if (!bridge) return -ENOMEM; bridge->capndx = cap_ptr; if (intel_gmch_probe(pdev, bridge)) goto found_gmch; for (i = 0; intel_agp_chipsets[i].name != NULL; i++) { if (pdev->device == intel_agp_chipsets[i].chip_id) { bridge->driver = intel_agp_chipsets[i].driver; break; } } if (!bridge->driver) { if (cap_ptr) dev_warn(&pdev->dev, "unsupported Intel chipset [%04x/%04x]\n", pdev->vendor, pdev->device); agp_put_bridge(bridge); return -ENODEV; } bridge->dev = pdev; bridge->dev_private_data = NULL; dev_info(&pdev->dev, "Intel %s Chipset\n", intel_agp_chipsets[i].name); r = &pdev->resource[0]; if (!r->start && r->end) { if (pci_assign_resource(pdev, 0)) { dev_err(&pdev->dev, "can't assign resource 0\n"); agp_put_bridge(bridge); return -ENODEV; } } if (pci_enable_device(pdev)) { dev_err(&pdev->dev, "can't enable PCI device\n"); agp_put_bridge(bridge); return -ENODEV; } if (cap_ptr) { pci_read_config_dword(pdev, bridge->capndx+PCI_AGP_STATUS, &bridge->mode); } found_gmch: pci_set_drvdata(pdev, bridge); err = agp_add_bridge(bridge); if (!err) intel_agp_enabled = 1; return err; }