void
intel_resolve_for_dri2_flush(struct brw_context *brw,
__DRIdrawable *drawable)
{
if (brw->gen < 6) {
/* MSAA and fast color clear are not supported, so don't waste time
* checking whether a resolve is needed.
*/
return;
}
struct gl_framebuffer *fb = drawable->driverPrivate;
struct intel_renderbuffer *rb;
/* Usually, only the back buffer will need to be downsampled. However,
* the front buffer will also need it if the user has rendered into it.
*/
static const gl_buffer_index buffers[2] = {
BUFFER_BACK_LEFT,
BUFFER_FRONT_LEFT,
};
for (int i = 0; i < 2; ++i) {
rb = intel_get_renderbuffer(fb, buffers[i]);
if (rb == NULL || rb->mt == NULL)
continue;
if (rb->mt->num_samples <= 1)
intel_miptree_resolve_color(brw, rb->mt);
else
intel_miptree_downsample(brw, rb->mt);
}
}
/*
* \brief Resolve buffers before drawing.
*
* Resolve the depth buffer's HiZ buffer and resolve the depth buffer of each
* enabled depth texture.
*
* (In the future, this will also perform MSAA resolves).
*/
static void
brw_predraw_resolve_buffers(struct brw_context *brw)
{
struct gl_context *ctx = &brw->ctx;
struct intel_renderbuffer *depth_irb;
struct intel_texture_object *tex_obj;
/* Resolve the depth buffer's HiZ buffer. */
depth_irb = intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_DEPTH);
if (depth_irb)
intel_renderbuffer_resolve_hiz(brw, depth_irb);
/* Resolve depth buffer of each enabled depth texture, and color buffer of
* each fast-clear-enabled color texture.
*/
for (int i = 0; i < BRW_MAX_TEX_UNIT; i++) {
if (!ctx->Texture.Unit[i]._ReallyEnabled)
continue;
tex_obj = intel_texture_object(ctx->Texture.Unit[i]._Current);
if (!tex_obj || !tex_obj->mt)
continue;
intel_miptree_all_slices_resolve_depth(brw, tex_obj->mt);
intel_miptree_resolve_color(brw, tex_obj->mt);
}
}
/**
* Implements a rectangular block transfer (blit) of pixels between two
* miptrees.
*
* Our blitter can operate on 1, 2, or 4-byte-per-pixel data, with generous,
* but limited, pitches and sizes allowed.
*
* The src/dst coordinates are relative to the given level/slice of the
* miptree.
*
* If @src_flip or @dst_flip is set, then the rectangle within that miptree
* will be inverted (including scanline order) when copying. This is common
* in GL when copying between window system and user-created
* renderbuffers/textures.
*/
bool
intel_miptree_blit(struct brw_context *brw,
struct intel_mipmap_tree *src_mt,
int src_level, int src_slice,
uint32_t src_x, uint32_t src_y, bool src_flip,
struct intel_mipmap_tree *dst_mt,
int dst_level, int dst_slice,
uint32_t dst_x, uint32_t dst_y, bool dst_flip,
uint32_t width, uint32_t height,
GLenum logicop)
{
/* No sRGB decode or encode is done by the hardware blitter, which is
* consistent with what we want in the callers (glCopyTexSubImage(),
* glBlitFramebuffer(), texture validation, etc.).
*/
gl_format src_format = _mesa_get_srgb_format_linear(src_mt->format);
gl_format dst_format = _mesa_get_srgb_format_linear(dst_mt->format);
/* The blitter doesn't support doing any format conversions. We do also
* support blitting ARGB8888 to XRGB8888 (trivial, the values dropped into
* the X channel don't matter), and XRGB8888 to ARGB8888 by setting the A
* channel to 1.0 at the end.
*/
if (src_format != dst_format &&
((src_format != MESA_FORMAT_ARGB8888 &&
src_format != MESA_FORMAT_XRGB8888) ||
(dst_format != MESA_FORMAT_ARGB8888 &&
dst_format != MESA_FORMAT_XRGB8888))) {
perf_debug("%s: Can't use hardware blitter from %s to %s, "
"falling back.\n", __FUNCTION__,
_mesa_get_format_name(src_format),
_mesa_get_format_name(dst_format));
return false;
}
/* According to the Ivy Bridge PRM, Vol1 Part4, section 1.2.1.2 (Graphics
* Data Size Limitations):
*
* The BLT engine is capable of transferring very large quantities of
* graphics data. Any graphics data read from and written to the
* destination is permitted to represent a number of pixels that
* occupies up to 65,536 scan lines and up to 32,768 bytes per scan line
* at the destination. The maximum number of pixels that may be
* represented per scan line’s worth of graphics data depends on the
* color depth.
*
* Furthermore, intelEmitCopyBlit (which is called below) uses a signed
* 16-bit integer to represent buffer pitch, so it can only handle buffer
* pitches < 32k.
*
* As a result of these two limitations, we can only use the blitter to do
* this copy when the region's pitch is less than 32k.
*/
if (src_mt->region->pitch > 32768 ||
dst_mt->region->pitch > 32768) {
perf_debug("Falling back due to >32k pitch\n");
return false;
}
/* The blitter has no idea about HiZ or fast color clears, so we need to
* resolve the miptrees before we do anything.
*/
intel_miptree_slice_resolve_depth(brw, src_mt, src_level, src_slice);
intel_miptree_slice_resolve_depth(brw, dst_mt, dst_level, dst_slice);
intel_miptree_resolve_color(brw, src_mt);
intel_miptree_resolve_color(brw, dst_mt);
if (src_flip)
src_y = src_mt->level[src_level].height - src_y - height;
if (dst_flip)
dst_y = dst_mt->level[dst_level].height - dst_y - height;
int src_pitch = src_mt->region->pitch;
if (src_flip != dst_flip)
src_pitch = -src_pitch;
uint32_t src_image_x, src_image_y;
intel_miptree_get_image_offset(src_mt, src_level, src_slice,
&src_image_x, &src_image_y);
src_x += src_image_x;
src_y += src_image_y;
uint32_t dst_image_x, dst_image_y;
intel_miptree_get_image_offset(dst_mt, dst_level, dst_slice,
&dst_image_x, &dst_image_y);
dst_x += dst_image_x;
dst_y += dst_image_y;
if (!intelEmitCopyBlit(brw,
src_mt->cpp,
src_pitch,
src_mt->region->bo, src_mt->offset,
src_mt->region->tiling,
dst_mt->region->pitch,
dst_mt->region->bo, dst_mt->offset,
dst_mt->region->tiling,
src_x, src_y,
dst_x, dst_y,
width, height,
logicop)) {
return false;
}
if (src_mt->format == MESA_FORMAT_XRGB8888 &&
dst_mt->format == MESA_FORMAT_ARGB8888) {
intel_miptree_set_alpha_to_one(brw, dst_mt,
dst_x, dst_y,
width, height);
}
return true;
}
/**
* \brief A fast path for glGetTexImage.
*
* \see intel_readpixels_tiled_memcpy()
*/
bool
intel_gettexsubimage_tiled_memcpy(struct gl_context *ctx,
struct gl_texture_image *texImage,
GLint xoffset, GLint yoffset,
GLsizei width, GLsizei height,
GLenum format, GLenum type,
GLvoid *pixels,
const struct gl_pixelstore_attrib *packing)
{
struct brw_context *brw = brw_context(ctx);
struct intel_texture_image *image = intel_texture_image(texImage);
int dst_pitch;
/* The miptree's buffer. */
drm_intel_bo *bo;
int error = 0;
uint32_t cpp;
mem_copy_fn mem_copy = NULL;
/* This fastpath is restricted to specific texture types:
* a 2D BGRA, RGBA, L8 or A8 texture. It could be generalized to support
* more types.
*
* FINISHME: The restrictions below on packing alignment and packing row
* length are likely unneeded now because we calculate the destination stride
* with _mesa_image_row_stride. However, before removing the restrictions
* we need tests.
*/
if (!brw->has_llc ||
!(type == GL_UNSIGNED_BYTE || type == GL_UNSIGNED_INT_8_8_8_8_REV) ||
!(texImage->TexObject->Target == GL_TEXTURE_2D ||
texImage->TexObject->Target == GL_TEXTURE_RECTANGLE) ||
pixels == NULL ||
_mesa_is_bufferobj(packing->BufferObj) ||
packing->Alignment > 4 ||
packing->SkipPixels > 0 ||
packing->SkipRows > 0 ||
(packing->RowLength != 0 && packing->RowLength != width) ||
packing->SwapBytes ||
packing->LsbFirst ||
packing->Invert)
return false;
/* We can't handle copying from RGBX or BGRX because the tiled_memcpy
* function doesn't set the last channel to 1.
*/
if (texImage->TexFormat == MESA_FORMAT_B8G8R8X8_UNORM ||
texImage->TexFormat == MESA_FORMAT_R8G8B8X8_UNORM)
return false;
if (!intel_get_memcpy(texImage->TexFormat, format, type, &mem_copy, &cpp,
INTEL_DOWNLOAD))
return false;
/* If this is a nontrivial texture view, let another path handle it instead. */
if (texImage->TexObject->MinLayer)
return false;
if (!image->mt ||
(image->mt->tiling != I915_TILING_X &&
image->mt->tiling != I915_TILING_Y)) {
/* The algorithm is written only for X- or Y-tiled memory. */
return false;
}
/* Since we are going to write raw data to the miptree, we need to resolve
* any pending fast color clears before we start.
*/
intel_miptree_resolve_color(brw, image->mt);
bo = image->mt->bo;
if (drm_intel_bo_references(brw->batch.bo, bo)) {
perf_debug("Flushing before mapping a referenced bo.\n");
intel_batchbuffer_flush(brw);
}
error = brw_bo_map(brw, bo, false /* write enable */, "miptree");
if (error) {
DBG("%s: failed to map bo\n", __func__);
return false;
}
dst_pitch = _mesa_image_row_stride(packing, width, format, type);
DBG("%s: level=%d x,y=(%d,%d) (w,h)=(%d,%d) format=0x%x type=0x%x "
"mesa_format=0x%x tiling=%d "
"packing=(alignment=%d row_length=%d skip_pixels=%d skip_rows=%d)\n",
__func__, texImage->Level, xoffset, yoffset, width, height,
format, type, texImage->TexFormat, image->mt->tiling,
packing->Alignment, packing->RowLength, packing->SkipPixels,
packing->SkipRows);
int level = texImage->Level + texImage->TexObject->MinLevel;
/* Adjust x and y offset based on miplevel */
xoffset += image->mt->level[level].level_x;
yoffset += image->mt->level[level].level_y;
tiled_to_linear(
xoffset * cpp, (xoffset + width) * cpp,
yoffset, yoffset + height,
pixels - (ptrdiff_t) yoffset * dst_pitch - (ptrdiff_t) xoffset * cpp,
bo->virtual,
dst_pitch, image->mt->pitch,
brw->has_swizzling,
image->mt->tiling,
mem_copy
);
drm_intel_bo_unmap(bo);
return true;
}
static void
intel_copy_image_sub_data(struct gl_context *ctx,
struct gl_texture_image *src_image,
int src_x, int src_y, int src_z,
struct gl_texture_image *dst_image,
int dst_x, int dst_y, int dst_z,
int src_width, int src_height)
{
struct brw_context *brw = brw_context(ctx);
struct intel_texture_image *intel_src_image = intel_texture_image(src_image);
struct intel_texture_image *intel_dst_image = intel_texture_image(dst_image);
if (_mesa_meta_CopyImageSubData_uncompressed(ctx,
src_image, src_x, src_y, src_z,
dst_image, dst_x, dst_y, dst_z,
src_width, src_height)) {
return;
}
if (intel_src_image->mt->num_samples > 0 ||
intel_dst_image->mt->num_samples > 0) {
_mesa_problem(ctx, "Failed to copy multisampled texture with meta path\n");
return;
}
/* Cube maps actually have different images per face */
if (src_image->TexObject->Target == GL_TEXTURE_CUBE_MAP)
src_z = src_image->Face;
if (dst_image->TexObject->Target == GL_TEXTURE_CUBE_MAP)
dst_z = dst_image->Face;
/* We are now going to try and copy the texture using the blitter. If
* that fails, we will fall back mapping the texture and using memcpy.
* In either case, we need to do a full resolve.
*/
intel_miptree_all_slices_resolve_hiz(brw, intel_src_image->mt);
intel_miptree_all_slices_resolve_depth(brw, intel_src_image->mt);
intel_miptree_resolve_color(brw, intel_src_image->mt);
intel_miptree_all_slices_resolve_hiz(brw, intel_dst_image->mt);
intel_miptree_all_slices_resolve_depth(brw, intel_dst_image->mt);
intel_miptree_resolve_color(brw, intel_dst_image->mt);
unsigned src_level = src_image->Level + src_image->TexObject->MinLevel;
unsigned dst_level = dst_image->Level + dst_image->TexObject->MinLevel;
if (copy_image_with_blitter(brw, intel_src_image->mt, src_level,
src_x, src_y, src_z,
intel_dst_image->mt, dst_level,
dst_x, dst_y, dst_z,
src_width, src_height))
return;
/* This is a worst-case scenario software fallback that maps the two
* textures and does a memcpy between them.
*/
copy_image_with_memcpy(brw, intel_src_image->mt, src_level,
src_x, src_y, src_z,
intel_dst_image->mt, dst_level,
dst_x, dst_y, dst_z,
src_width, src_height);
}
/*
* Render a bitmap.
*/
static bool
do_blit_bitmap( struct gl_context *ctx,
GLint dstx, GLint dsty,
GLsizei width, GLsizei height,
const struct gl_pixelstore_attrib *unpack,
const GLubyte *bitmap )
{
struct brw_context *brw = brw_context(ctx);
struct gl_framebuffer *fb = ctx->DrawBuffer;
struct intel_renderbuffer *irb;
GLfloat tmpColor[4];
GLubyte ubcolor[4];
GLuint color;
GLsizei bitmap_width = width;
GLsizei bitmap_height = height;
GLint px, py;
GLuint stipple[32];
GLint orig_dstx = dstx;
GLint orig_dsty = dsty;
/* Update draw buffer bounds */
_mesa_update_state(ctx);
if (ctx->Depth.Test) {
/* The blit path produces incorrect results when depth testing is on.
* It seems the blit Z coord is always 1.0 (the far plane) so fragments
* will likely be obscured by other, closer geometry.
*/
return false;
}
intel_prepare_render(brw);
if (fb->_NumColorDrawBuffers != 1) {
perf_debug("accelerated glBitmap() only supports rendering to a "
"single color buffer\n");
return false;
}
irb = intel_renderbuffer(fb->_ColorDrawBuffers[0]);
if (_mesa_is_bufferobj(unpack->BufferObj)) {
bitmap = map_pbo(ctx, width, height, unpack, bitmap);
if (bitmap == NULL)
return true; /* even though this is an error, we're done */
}
COPY_4V(tmpColor, ctx->Current.RasterColor);
if (_mesa_need_secondary_color(ctx)) {
ADD_3V(tmpColor, tmpColor, ctx->Current.RasterSecondaryColor);
}
UNCLAMPED_FLOAT_TO_UBYTE(ubcolor[0], tmpColor[0]);
UNCLAMPED_FLOAT_TO_UBYTE(ubcolor[1], tmpColor[1]);
UNCLAMPED_FLOAT_TO_UBYTE(ubcolor[2], tmpColor[2]);
UNCLAMPED_FLOAT_TO_UBYTE(ubcolor[3], tmpColor[3]);
switch (_mesa_get_render_format(ctx, intel_rb_format(irb))) {
case MESA_FORMAT_ARGB8888:
case MESA_FORMAT_XRGB8888:
color = PACK_COLOR_8888(ubcolor[3], ubcolor[0], ubcolor[1], ubcolor[2]);
break;
case MESA_FORMAT_RGB565:
color = PACK_COLOR_565(ubcolor[0], ubcolor[1], ubcolor[2]);
break;
default:
perf_debug("Unsupported format %s in accelerated glBitmap()\n",
_mesa_get_format_name(irb->mt->format));
return false;
}
if (!intel_check_blit_fragment_ops(ctx, tmpColor[3] == 1.0F))
return false;
/* Clip to buffer bounds and scissor. */
if (!_mesa_clip_to_region(fb->_Xmin, fb->_Ymin,
fb->_Xmax, fb->_Ymax,
&dstx, &dsty, &width, &height))
goto out;
dsty = y_flip(fb, dsty, height);
#define DY 32
#define DX 32
/* The blitter has no idea about fast color clears, so we need to resolve
* the miptree before we do anything.
*/
intel_miptree_resolve_color(brw, irb->mt);
/* Chop it all into chunks that can be digested by hardware: */
for (py = 0; py < height; py += DY) {
for (px = 0; px < width; px += DX) {
int h = MIN2(DY, height - py);
int w = MIN2(DX, width - px);
GLuint sz = ALIGN(ALIGN(w,8) * h, 64)/8;
GLenum logic_op = ctx->Color.ColorLogicOpEnabled ?
ctx->Color.LogicOp : GL_COPY;
assert(sz <= sizeof(stipple));
memset(stipple, 0, sz);
/* May need to adjust this when padding has been introduced in
* sz above:
*
* Have to translate destination coordinates back into source
* coordinates.
*/
int count = get_bitmap_rect(bitmap_width, bitmap_height, unpack,
bitmap,
-orig_dstx + (dstx + px),
-orig_dsty + y_flip(fb, dsty + py, h),
w, h,
(GLubyte *)stipple,
8,
_mesa_is_winsys_fbo(fb));
if (count == 0)
continue;
if (!intelEmitImmediateColorExpandBlit(brw,
irb->mt->cpp,
(GLubyte *)stipple,
sz,
color,
irb->mt->region->pitch,
irb->mt->region->bo,
0,
irb->mt->region->tiling,
dstx + px,
dsty + py,
w, h,
logic_op)) {
return false;
}
if (ctx->Query.CurrentOcclusionObject)
ctx->Query.CurrentOcclusionObject->Result += count;
}
}
out:
if (unlikely(INTEL_DEBUG & DEBUG_SYNC))
intel_batchbuffer_flush(brw);
if (_mesa_is_bufferobj(unpack->BufferObj)) {
/* done with PBO so unmap it now */
ctx->Driver.UnmapBuffer(ctx, unpack->BufferObj);
}
intel_check_front_buffer_rendering(brw);
return true;
}
static void
blorp_surf_for_miptree(struct brw_context *brw,
struct blorp_surf *surf,
struct intel_mipmap_tree *mt,
bool is_render_target,
uint32_t safe_aux_usage,
unsigned *level,
unsigned start_layer, unsigned num_layers,
struct isl_surf tmp_surfs[2])
{
if (mt->msaa_layout == INTEL_MSAA_LAYOUT_UMS ||
mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) {
const unsigned num_samples = MAX2(1, mt->num_samples);
for (unsigned i = 0; i < num_layers; i++) {
for (unsigned s = 0; s < num_samples; s++) {
const unsigned phys_layer = (start_layer + i) * num_samples + s;
intel_miptree_check_level_layer(mt, *level, phys_layer);
}
}
} else {
for (unsigned i = 0; i < num_layers; i++)
intel_miptree_check_level_layer(mt, *level, start_layer + i);
}
intel_miptree_get_isl_surf(brw, mt, &tmp_surfs[0]);
surf->surf = &tmp_surfs[0];
surf->addr = (struct blorp_address) {
.buffer = mt->bo,
.offset = mt->offset,
.read_domains = is_render_target ? I915_GEM_DOMAIN_RENDER :
I915_GEM_DOMAIN_SAMPLER,
.write_domain = is_render_target ? I915_GEM_DOMAIN_RENDER : 0,
};
if (brw->gen == 6 && mt->format == MESA_FORMAT_S_UINT8 &&
mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
/* Sandy bridge stencil and HiZ use this ALL_SLICES_AT_EACH_LOD hack in
* order to allow for layered rendering. The hack makes each LOD of the
* stencil or HiZ buffer a single tightly packed array surface at some
* offset into the surface. Since ISL doesn't know how to deal with the
* crazy ALL_SLICES_AT_EACH_LOD layout and since we have to do a manual
* offset of it anyway, we might as well do the offset here and keep the
* hacks inside the i965 driver.
*
* See also gen6_depth_stencil_state.c
*/
uint32_t offset;
apply_gen6_stencil_hiz_offset(&tmp_surfs[0], mt, *level, &offset);
surf->addr.offset += offset;
*level = 0;
}
struct isl_surf *aux_surf = &tmp_surfs[1];
intel_miptree_get_aux_isl_surf(brw, mt, aux_surf, &surf->aux_usage);
if (surf->aux_usage != ISL_AUX_USAGE_NONE) {
if (surf->aux_usage == ISL_AUX_USAGE_HIZ) {
/* If we're not going to use it as a depth buffer, resolve HiZ */
if (!(safe_aux_usage & (1 << ISL_AUX_USAGE_HIZ))) {
for (unsigned i = 0; i < num_layers; i++) {
intel_miptree_slice_resolve_depth(brw, mt, *level,
start_layer + i);
/* If we're rendering to it then we'll need a HiZ resolve once
* we're done before we can use it with HiZ again.
*/
if (is_render_target)
intel_miptree_slice_set_needs_hiz_resolve(mt, *level,
start_layer + i);
}
surf->aux_usage = ISL_AUX_USAGE_NONE;
}
} else if (!(safe_aux_usage & (1 << surf->aux_usage))) {
uint32_t flags = 0;
if (safe_aux_usage & (1 << ISL_AUX_USAGE_CCS_E))
flags |= INTEL_MIPTREE_IGNORE_CCS_E;
intel_miptree_resolve_color(brw, mt,
*level, start_layer, num_layers, flags);
assert(!intel_miptree_has_color_unresolved(mt, *level, 1,
start_layer, num_layers));
surf->aux_usage = ISL_AUX_USAGE_NONE;
}
}
if (is_render_target)
intel_miptree_used_for_rendering(brw, mt, *level,
start_layer, num_layers);
if (surf->aux_usage != ISL_AUX_USAGE_NONE) {
/* We only really need a clear color if we also have an auxiliary
* surface. Without one, it does nothing.
*/
surf->clear_color = intel_miptree_get_isl_clear_color(brw, mt);
surf->aux_surf = aux_surf;
surf->aux_addr = (struct blorp_address) {
.read_domains = is_render_target ? I915_GEM_DOMAIN_RENDER :
I915_GEM_DOMAIN_SAMPLER,
.write_domain = is_render_target ? I915_GEM_DOMAIN_RENDER : 0,
};
if (mt->mcs_buf) {
surf->aux_addr.buffer = mt->mcs_buf->bo;
surf->aux_addr.offset = mt->mcs_buf->offset;
} else {
assert(surf->aux_usage == ISL_AUX_USAGE_HIZ);
struct intel_mipmap_tree *hiz_mt = mt->hiz_buf->mt;
if (hiz_mt) {
surf->aux_addr.buffer = hiz_mt->bo;
if (brw->gen == 6 &&
hiz_mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
/* gen6 requires the HiZ buffer to be manually offset to the
* right location. We could fixup the surf but it doesn't
* matter since most of those fields don't matter.
*/
apply_gen6_stencil_hiz_offset(aux_surf, hiz_mt, *level,
&surf->aux_addr.offset);
} else {
surf->aux_addr.offset = 0;
}
assert(hiz_mt->pitch == aux_surf->row_pitch);
} else {
surf->aux_addr.buffer = mt->hiz_buf->aux_base.bo;
surf->aux_addr.offset = mt->hiz_buf->aux_base.offset;
}
}
} else {
surf->aux_addr = (struct blorp_address) {
.buffer = NULL,
};
memset(&surf->clear_color, 0, sizeof(surf->clear_color));
}
assert((surf->aux_usage == ISL_AUX_USAGE_NONE) ==
(surf->aux_addr.buffer == NULL));
}
/**
* \brief A fast path for glReadPixels
*
* This fast path is taken when the source format is BGRA, RGBA,
* A or L and when the texture memory is X- or Y-tiled. It downloads
* the source data by directly mapping the memory without a GTT fence.
* This then needs to be de-tiled on the CPU before presenting the data to
* the user in the linear fasion.
*
* This is a performance win over the conventional texture download path.
* In the conventional texture download path, the texture is either mapped
* through the GTT or copied to a linear buffer with the blitter before
* handing off to a software path. This allows us to avoid round-tripping
* through the GPU (in the case where we would be blitting) and do only a
* single copy operation.
*/
static bool
intel_readpixels_tiled_memcpy(struct gl_context * ctx,
GLint xoffset, GLint yoffset,
GLsizei width, GLsizei height,
GLenum format, GLenum type,
GLvoid * pixels,
const struct gl_pixelstore_attrib *pack)
{
struct brw_context *brw = brw_context(ctx);
struct gl_renderbuffer *rb = ctx->ReadBuffer->_ColorReadBuffer;
/* This path supports reading from color buffers only */
if (rb == NULL)
return false;
struct intel_renderbuffer *irb = intel_renderbuffer(rb);
int dst_pitch;
/* The miptree's buffer. */
drm_intel_bo *bo;
int error = 0;
uint32_t cpp;
mem_copy_fn mem_copy = NULL;
/* This fastpath is restricted to specific renderbuffer types:
* a 2D BGRA, RGBA, L8 or A8 texture. It could be generalized to support
* more types.
*/
if (!brw->has_llc ||
!(type == GL_UNSIGNED_BYTE || type == GL_UNSIGNED_INT_8_8_8_8_REV) ||
pixels == NULL ||
_mesa_is_bufferobj(pack->BufferObj) ||
pack->Alignment > 4 ||
pack->SkipPixels > 0 ||
pack->SkipRows > 0 ||
(pack->RowLength != 0 && pack->RowLength != width) ||
pack->SwapBytes ||
pack->LsbFirst ||
pack->Invert)
return false;
/* Only a simple blit, no scale, bias or other mapping. */
if (ctx->_ImageTransferState)
return false;
/* This renderbuffer can come from a texture. In this case, we impose
* some of the same restrictions we have for textures and adjust for
* miplevels.
*/
if (rb->TexImage) {
if (rb->TexImage->TexObject->Target != GL_TEXTURE_2D &&
rb->TexImage->TexObject->Target != GL_TEXTURE_RECTANGLE)
return false;
int level = rb->TexImage->Level + rb->TexImage->TexObject->MinLevel;
/* Adjust x and y offset based on miplevel */
xoffset += irb->mt->level[level].level_x;
yoffset += irb->mt->level[level].level_y;
}
/* It is possible that the renderbuffer (or underlying texture) is
* multisampled. Since ReadPixels from a multisampled buffer requires a
* multisample resolve, we can't handle this here
*/
if (rb->NumSamples > 1)
return false;
/* We can't handle copying from RGBX or BGRX because the tiled_memcpy
* function doesn't set the last channel to 1. Note this checks BaseFormat
* rather than TexFormat in case the RGBX format is being simulated with an
* RGBA format.
*/
if (rb->_BaseFormat == GL_RGB)
return false;
if (!intel_get_memcpy(rb->Format, format, type, &mem_copy, &cpp,
INTEL_DOWNLOAD))
return false;
if (!irb->mt ||
(irb->mt->tiling != I915_TILING_X &&
irb->mt->tiling != I915_TILING_Y)) {
/* The algorithm is written only for X- or Y-tiled memory. */
return false;
}
/* Since we are going to read raw data to the miptree, we need to resolve
* any pending fast color clears before we start.
*/
intel_miptree_resolve_color(brw, irb->mt);
bo = irb->mt->bo;
if (drm_intel_bo_references(brw->batch.bo, bo)) {
perf_debug("Flushing before mapping a referenced bo.\n");
intel_batchbuffer_flush(brw);
}
error = brw_bo_map(brw, bo, false /* write enable */, "miptree");
if (error) {
DBG("%s: failed to map bo\n", __func__);
return false;
}
dst_pitch = _mesa_image_row_stride(pack, width, format, type);
/* For a window-system renderbuffer, the buffer is actually flipped
* vertically, so we need to handle that. Since the detiling function
* can only really work in the forwards direction, we have to be a
* little creative. First, we compute the Y-offset of the first row of
* the renderbuffer (in renderbuffer coordinates). We then match that
* with the last row of the client's data. Finally, we give
* tiled_to_linear a negative pitch so that it walks through the
* client's data backwards as it walks through the renderbufer forwards.
*/
if (rb->Name == 0) {
yoffset = rb->Height - yoffset - height;
pixels += (ptrdiff_t) (height - 1) * dst_pitch;
dst_pitch = -dst_pitch;
}
/* We postponed printing this message until having committed to executing
* the function.
*/
DBG("%s: x,y=(%d,%d) (w,h)=(%d,%d) format=0x%x type=0x%x "
"mesa_format=0x%x tiling=%d "
"pack=(alignment=%d row_length=%d skip_pixels=%d skip_rows=%d)\n",
__func__, xoffset, yoffset, width, height,
format, type, rb->Format, irb->mt->tiling,
pack->Alignment, pack->RowLength, pack->SkipPixels,
pack->SkipRows);
tiled_to_linear(
xoffset * cpp, (xoffset + width) * cpp,
yoffset, yoffset + height,
pixels - (ptrdiff_t) yoffset * dst_pitch - (ptrdiff_t) xoffset * cpp,
bo->virtual,
dst_pitch, irb->mt->pitch,
brw->has_swizzling,
irb->mt->tiling,
mem_copy
);
drm_intel_bo_unmap(bo);
return true;
}
