static void skl_power_well_post_enable(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { struct drm_device *dev = dev_priv->dev; /* * After we re-enable the power well, if we touch VGA register 0x3d5 * we'll get unclaimed register interrupts. This stops after we write * anything to the VGA MSR register. The vgacon module uses this * register all the time, so if we unbind our driver and, as a * consequence, bind vgacon, we'll get stuck in an infinite loop at * console_unlock(). So make here we touch the VGA MSR register, making * sure vgacon can keep working normally without triggering interrupts * and error messages. */ if (power_well->data == SKL_DISP_PW_2) { vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); outb(inb(VGA_MSR_READ), VGA_MSR_WRITE); vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); gen8_irq_power_well_post_enable(dev_priv, 1 << PIPE_C | 1 << PIPE_B); } if (power_well->data == SKL_DISP_PW_1) { intel_prepare_ddi(dev); gen8_irq_power_well_post_enable(dev_priv, 1 << PIPE_A); } }
static int bxt_resume_prepare(struct drm_i915_private *dev_priv) { struct drm_device *dev = dev_priv->dev; /* TODO: when CSR FW support is added make sure the FW is loaded */ bxt_disable_dc9(dev_priv); /* * TODO: when DC5 support is added enable DC5 here if the CSR FW * is available. */ broxton_init_cdclk(dev); broxton_ddi_phy_init(dev); intel_prepare_ddi(dev); return 0; }