/** * Creates the state cache entry for the given DEPTH_STENCIL_STATE state key. */ static drm_intel_bo * depth_stencil_state_create_from_key(struct brw_context *brw, struct brw_depth_stencil_state_key *key) { struct gen6_depth_stencil_state ds; drm_intel_bo *bo; memset(&ds, 0, sizeof(ds)); /* _NEW_STENCIL */ if (key->stencil) { ds.ds0.stencil_enable = 1; ds.ds0.stencil_func = intel_translate_compare_func(key->stencil_func[0]); ds.ds0.stencil_fail_op = intel_translate_stencil_op(key->stencil_fail_op[0]); ds.ds0.stencil_pass_depth_fail_op = intel_translate_stencil_op(key->stencil_pass_depth_fail_op[0]); ds.ds0.stencil_pass_depth_pass_op = intel_translate_stencil_op(key->stencil_pass_depth_pass_op[0]); ds.ds1.stencil_write_mask = key->stencil_write_mask[0]; ds.ds1.stencil_test_mask = key->stencil_test_mask[0]; if (key->stencil_two_side) { ds.ds0.bf_stencil_enable = 1; ds.ds0.bf_stencil_func = intel_translate_compare_func(key->stencil_func[1]); ds.ds0.bf_stencil_fail_op = intel_translate_stencil_op(key->stencil_fail_op[1]); ds.ds0.bf_stencil_pass_depth_fail_op = intel_translate_stencil_op(key->stencil_pass_depth_fail_op[1]); ds.ds0.bf_stencil_pass_depth_pass_op = intel_translate_stencil_op(key->stencil_pass_depth_pass_op[1]); ds.ds1.bf_stencil_write_mask = key->stencil_write_mask[1]; ds.ds1.bf_stencil_test_mask = key->stencil_test_mask[1]; } /* Not really sure about this: */ if (key->stencil_write_mask[0] || (key->stencil_two_side && key->stencil_write_mask[1])) ds.ds0.stencil_write_enable = 1; } /* _NEW_DEPTH */ if (key->depth_test) { ds.ds2.depth_test_enable = 1; ds.ds2.depth_test_func = intel_translate_compare_func(key->depth_func); ds.ds2.depth_write_enable = key->depth_write; } bo = brw_upload_cache(&brw->cache, BRW_DEPTH_STENCIL_STATE, key, sizeof(*key), NULL, 0, &ds, sizeof(ds)); return bo; }
static void i830StencilFuncSeparate(GLcontext *ctx, GLenum face, GLenum func, GLint ref, GLuint mask) { i830ContextPtr i830 = I830_CONTEXT(ctx); int test = intel_translate_compare_func(func); mask = mask & 0xff; if (INTEL_DEBUG&DEBUG_DRI) fprintf(stderr, "%s : func: %s, ref : 0x%x, mask: 0x%x\n", __FUNCTION__, _mesa_lookup_enum_by_nr(func), ref, mask); I830_STATECHANGE(i830, I830_UPLOAD_CTX); i830->state.Ctx[I830_CTXREG_STATE4] &= ~MODE4_ENABLE_STENCIL_TEST_MASK; i830->state.Ctx[I830_CTXREG_STATE4] |= (ENABLE_STENCIL_TEST_MASK | STENCIL_TEST_MASK(mask)); i830->state.Ctx[I830_CTXREG_STENCILTST] &= ~(STENCIL_REF_VALUE_MASK | ENABLE_STENCIL_TEST_FUNC_MASK); i830->state.Ctx[I830_CTXREG_STENCILTST] |= (ENABLE_STENCIL_REF_VALUE | ENABLE_STENCIL_TEST_FUNC | STENCIL_REF_VALUE(ref) | STENCIL_TEST_FUNC(test)); }
static void i915StencilFuncSeparate(GLcontext * ctx, GLenum face, GLenum func, GLint ref, GLuint mask) { struct i915_context *i915 = I915_CONTEXT(ctx); int test = intel_translate_compare_func(func); mask = mask & 0xff; DBG("%s : func: %s, ref : 0x%x, mask: 0x%x\n", __FUNCTION__, _mesa_lookup_enum_by_nr(func), ref, mask); I915_STATECHANGE(i915, I915_UPLOAD_CTX); i915->state.Ctx[I915_CTXREG_STATE4] &= ~MODE4_ENABLE_STENCIL_TEST_MASK; i915->state.Ctx[I915_CTXREG_STATE4] |= (ENABLE_STENCIL_TEST_MASK | STENCIL_TEST_MASK(mask)); i915->state.Ctx[I915_CTXREG_LIS5] &= ~(S5_STENCIL_REF_MASK | S5_STENCIL_TEST_FUNC_MASK); i915->state.Ctx[I915_CTXREG_LIS5] |= ((ref << S5_STENCIL_REF_SHIFT) | (test << S5_STENCIL_TEST_FUNC_SHIFT)); }
static void i915DepthFunc(GLcontext * ctx, GLenum func) { struct i915_context *i915 = I915_CONTEXT(ctx); int test = intel_translate_compare_func(func); DBG("%s\n", __FUNCTION__); I915_STATECHANGE(i915, I915_UPLOAD_CTX); i915->state.Ctx[I915_CTXREG_LIS6] &= ~S6_DEPTH_TEST_FUNC_MASK; i915->state.Ctx[I915_CTXREG_LIS6] |= test << S6_DEPTH_TEST_FUNC_SHIFT; }
static void i830DepthFunc(struct gl_context * ctx, GLenum func) { struct i830_context *i830 = i830_context(ctx); int test = intel_translate_compare_func(func); DBG("%s\n", __FUNCTION__); I830_STATECHANGE(i830, I830_UPLOAD_CTX); i830->state.Ctx[I830_CTXREG_STATE3] &= ~DEPTH_TEST_FUNC_MASK; i830->state.Ctx[I830_CTXREG_STATE3] |= (ENABLE_DEPTH_TEST_FUNC | DEPTH_TEST_FUNC(test)); }
static void i830DepthFunc(GLcontext *ctx, GLenum func) { i830ContextPtr i830 = I830_CONTEXT(ctx); int test = intel_translate_compare_func(func); if (INTEL_DEBUG&DEBUG_DRI) fprintf(stderr, "%s\n", __FUNCTION__); I830_STATECHANGE(i830, I830_UPLOAD_CTX); i830->state.Ctx[I830_CTXREG_STATE3] &= ~DEPTH_TEST_FUNC_MASK; i830->state.Ctx[I830_CTXREG_STATE3] |= (ENABLE_DEPTH_TEST_FUNC | DEPTH_TEST_FUNC(test)); }
static void i915AlphaFunc(GLcontext * ctx, GLenum func, GLfloat ref) { struct i915_context *i915 = I915_CONTEXT(ctx); int test = intel_translate_compare_func(func); GLubyte refByte; UNCLAMPED_FLOAT_TO_UBYTE(refByte, ref); I915_STATECHANGE(i915, I915_UPLOAD_CTX); i915->state.Ctx[I915_CTXREG_LIS6] &= ~(S6_ALPHA_TEST_FUNC_MASK | S6_ALPHA_REF_MASK); i915->state.Ctx[I915_CTXREG_LIS6] |= ((test << S6_ALPHA_TEST_FUNC_SHIFT) | (((GLuint) refByte) << S6_ALPHA_REF_SHIFT)); }
static void i915DepthFunc(struct gl_context * ctx, GLenum func) { struct i915_context *i915 = I915_CONTEXT(ctx); int test = intel_translate_compare_func(func); GLuint dw; DBG("%s\n", __FUNCTION__); dw = i915->state.Ctx[I915_CTXREG_LIS6]; dw &= ~S6_DEPTH_TEST_FUNC_MASK; dw |= test << S6_DEPTH_TEST_FUNC_SHIFT; if (dw != i915->state.Ctx[I915_CTXREG_LIS6]) { I915_STATECHANGE(i915, I915_UPLOAD_CTX); i915->state.Ctx[I915_CTXREG_LIS6] = dw; } }
static void i830AlphaFunc(GLcontext *ctx, GLenum func, GLfloat ref) { i830ContextPtr i830 = I830_CONTEXT(ctx); int test = intel_translate_compare_func(func); GLubyte refByte; GLuint refInt; UNCLAMPED_FLOAT_TO_UBYTE(refByte, ref); refInt = (GLuint)refByte; I830_STATECHANGE(i830, I830_UPLOAD_CTX); i830->state.Ctx[I830_CTXREG_STATE2] &= ~ALPHA_TEST_REF_MASK; i830->state.Ctx[I830_CTXREG_STATE2] |= (ENABLE_ALPHA_TEST_FUNC | ENABLE_ALPHA_REF_VALUE | ALPHA_TEST_FUNC(test) | ALPHA_REF_VALUE(refInt)); }
static void i830StencilFuncSeparate(struct gl_context * ctx, GLenum face, GLenum func, GLint ref, GLuint mask) { struct i830_context *i830 = i830_context(ctx); int test = intel_translate_compare_func(func); mask = mask & 0xff; DBG("%s : func: %s, ref : 0x%x, mask: 0x%x\n", __FUNCTION__, _mesa_lookup_enum_by_nr(func), ref, mask); I830_STATECHANGE(i830, I830_UPLOAD_CTX); i830->state.Ctx[I830_CTXREG_STATE4] &= ~MODE4_ENABLE_STENCIL_TEST_MASK; i830->state.Ctx[I830_CTXREG_STATE4] |= (ENABLE_STENCIL_TEST_MASK | STENCIL_TEST_MASK(mask)); i830->state.Ctx[I830_CTXREG_STENCILTST] &= ~(STENCIL_REF_VALUE_MASK | ENABLE_STENCIL_TEST_FUNC_MASK); i830->state.Ctx[I830_CTXREG_STENCILTST] |= (ENABLE_STENCIL_REF_VALUE | ENABLE_STENCIL_TEST_FUNC | STENCIL_REF_VALUE(ref) | STENCIL_TEST_FUNC(test)); }
static void i915ImportTexObjState( struct gl_texture_object *texObj ) { i915TextureObjectPtr t = (i915TextureObjectPtr)texObj->DriverData; int minFilt = 0, mipFilt = 0, magFilt = 0, shadow = 0; if(INTEL_DEBUG&DEBUG_DRI) fprintf(stderr, "%s\n", __FUNCTION__); switch (texObj->MinFilter) { case GL_NEAREST: minFilt = FILTER_NEAREST; mipFilt = MIPFILTER_NONE; break; case GL_LINEAR: minFilt = FILTER_LINEAR; mipFilt = MIPFILTER_NONE; break; case GL_NEAREST_MIPMAP_NEAREST: minFilt = FILTER_NEAREST; mipFilt = MIPFILTER_NEAREST; break; case GL_LINEAR_MIPMAP_NEAREST: minFilt = FILTER_LINEAR; mipFilt = MIPFILTER_NEAREST; break; case GL_NEAREST_MIPMAP_LINEAR: minFilt = FILTER_NEAREST; mipFilt = MIPFILTER_LINEAR; break; case GL_LINEAR_MIPMAP_LINEAR: minFilt = FILTER_LINEAR; mipFilt = MIPFILTER_LINEAR; break; default: break; } if ( texObj->MaxAnisotropy > 1.0 ) { minFilt = FILTER_ANISOTROPIC; magFilt = FILTER_ANISOTROPIC; } else { switch (texObj->MagFilter) { case GL_NEAREST: magFilt = FILTER_NEAREST; break; case GL_LINEAR: magFilt = FILTER_LINEAR; break; default: break; } } if (texObj->CompareMode == GL_COMPARE_R_TO_TEXTURE_ARB && texObj->Target != GL_TEXTURE_3D) { shadow = SS2_SHADOW_ENABLE; shadow |= intel_translate_compare_func( texObj->CompareFunc ); minFilt = FILTER_4X4_FLAT; magFilt = FILTER_4X4_FLAT; } t->Setup[I915_TEXREG_SS2] &= ~(SS2_MIN_FILTER_MASK | SS2_MIP_FILTER_MASK | SS2_MAG_FILTER_MASK | SS2_SHADOW_ENABLE | SS2_SHADOW_FUNC_MASK); t->Setup[I915_TEXREG_SS2] |= ((minFilt << SS2_MIN_FILTER_SHIFT) | (mipFilt << SS2_MIP_FILTER_SHIFT) | (magFilt << SS2_MAG_FILTER_SHIFT) | shadow); { GLuint ss3 = t->Setup[I915_TEXREG_SS3] & ~(SS3_TCX_ADDR_MODE_MASK | SS3_TCY_ADDR_MODE_MASK | SS3_TCZ_ADDR_MODE_MASK); GLenum ws = texObj->WrapS; GLenum wt = texObj->WrapT; GLenum wr = texObj->WrapR; t->refs_border_color = 0; if (texObj->Target == GL_TEXTURE_3D && (texObj->MinFilter != GL_NEAREST || texObj->MagFilter != GL_NEAREST)) { /* Try to mimic GL_CLAMP functionality a little better - * switch to CLAMP_TO_BORDER whenever a non-NEAREST filter is * in use. Only do this for 3D textures at the moment -- * doing it universally would fix the conform texbc.c * failure, though. */ if (ws == GL_CLAMP) ws = GL_CLAMP_TO_BORDER; if (wt == GL_CLAMP) wt = GL_CLAMP_TO_BORDER; if (wr == GL_CLAMP) wr = GL_CLAMP_TO_BORDER; /* 3D textures don't seem to respect the border color. * Fallback if there's ever a danger that they might refer to * it. */ if (ws == GL_CLAMP_TO_BORDER) t->refs_border_color = 1; if (wt == GL_CLAMP_TO_BORDER) t->refs_border_color = 1; if (wr == GL_CLAMP_TO_BORDER) t->refs_border_color = 1; } ss3 |= translate_wrap_mode(ws) << SS3_TCX_ADDR_MODE_SHIFT; ss3 |= translate_wrap_mode(wt) << SS3_TCY_ADDR_MODE_SHIFT; ss3 |= translate_wrap_mode(wr) << SS3_TCZ_ADDR_MODE_SHIFT; if (ss3 != t->Setup[I915_TEXREG_SS3]) { t->intel.dirty = I915_UPLOAD_TEX_ALL; t->Setup[I915_TEXREG_SS3] = ss3; } } { const GLubyte *color = texObj->_BorderChan; t->Setup[I915_TEXREG_SS4] = INTEL_PACKCOLOR8888(color[0],color[1], color[2],color[3]); } }
/** * Creates the state cache entry for the given CC unit key. */ static void upload_cc_unit(struct brw_context *brw) { struct gl_context *ctx = &brw->ctx; struct brw_cc_unit_state *cc; cc = brw_state_batch(brw, AUB_TRACE_CC_STATE, sizeof(*cc), 64, &brw->cc.state_offset); memset(cc, 0, sizeof(*cc)); /* _NEW_STENCIL | _NEW_BUFFERS */ if (ctx->Stencil._Enabled) { const unsigned back = ctx->Stencil._BackFace; cc->cc0.stencil_enable = 1; cc->cc0.stencil_func = intel_translate_compare_func(ctx->Stencil.Function[0]); cc->cc0.stencil_fail_op = intel_translate_stencil_op(ctx->Stencil.FailFunc[0]); cc->cc0.stencil_pass_depth_fail_op = intel_translate_stencil_op(ctx->Stencil.ZFailFunc[0]); cc->cc0.stencil_pass_depth_pass_op = intel_translate_stencil_op(ctx->Stencil.ZPassFunc[0]); cc->cc1.stencil_ref = _mesa_get_stencil_ref(ctx, 0); cc->cc1.stencil_write_mask = ctx->Stencil.WriteMask[0]; cc->cc1.stencil_test_mask = ctx->Stencil.ValueMask[0]; if (ctx->Stencil._TestTwoSide) { cc->cc0.bf_stencil_enable = 1; cc->cc0.bf_stencil_func = intel_translate_compare_func(ctx->Stencil.Function[back]); cc->cc0.bf_stencil_fail_op = intel_translate_stencil_op(ctx->Stencil.FailFunc[back]); cc->cc0.bf_stencil_pass_depth_fail_op = intel_translate_stencil_op(ctx->Stencil.ZFailFunc[back]); cc->cc0.bf_stencil_pass_depth_pass_op = intel_translate_stencil_op(ctx->Stencil.ZPassFunc[back]); cc->cc1.bf_stencil_ref = _mesa_get_stencil_ref(ctx, back); cc->cc2.bf_stencil_write_mask = ctx->Stencil.WriteMask[back]; cc->cc2.bf_stencil_test_mask = ctx->Stencil.ValueMask[back]; } /* Not really sure about this: */ if (ctx->Stencil.WriteMask[0] || (ctx->Stencil._TestTwoSide && ctx->Stencil.WriteMask[back])) cc->cc0.stencil_write_enable = 1; } /* _NEW_COLOR */ if (ctx->Color.ColorLogicOpEnabled && ctx->Color.LogicOp != GL_COPY) { cc->cc2.logicop_enable = 1; cc->cc5.logicop_func = intel_translate_logic_op(ctx->Color.LogicOp); } else if (ctx->Color.BlendEnabled) { GLenum eqRGB = ctx->Color.Blend[0].EquationRGB; GLenum eqA = ctx->Color.Blend[0].EquationA; GLenum srcRGB = ctx->Color.Blend[0].SrcRGB; GLenum dstRGB = ctx->Color.Blend[0].DstRGB; GLenum srcA = ctx->Color.Blend[0].SrcA; GLenum dstA = ctx->Color.Blend[0].DstA; /* If the renderbuffer is XRGB, we have to frob the blend function to * force the destination alpha to 1.0. This means replacing GL_DST_ALPHA * with GL_ONE and GL_ONE_MINUS_DST_ALPHA with GL_ZERO. */ if (ctx->DrawBuffer->Visual.alphaBits == 0) { srcRGB = brw_fix_xRGB_alpha(srcRGB); srcA = brw_fix_xRGB_alpha(srcA); dstRGB = brw_fix_xRGB_alpha(dstRGB); dstA = brw_fix_xRGB_alpha(dstA); } if (eqRGB == GL_MIN || eqRGB == GL_MAX) { srcRGB = dstRGB = GL_ONE; } if (eqA == GL_MIN || eqA == GL_MAX) { srcA = dstA = GL_ONE; } cc->cc6.dest_blend_factor = brw_translate_blend_factor(dstRGB); cc->cc6.src_blend_factor = brw_translate_blend_factor(srcRGB); cc->cc6.blend_function = brw_translate_blend_equation(eqRGB); cc->cc5.ia_dest_blend_factor = brw_translate_blend_factor(dstA); cc->cc5.ia_src_blend_factor = brw_translate_blend_factor(srcA); cc->cc5.ia_blend_function = brw_translate_blend_equation(eqA); cc->cc3.blend_enable = 1; cc->cc3.ia_blend_enable = (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB); } /* _NEW_BUFFERS */ if (ctx->Color.AlphaEnabled && ctx->DrawBuffer->_NumColorDrawBuffers <= 1) { cc->cc3.alpha_test = 1; cc->cc3.alpha_test_func = intel_translate_compare_func(ctx->Color.AlphaFunc); cc->cc3.alpha_test_format = BRW_ALPHATEST_FORMAT_UNORM8; UNCLAMPED_FLOAT_TO_UBYTE(cc->cc7.alpha_ref.ub[0], ctx->Color.AlphaRef); } if (ctx->Color.DitherFlag) { cc->cc5.dither_enable = 1; cc->cc6.y_dither_offset = 0; cc->cc6.x_dither_offset = 0; } /* _NEW_DEPTH */ if (ctx->Depth.Test) { cc->cc2.depth_test = 1; cc->cc2.depth_test_function = intel_translate_compare_func(ctx->Depth.Func); cc->cc2.depth_write_enable = ctx->Depth.Mask; } if (brw->stats_wm || unlikely(INTEL_DEBUG & DEBUG_STATS)) cc->cc5.statistics_enable = 1; /* CACHE_NEW_CC_VP */ cc->cc4.cc_viewport_state_offset = (brw->batch.bo->offset + brw->cc.vp_offset) >> 5; /* reloc */ brw->state.dirty.cache |= CACHE_NEW_CC_UNIT; /* Emit CC viewport relocation */ drm_intel_bo_emit_reloc(brw->batch.bo, (brw->cc.state_offset + offsetof(struct brw_cc_unit_state, cc4)), brw->batch.bo, brw->cc.vp_offset, I915_GEM_DOMAIN_INSTRUCTION, 0); }
/** * Creates the state cache entry for the given CC unit key. */ static dri_bo * cc_unit_create_from_key(struct brw_context *brw, struct brw_cc_unit_key *key) { struct brw_cc_unit_state cc; dri_bo *bo; memset(&cc, 0, sizeof(cc)); /* _NEW_STENCIL */ if (key->stencil) { cc.cc0.stencil_enable = 1; cc.cc0.stencil_func = intel_translate_compare_func(key->stencil_func[0]); cc.cc0.stencil_fail_op = intel_translate_stencil_op(key->stencil_fail_op[0]); cc.cc0.stencil_pass_depth_fail_op = intel_translate_stencil_op(key->stencil_pass_depth_fail_op[0]); cc.cc0.stencil_pass_depth_pass_op = intel_translate_stencil_op(key->stencil_pass_depth_pass_op[0]); cc.cc1.stencil_ref = key->stencil_ref[0]; cc.cc1.stencil_write_mask = key->stencil_write_mask[0]; cc.cc1.stencil_test_mask = key->stencil_test_mask[0]; if (key->stencil_two_side) { cc.cc0.bf_stencil_enable = 1; cc.cc0.bf_stencil_func = intel_translate_compare_func(key->stencil_func[1]); cc.cc0.bf_stencil_fail_op = intel_translate_stencil_op(key->stencil_fail_op[1]); cc.cc0.bf_stencil_pass_depth_fail_op = intel_translate_stencil_op(key->stencil_pass_depth_fail_op[1]); cc.cc0.bf_stencil_pass_depth_pass_op = intel_translate_stencil_op(key->stencil_pass_depth_pass_op[1]); cc.cc1.bf_stencil_ref = key->stencil_ref[1]; cc.cc2.bf_stencil_write_mask = key->stencil_write_mask[1]; cc.cc2.bf_stencil_test_mask = key->stencil_test_mask[1]; } /* Not really sure about this: */ if (key->stencil_write_mask[0] || (key->stencil_two_side && key->stencil_write_mask[1])) cc.cc0.stencil_write_enable = 1; } /* _NEW_COLOR */ if (key->logic_op != GL_COPY) { cc.cc2.logicop_enable = 1; cc.cc5.logicop_func = intel_translate_logic_op(key->logic_op); } else if (key->color_blend) { GLenum eqRGB = key->blend_eq_rgb; GLenum eqA = key->blend_eq_a; GLenum srcRGB = key->blend_src_rgb; GLenum dstRGB = key->blend_dst_rgb; GLenum srcA = key->blend_src_a; GLenum dstA = key->blend_dst_a; if (eqRGB == GL_MIN || eqRGB == GL_MAX) { srcRGB = dstRGB = GL_ONE; } if (eqA == GL_MIN || eqA == GL_MAX) { srcA = dstA = GL_ONE; } cc.cc6.dest_blend_factor = brw_translate_blend_factor(dstRGB); cc.cc6.src_blend_factor = brw_translate_blend_factor(srcRGB); cc.cc6.blend_function = brw_translate_blend_equation(eqRGB); cc.cc5.ia_dest_blend_factor = brw_translate_blend_factor(dstA); cc.cc5.ia_src_blend_factor = brw_translate_blend_factor(srcA); cc.cc5.ia_blend_function = brw_translate_blend_equation(eqA); cc.cc3.blend_enable = 1; cc.cc3.ia_blend_enable = (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB); } if (key->alpha_enabled) { cc.cc3.alpha_test = 1; cc.cc3.alpha_test_func = intel_translate_compare_func(key->alpha_func); cc.cc3.alpha_test_format = BRW_ALPHATEST_FORMAT_UNORM8; UNCLAMPED_FLOAT_TO_UBYTE(cc.cc7.alpha_ref.ub[0], key->alpha_ref); } if (key->dither) { cc.cc5.dither_enable = 1; cc.cc6.y_dither_offset = 0; cc.cc6.x_dither_offset = 0; } /* _NEW_DEPTH */ if (key->depth_test) { cc.cc2.depth_test = 1; cc.cc2.depth_test_function = intel_translate_compare_func(key->depth_func); cc.cc2.depth_write_enable = key->depth_write; } /* CACHE_NEW_CC_VP */ cc.cc4.cc_viewport_state_offset = brw->cc.vp_bo->offset >> 5; /* reloc */ if (INTEL_DEBUG & DEBUG_STATS) cc.cc5.statistics_enable = 1; bo = brw_upload_cache(&brw->cache, BRW_CC_UNIT, key, sizeof(*key), &brw->cc.vp_bo, 1, &cc, sizeof(cc), NULL, NULL); /* Emit CC viewport relocation */ dri_bo_emit_reloc(bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0, offsetof(struct brw_cc_unit_state, cc4), brw->cc.vp_bo); return bo; }
void i915_update_stencil(struct gl_context * ctx) { struct i915_context *i915 = I915_CONTEXT(ctx); GLuint front_ref, front_writemask, front_mask; GLenum front_func, front_fail, front_pass_z_fail, front_pass_z_pass; GLuint back_ref, back_writemask, back_mask; GLenum back_func, back_fail, back_pass_z_fail, back_pass_z_pass; GLuint dirty = 0; /* The 915 considers CW to be "front" for two-sided stencil, so choose * appropriately. */ /* _NEW_POLYGON | _NEW_STENCIL */ if (ctx->Polygon.FrontFace == GL_CW) { front_ref = ctx->Stencil.Ref[0]; front_mask = ctx->Stencil.ValueMask[0]; front_writemask = ctx->Stencil.WriteMask[0]; front_func = ctx->Stencil.Function[0]; front_fail = ctx->Stencil.FailFunc[0]; front_pass_z_fail = ctx->Stencil.ZFailFunc[0]; front_pass_z_pass = ctx->Stencil.ZPassFunc[0]; back_ref = ctx->Stencil.Ref[ctx->Stencil._BackFace]; back_mask = ctx->Stencil.ValueMask[ctx->Stencil._BackFace]; back_writemask = ctx->Stencil.WriteMask[ctx->Stencil._BackFace]; back_func = ctx->Stencil.Function[ctx->Stencil._BackFace]; back_fail = ctx->Stencil.FailFunc[ctx->Stencil._BackFace]; back_pass_z_fail = ctx->Stencil.ZFailFunc[ctx->Stencil._BackFace]; back_pass_z_pass = ctx->Stencil.ZPassFunc[ctx->Stencil._BackFace]; } else { front_ref = ctx->Stencil.Ref[ctx->Stencil._BackFace]; front_mask = ctx->Stencil.ValueMask[ctx->Stencil._BackFace]; front_writemask = ctx->Stencil.WriteMask[ctx->Stencil._BackFace]; front_func = ctx->Stencil.Function[ctx->Stencil._BackFace]; front_fail = ctx->Stencil.FailFunc[ctx->Stencil._BackFace]; front_pass_z_fail = ctx->Stencil.ZFailFunc[ctx->Stencil._BackFace]; front_pass_z_pass = ctx->Stencil.ZPassFunc[ctx->Stencil._BackFace]; back_ref = ctx->Stencil.Ref[0]; back_mask = ctx->Stencil.ValueMask[0]; back_writemask = ctx->Stencil.WriteMask[0]; back_func = ctx->Stencil.Function[0]; back_fail = ctx->Stencil.FailFunc[0]; back_pass_z_fail = ctx->Stencil.ZFailFunc[0]; back_pass_z_pass = ctx->Stencil.ZPassFunc[0]; } #define set_ctx_bits(reg, mask, set) do{ \ GLuint dw = i915->state.Ctx[reg]; \ dw &= ~(mask); \ dw |= (set); \ dirty |= dw != i915->state.Ctx[reg]; \ i915->state.Ctx[reg] = dw; \ } while(0) /* Set front state. */ set_ctx_bits(I915_CTXREG_STATE4, MODE4_ENABLE_STENCIL_TEST_MASK | MODE4_ENABLE_STENCIL_WRITE_MASK, ENABLE_STENCIL_TEST_MASK | ENABLE_STENCIL_WRITE_MASK | STENCIL_TEST_MASK(front_mask) | STENCIL_WRITE_MASK(front_writemask)); set_ctx_bits(I915_CTXREG_LIS5, S5_STENCIL_REF_MASK | S5_STENCIL_TEST_FUNC_MASK | S5_STENCIL_FAIL_MASK | S5_STENCIL_PASS_Z_FAIL_MASK | S5_STENCIL_PASS_Z_PASS_MASK, (front_ref << S5_STENCIL_REF_SHIFT) | (intel_translate_compare_func(front_func) << S5_STENCIL_TEST_FUNC_SHIFT) | (intel_translate_stencil_op(front_fail) << S5_STENCIL_FAIL_SHIFT) | (intel_translate_stencil_op(front_pass_z_fail) << S5_STENCIL_PASS_Z_FAIL_SHIFT) | (intel_translate_stencil_op(front_pass_z_pass) << S5_STENCIL_PASS_Z_PASS_SHIFT)); /* Set back state if different from front. */ if (ctx->Stencil._TestTwoSide) { set_ctx_bits(I915_CTXREG_BF_STENCIL_OPS, BFO_STENCIL_REF_MASK | BFO_STENCIL_TEST_MASK | BFO_STENCIL_FAIL_MASK | BFO_STENCIL_PASS_Z_FAIL_MASK | BFO_STENCIL_PASS_Z_PASS_MASK, BFO_STENCIL_TWO_SIDE | (back_ref << BFO_STENCIL_REF_SHIFT) | (intel_translate_compare_func(back_func) << BFO_STENCIL_TEST_SHIFT) | (intel_translate_stencil_op(back_fail) << BFO_STENCIL_FAIL_SHIFT) | (intel_translate_stencil_op(back_pass_z_fail) << BFO_STENCIL_PASS_Z_FAIL_SHIFT) | (intel_translate_stencil_op(back_pass_z_pass) << BFO_STENCIL_PASS_Z_PASS_SHIFT)); set_ctx_bits(I915_CTXREG_BF_STENCIL_MASKS, BFM_STENCIL_TEST_MASK_MASK | BFM_STENCIL_WRITE_MASK_MASK, BFM_STENCIL_TEST_MASK(back_mask) | BFM_STENCIL_WRITE_MASK(back_writemask)); } else { set_ctx_bits(I915_CTXREG_BF_STENCIL_OPS, BFO_STENCIL_TWO_SIDE, 0); } #undef set_ctx_bits if (dirty) I915_STATECHANGE(i915, I915_UPLOAD_CTX); }
static void gen6_upload_blend_state(struct brw_context *brw) { bool is_buffer_zero_integer_format = false; struct gl_context *ctx = &brw->intel.ctx; struct gen6_blend_state *blend; int b; int nr_draw_buffers = ctx->DrawBuffer->_NumColorDrawBuffers; int size; /* We need at least one BLEND_STATE written, because we might do * thread dispatch even if _NumColorDrawBuffers is 0 (for example * for computed depth or alpha test), which will do an FB write * with render target 0, which will reference BLEND_STATE[0] for * alpha test enable. */ if (nr_draw_buffers == 0 && ctx->Color.AlphaEnabled) nr_draw_buffers = 1; size = sizeof(*blend) * nr_draw_buffers; blend = brw_state_batch(brw, AUB_TRACE_BLEND_STATE, size, 64, &brw->cc.blend_state_offset); memset(blend, 0, size); for (b = 0; b < nr_draw_buffers; b++) { /* _NEW_BUFFERS */ struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[b]; GLenum rb_type; bool integer; if (rb) rb_type = _mesa_get_format_datatype(rb->Format); else rb_type = GL_UNSIGNED_NORMALIZED; /* Used for implementing the following bit of GL_EXT_texture_integer: * "Per-fragment operations that require floating-point color * components, including multisample alpha operations, alpha test, * blending, and dithering, have no effect when the corresponding * colors are written to an integer color buffer." */ integer = (rb_type == GL_INT || rb_type == GL_UNSIGNED_INT); if(b == 0 && integer) is_buffer_zero_integer_format = true; /* _NEW_COLOR */ if (ctx->Color.ColorLogicOpEnabled) { /* Floating point RTs should have no effect from LogicOp, * except for disabling of blending, but other types should. * * However, from the Sandy Bridge PRM, Vol 2 Par 1, Section 8.1.11, * "Logic Ops", * * "Logic Ops are only supported on *_UNORM surfaces (excluding * _SRGB variants), otherwise Logic Ops must be DISABLED." */ WARN_ONCE(ctx->Color.LogicOp != GL_COPY && rb_type != GL_UNSIGNED_NORMALIZED && rb_type != GL_FLOAT, "Ignoring %s logic op on %s " "renderbuffer\n", _mesa_lookup_enum_by_nr(ctx->Color.LogicOp), _mesa_lookup_enum_by_nr(rb_type)); if (rb_type == GL_UNSIGNED_NORMALIZED) { blend[b].blend1.logic_op_enable = 1; blend[b].blend1.logic_op_func = intel_translate_logic_op(ctx->Color.LogicOp); } } else if (ctx->Color.BlendEnabled & (1 << b) && !integer) { GLenum eqRGB = ctx->Color.Blend[b].EquationRGB; GLenum eqA = ctx->Color.Blend[b].EquationA; GLenum srcRGB = ctx->Color.Blend[b].SrcRGB; GLenum dstRGB = ctx->Color.Blend[b].DstRGB; GLenum srcA = ctx->Color.Blend[b].SrcA; GLenum dstA = ctx->Color.Blend[b].DstA; if (eqRGB == GL_MIN || eqRGB == GL_MAX) { srcRGB = dstRGB = GL_ONE; } if (eqA == GL_MIN || eqA == GL_MAX) { srcA = dstA = GL_ONE; } blend[b].blend0.dest_blend_factor = brw_translate_blend_factor(dstRGB); blend[b].blend0.source_blend_factor = brw_translate_blend_factor(srcRGB); blend[b].blend0.blend_func = brw_translate_blend_equation(eqRGB); blend[b].blend0.ia_dest_blend_factor = brw_translate_blend_factor(dstA); blend[b].blend0.ia_source_blend_factor = brw_translate_blend_factor(srcA); blend[b].blend0.ia_blend_func = brw_translate_blend_equation(eqA); blend[b].blend0.blend_enable = 1; blend[b].blend0.ia_blend_enable = (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB); } /* See section 8.1.6 "Pre-Blend Color Clamping" of the * SandyBridge PRM Volume 2 Part 1 for HW requirements. * * We do our ARB_color_buffer_float CLAMP_FRAGMENT_COLOR * clamping in the fragment shader. For its clamping of * blending, the spec says: * * "RESOLVED: For fixed-point color buffers, the inputs and * the result of the blending equation are clamped. For * floating-point color buffers, no clamping occurs." * * So, generally, we want clamping to the render target's range. * And, good news, the hardware tables for both pre- and * post-blend color clamping are either ignored, or any are * allowed, or clamping is required but RT range clamping is a * valid option. */ blend[b].blend1.pre_blend_clamp_enable = 1; blend[b].blend1.post_blend_clamp_enable = 1; blend[b].blend1.clamp_range = BRW_RENDERTARGET_CLAMPRANGE_FORMAT; /* _NEW_COLOR */ if (ctx->Color.AlphaEnabled && !integer) { blend[b].blend1.alpha_test_enable = 1; blend[b].blend1.alpha_test_func = intel_translate_compare_func(ctx->Color.AlphaFunc); } /* _NEW_COLOR */ if (ctx->Color.DitherFlag && !integer) { blend[b].blend1.dither_enable = 1; blend[b].blend1.y_dither_offset = 0; blend[b].blend1.x_dither_offset = 0; } blend[b].blend1.write_disable_r = !ctx->Color.ColorMask[b][0]; blend[b].blend1.write_disable_g = !ctx->Color.ColorMask[b][1]; blend[b].blend1.write_disable_b = !ctx->Color.ColorMask[b][2]; blend[b].blend1.write_disable_a = !ctx->Color.ColorMask[b][3]; /* OpenGL specification 3.3 (page 196), section 4.1.3 says: * "If drawbuffer zero is not NONE and the buffer it references has an * integer format, the SAMPLE_ALPHA_TO_COVERAGE and SAMPLE_ALPHA_TO_ONE * operations are skipped." */ if(!is_buffer_zero_integer_format) { /* _NEW_MULTISAMPLE */ blend[b].blend1.alpha_to_coverage = ctx->Multisample._Enabled && ctx->Multisample.SampleAlphaToCoverage; /* From SandyBridge PRM, volume 2 Part 1, section 8.2.3, BLEND_STATE: * DWord 1, Bit 30 (AlphaToOne Enable): * "If Dual Source Blending is enabled, this bit must be disabled" */ WARN_ONCE(ctx->Color.Blend[b]._UsesDualSrc && ctx->Multisample._Enabled && ctx->Multisample.SampleAlphaToOne, "HW workaround: disabling alpha to one with dual src " "blending\n"); if (ctx->Color.Blend[b]._UsesDualSrc) blend[b].blend1.alpha_to_one = false; else blend[b].blend1.alpha_to_one = ctx->Multisample._Enabled && ctx->Multisample.SampleAlphaToOne; blend[b].blend1.alpha_to_coverage_dither = (brw->intel.gen >= 7); } else { blend[b].blend1.alpha_to_coverage = false; blend[b].blend1.alpha_to_one = false; } } brw->state.dirty.cache |= CACHE_NEW_BLEND_STATE; }
static void gen6_upload_depth_stencil_state(struct brw_context *brw) { struct gl_context *ctx = &brw->ctx; struct gen6_depth_stencil_state *ds; struct intel_renderbuffer *depth_irb; /* _NEW_BUFFERS */ depth_irb = intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_DEPTH); ds = brw_state_batch(brw, AUB_TRACE_DEPTH_STENCIL_STATE, sizeof(*ds), 64, &brw->cc.depth_stencil_state_offset); memset(ds, 0, sizeof(*ds)); /* _NEW_STENCIL | _NEW_BUFFERS */ if (ctx->Stencil._Enabled) { int back = ctx->Stencil._BackFace; ds->ds0.stencil_enable = 1; ds->ds0.stencil_func = intel_translate_compare_func(ctx->Stencil.Function[0]); ds->ds0.stencil_fail_op = intel_translate_stencil_op(ctx->Stencil.FailFunc[0]); ds->ds0.stencil_pass_depth_fail_op = intel_translate_stencil_op(ctx->Stencil.ZFailFunc[0]); ds->ds0.stencil_pass_depth_pass_op = intel_translate_stencil_op(ctx->Stencil.ZPassFunc[0]); ds->ds1.stencil_write_mask = ctx->Stencil.WriteMask[0]; ds->ds1.stencil_test_mask = ctx->Stencil.ValueMask[0]; if (ctx->Stencil._TestTwoSide) { ds->ds0.bf_stencil_enable = 1; ds->ds0.bf_stencil_func = intel_translate_compare_func(ctx->Stencil.Function[back]); ds->ds0.bf_stencil_fail_op = intel_translate_stencil_op(ctx->Stencil.FailFunc[back]); ds->ds0.bf_stencil_pass_depth_fail_op = intel_translate_stencil_op(ctx->Stencil.ZFailFunc[back]); ds->ds0.bf_stencil_pass_depth_pass_op = intel_translate_stencil_op(ctx->Stencil.ZPassFunc[back]); ds->ds1.bf_stencil_write_mask = ctx->Stencil.WriteMask[back]; ds->ds1.bf_stencil_test_mask = ctx->Stencil.ValueMask[back]; } ds->ds0.stencil_write_enable = ctx->Stencil._WriteEnabled; } /* _NEW_DEPTH */ if (ctx->Depth.Test && depth_irb) { ds->ds2.depth_test_enable = ctx->Depth.Test; ds->ds2.depth_test_func = intel_translate_compare_func(ctx->Depth.Func); ds->ds2.depth_write_enable = ctx->Depth.Mask; } /* Point the GPU at the new indirect state. */ if (brw->gen == 6) { BEGIN_BATCH(4); OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (4 - 2)); OUT_BATCH(0); OUT_BATCH(brw->cc.depth_stencil_state_offset | 1); OUT_BATCH(0); ADVANCE_BATCH(); } else { BEGIN_BATCH(2); OUT_BATCH(_3DSTATE_DEPTH_STENCIL_STATE_POINTERS << 16 | (2 - 2)); OUT_BATCH(brw->cc.depth_stencil_state_offset | 1); ADVANCE_BATCH(); } }
static void prepare_blend_state(struct brw_context *brw) { struct gl_context *ctx = &brw->intel.ctx; struct gen6_blend_state *blend; int b; int nr_draw_buffers = ctx->DrawBuffer->_NumColorDrawBuffers; int size; /* We need at least one BLEND_STATE written, because we might do * thread dispatch even if _NumColorDrawBuffers is 0 (for example * for computed depth or alpha test), which will do an FB write * with render target 0, which will reference BLEND_STATE[0] for * alpha test enable. */ if (nr_draw_buffers == 0 && ctx->Color.AlphaEnabled) nr_draw_buffers = 1; size = sizeof(*blend) * nr_draw_buffers; blend = brw_state_batch(brw, AUB_TRACE_BLEND_STATE, size, 64, &brw->cc.blend_state_offset); memset(blend, 0, size); for (b = 0; b < nr_draw_buffers; b++) { /* _NEW_COLOR */ if (ctx->Color._LogicOpEnabled) { struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[b]; /* _NEW_BUFFERS */ /* Floating point RTs should have no effect from LogicOp, * except for disabling of blending */ if (_mesa_get_format_datatype(rb->Format) != GL_FLOAT) { blend[b].blend1.logic_op_enable = 1; blend[b].blend1.logic_op_func = intel_translate_logic_op(ctx->Color.LogicOp); } } else if (ctx->Color.BlendEnabled & (1 << b)) { GLenum eqRGB = ctx->Color.Blend[0].EquationRGB; GLenum eqA = ctx->Color.Blend[0].EquationA; GLenum srcRGB = ctx->Color.Blend[0].SrcRGB; GLenum dstRGB = ctx->Color.Blend[0].DstRGB; GLenum srcA = ctx->Color.Blend[0].SrcA; GLenum dstA = ctx->Color.Blend[0].DstA; if (eqRGB == GL_MIN || eqRGB == GL_MAX) { srcRGB = dstRGB = GL_ONE; } if (eqA == GL_MIN || eqA == GL_MAX) { srcA = dstA = GL_ONE; } blend[b].blend0.dest_blend_factor = brw_translate_blend_factor(dstRGB); blend[b].blend0.source_blend_factor = brw_translate_blend_factor(srcRGB); blend[b].blend0.blend_func = brw_translate_blend_equation(eqRGB); blend[b].blend0.ia_dest_blend_factor = brw_translate_blend_factor(dstA); blend[b].blend0.ia_source_blend_factor = brw_translate_blend_factor(srcA); blend[b].blend0.ia_blend_func = brw_translate_blend_equation(eqA); blend[b].blend0.blend_enable = 1; blend[b].blend0.ia_blend_enable = (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB); } /* _NEW_COLOR */ if (ctx->Color.AlphaEnabled) { blend[b].blend1.alpha_test_enable = 1; blend[b].blend1.alpha_test_func = intel_translate_compare_func(ctx->Color.AlphaFunc); } /* _NEW_COLOR */ if (ctx->Color.DitherFlag) { blend[b].blend1.dither_enable = 1; blend[b].blend1.y_dither_offset = 0; blend[b].blend1.x_dither_offset = 0; } blend[b].blend1.write_disable_r = !ctx->Color.ColorMask[b][0]; blend[b].blend1.write_disable_g = !ctx->Color.ColorMask[b][1]; blend[b].blend1.write_disable_b = !ctx->Color.ColorMask[b][2]; blend[b].blend1.write_disable_a = !ctx->Color.ColorMask[b][3]; } brw->state.dirty.cache |= CACHE_NEW_BLEND_STATE; }
static void gen6_upload_depth_stencil_state(struct brw_context *brw) { struct gl_context *ctx = &brw->intel.ctx; struct gen6_depth_stencil_state *ds; struct intel_renderbuffer *depth_irb; /* _NEW_BUFFERS */ depth_irb = intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_DEPTH); ds = brw_state_batch(brw, AUB_TRACE_DEPTH_STENCIL_STATE, sizeof(*ds), 64, &brw->cc.depth_stencil_state_offset); memset(ds, 0, sizeof(*ds)); /* _NEW_STENCIL */ if (ctx->Stencil._Enabled) { int back = ctx->Stencil._BackFace; ds->ds0.stencil_enable = 1; ds->ds0.stencil_func = intel_translate_compare_func(ctx->Stencil.Function[0]); ds->ds0.stencil_fail_op = intel_translate_stencil_op(ctx->Stencil.FailFunc[0]); ds->ds0.stencil_pass_depth_fail_op = intel_translate_stencil_op(ctx->Stencil.ZFailFunc[0]); ds->ds0.stencil_pass_depth_pass_op = intel_translate_stencil_op(ctx->Stencil.ZPassFunc[0]); ds->ds1.stencil_write_mask = ctx->Stencil.WriteMask[0]; ds->ds1.stencil_test_mask = ctx->Stencil.ValueMask[0]; if (ctx->Stencil._TestTwoSide) { ds->ds0.bf_stencil_enable = 1; ds->ds0.bf_stencil_func = intel_translate_compare_func(ctx->Stencil.Function[back]); ds->ds0.bf_stencil_fail_op = intel_translate_stencil_op(ctx->Stencil.FailFunc[back]); ds->ds0.bf_stencil_pass_depth_fail_op = intel_translate_stencil_op(ctx->Stencil.ZFailFunc[back]); ds->ds0.bf_stencil_pass_depth_pass_op = intel_translate_stencil_op(ctx->Stencil.ZPassFunc[back]); ds->ds1.bf_stencil_write_mask = ctx->Stencil.WriteMask[back]; ds->ds1.bf_stencil_test_mask = ctx->Stencil.ValueMask[back]; } /* Not really sure about this: */ if (ctx->Stencil.WriteMask[0] || (ctx->Stencil._TestTwoSide && ctx->Stencil.WriteMask[back])) ds->ds0.stencil_write_enable = 1; } /* _NEW_DEPTH */ if (ctx->Depth.Test && depth_irb) { ds->ds2.depth_test_enable = ctx->Depth.Test; ds->ds2.depth_test_func = intel_translate_compare_func(ctx->Depth.Func); ds->ds2.depth_write_enable = ctx->Depth.Mask; } brw->state.dirty.cache |= CACHE_NEW_DEPTH_STENCIL_STATE; }