// Bootstrap processor starts running C code here.
// Allocate a real stack and switch to it, first
// doing some setup required for memory allocator to work.
int
main(void)
{
kvmalloc(); // kernel page table
mpinit(); // collect info about this machine
lapicinit(mpbcpu());
seginit(); // set up segments
cprintf("\ncpu%d: starting xv6\n\n", cpu->id);
picinit(); // interrupt controller
ioapicinit(); // another interrupt controller
consoleinit(); // I/O devices & their interrupts
uartinit(); // serial port
pinit(); // process table
tvinit(); // trap vectors
binit(); // buffer cache
fileinit(); // file table
iinit(); // inode cache
ideinit(); // disk
if(!ismp)
timerinit(); // uniprocessor timer
startothers(); // start other processors (must come before kinit)
kinit(); // initialize memory allocator
userinit(); // first user process (must come after kinit)
// Finish setting up this processor in mpmain.
mpmain();
}
// Bootstrap processor starts running C code here.
// Allocate a real stack and switch to it, first
// doing some setup required for memory allocator to work.
int
main(void)
{
kinit1(end, P2V(4*1024*1024)); // phys page allocator
kvmalloc(); // kernel page table
mpinit(); // collect info about this machine
lapicinit();
seginit(); // set up segments
cprintf("\ncpu%d: starting xv6\n\n", cpu->id);
picinit(); // interrupt controller
ioapicinit(); // another interrupt controller
consoleinit(); // I/O devices & their interrupts
uartinit(); // serial port
pinit(); // process table
tvinit(); // trap vectors
binit(); // buffer cache
fileinit(); // file table
ideinit(); // disk
if(!ismp)
timerinit(); // uniprocessor timer
startothers(); // start other processors
kinit2(P2V(4*1024*1024), P2V(PHYSTOP)); // must come after startothers()
userinit(); // first user process
mpmain();
}
// Bootstrap processor starts running C code here.
// Allocate a real stack and switch to it, first
// doing some setup required for memory allocator to work.
int
main(void)
{
kinit1(end, P2V(4*1024*1024)); // phys page allocator
kvmalloc(); // kernel page table
mpinit(); // detect other processors
lapicinit(); // interrupt controller
seginit(); // segment descriptors
cprintf("\ncpu%d: starting xv6\n\n", cpunum());
picinit(); // another interrupt controller
ioapicinit(); // another interrupt controller
consoleinit(); // console hardware
uartinit(); // serial port
pinit(); // process table
tvinit(); // trap vectors
binit(); // buffer cache
fileinit(); // file table
ideinit(); // disk
if(!ismp)
timerinit(); // uniprocessor timer
startothers(); // start other processors
kinit2(P2V(4*1024*1024), P2V(PHYSTOP)); // must come after startothers()
userinit(); // first user process
mpmain(); // finish this processor's setup
init_semaphores_on_boot();
}
// Bootstrap processor starts running C code here.
int
main(int memsize)
{
mpinit(); // collect info about this machine
lapicinit(mpbcpu());
ksegment();
picinit(); // interrupt controller
ioapicinit(); // another interrupt controller
consoleinit(); // I/O devices & their interrupts
uartinit(); // serial port
cprintf("cpus %p cpu %p\n", cpus, cpu);
cprintf("\ncpu%d: starting xv6\n\n", cpu->id);
cprintf("mem: %d kb\n", memsize);
kinit(memsize); // physical memory allocator
pinit(); // process table
tvinit(); // trap vectors
binit(); // buffer cache
fileinit(); // file table
iinit(); // inode cache
ideinit(); // disk
if(!ismp)
timerinit(); // uniprocessor timer
pageinit(); // enable paging
userinit(); // first user process
bootothers(); // start other processors
// Finish setting up this processor in mpmain.
mpmain();
}
// Bootstrap processor starts running C code here.
// Allocate a real stack and switch to it, first
// doing some setup required for memory allocator to work.
int
main(void)
{
unsigned char FB[]="MESSAGE WRITTEN THROUGH FRAMEBUFFER!!";
fb_init(); // initialize framebuffer device (2015.11.02)
cprintf("\nUsing Framebuffer still presents some problems :(\n\n");
cprintf("\nSuggestion: review the way it is used in console.c\n\n");
fb_write(FB, sizeof(FB)); // Framebuffer maybe could be used before this moment (2015.11.02)
see_mylock(MYLOCK);
kinit1(end, P2V(4*1024*1024)); // phys page allocator
kvmalloc(); // kernel page table
mpinit(); // collect info about this machine
lapicinit();
seginit(); // set up segments
cprintf("\ncpu%d: starting xv6\n\n", cpu->id);
picinit(); // interrupt controller
ioapicinit(); // another interrupt controller
consoleinit(); // I/O devices & their interrupts
uartinit(); // serial port
pinit(); // process table
tvinit(); // trap vectors
binit(); // buffer cache
fileinit(); // file table
ideinit(); // disk
if(!ismp)
timerinit(); // uniprocessor timer
startothers(); // start other processors
kinit2(P2V(4*1024*1024), P2V(PHYSTOP)); // must come after startothers()
userinit(); // first user process
// Finish setting up this processor in mpmain.
mpmain();
}
// Bootstrap processor starts running C code here.
// Allocate a real stack and switch to it, first
// doing some setup required for memory allocator to work.
int
main(void)
{
monitor_clear ();
// Print basic system information.
cprintf ("Ensidia\n\n");
cprintf ("Copyright (c) 2013-2014 Fotis Koutoulakis\n");
cprintf ("Based on xv6 by Russ Cox et al, at MIT CSAIL\n");
kinit1(end, P2V(4*1024*1024)); // phys page allocator
kvmalloc(); // kernel page table
mpinit(); // collect info about this machine
lapicinit();
seginit(); // set up segments
cprintf("\ncpu%d: starting xng kernel\n\n", cpu->id);
picinit(); // interrupt controller
ioapicinit(); // another interrupt controller
consoleinit(); // I/O devices & their interrupts
uartinit(); // serial port
pinit(); // process table
tvinit(); // trap vectors
binit(); // buffer cache
fileinit(); // file table
iinit(); // inode cache
ideinit(); // disk
if(!ismp)
timerinit(); // uniprocessor timer
startothers(); // start other processors
kinit2(P2V(4*1024*1024), P2V(PHYSTOP)); // must come after startothers()
userinit(); // first user process
// Finish setting up this processor in mpmain.
mpmain();
}
/*int main(void){*/
void kmain(void){
// vga_init();
// puts((uint8_t*)"Hello kernel world!\n");
/*do some work here, like initialize timer or paging*/
kinit1(end, P2V(4*1024*1024)); // phys page allocator
kvmalloc(); // kernel page table
mpinit(); // collect info about this machine
lapicinit();
// gdt_descriptor();
// puts((uint8_t*)"GDT initialized...\n");
// idt_descriptor();
// puts((uint8_t*)"IDT initialized...\n");
// cprintf("IDT initialized...\n");
seginit(); // set up segments
cprintf("\ncpu%d: starting xv6\n\n", cpu->id);
picinit(); // interrupt controller
ioapicinit(); // another interrupt controller
consoleinit(); // I/O devices & their interrupts
uartinit(); // serial port
pinit(); // process table
tvinit(); // trap vectors
binit(); // buffer cache
fileinit(); // file table
ideinit(); // disk
if(!ismp)
timerinit(); // uniprocessor timer
startothers(); // start other processors
kinit2(P2V(4*1024*1024), P2V(PHYSTOP)); // must come after startothers()
userinit(); // first user process
// Finish setting up this processor in mpmain.
mpmain();
}
// Bootstrap processor starts running C code here.
// Allocate a real stack and switch to it, first
// doing some setup required for memory allocator to work.
int
main(void)
{
kinit1(end, P2V(4*1024*1024)); // phys page allocator // kmem. freelist added
cprintf("%x \n", end);
kvmalloc(); // kernel page table
#ifdef CONFIG_MULTI_PROCESS
mpinit(); // collect info about this machine
#endif
lapicinit();
seginit(); // set up segments
picinit(); // interrupt controller: Programmable Interrupt Controller
#ifdef CONFIG_MULTI_PROCESS
ioapicinit(); // another interrupt controller
#endif
consoleinit(); // I/O devices & their interrupts
uartinit(); // serial port
pinit(); // process table
tvinit(); // trap vectors
binit(); // buffer cache
fileinit(); // file table
iinit(); // inode cache
ideinit(); // disk
if(!ismp)
timerinit(); // uniprocessor timer
#ifdef CONFIG_MULTI_PROCESS
startothers(); // start other processors
kinit2(P2V(4*1024*1024), P2V(PHYSTOP)); // must come after startothers()
#endif
userinit(); // first user process
// Finish setting up this processor in mpmain.
mpmain();
}
// Bootstrap processor starts running C code here.
// Allocate a real stack and switch to it, first
// doing some setup required for memory allocator to work.
int
main(void)
{
kinit1(end, P2V(4*1024*1024)); // phys page allocator
kvmalloc(); // kernel page table
mpinit(); // collect info about this machine
lapicinit();
seginit(); // set up segments
cprintf("\ncpu%d: starting xv6\n\n", cpu->id);
picinit(); // interrupt controller
ioapicinit(); // another interrupt controller
consoleinit(); // I/O devices & their interrupts
uartinit(); // serial port
initGraphMode();
initDom();
tryOnce();
toggleOn();
pinit(); // process table
toggleOn();
tvinit(); // trap vectors
toggleOn();
binit(); // buffer cache
toggleOn();
fileinit(); // file table
toggleOn();
iinit(); // inode cache
toggleOn();
ideinit(); // disk
toggleOn();
if(!ismp)
timerinit(); // uniprocessor timer
toggleOn();
startothers(); // start other processors
toggleOn();
kinit2(P2V(4*1024*1024), P2V(PHYSTOP)); // must come after startothers()
toggleOn();
txt_initLock();
mouseEnable();
initProcessMsgMap();
userinit(); // first user process
toggleOn();
endToggle();
// Finish setting up this processor in mpmain.
mpmain();
}
void
mpinitcpu(long unit)
{
cpuinit(unit);
/* TODO: initialise HPET; enable [rerouted] interrupts */
#if (HPET)
hpetinit();
#endif
apicinit();
#if (IOAPIC)
ioapicinit();
#endif
tssinit(unit);
return;
}
ASMLINK
void
mpmain(struct m_cpu *cpu)
{
// gdtinit();
seginit(cpu->id);
idtset();
m_xchgl(&cpu->started, 1L);
/* TODO: initialise HPET; enable [rerouted] interrupts */
#if (HPET)
hpetinit();
apicinitcpu(cpu->id);
ioapicinit(cpu->id);
tssinit(cpu->id);
#endif
while (1) {
k_waitint();
}
}
// Os procedimentos de inicialização começam a executar o
// código .C a partir daqui.
// Aloca uma pilha real e troca para ela, primeiro fazendo
// algumas configurações necessárias par o alocador de memória funcionar.
int main(void) {
kinit1(end, P2V(4*1024*1024)); // alocador de páginas de memória física
kvmalloc(); // tabela de páginas do kernel
mpinit(); // detecta outros processadores
lapicinit(); // controlador de interrupções
seginit(); // descritores de segmentos
picinit(); // desabilita pic
ioapicinit(); // outro controlador de interrupções
consoleinit(); // console hardware
uartinit(); // porta serial
pinit(); // tabela de processos
tvinit(); // vetores trap
binit(); // buffer cache
fileinit(); // tabela de arquivo
ideinit(); // disco
startothers(); // inicia outros processadores
kinit2(P2V(4*1024*1024), P2V(PHYSTOP)); // deve vir após startothers()
userinit(); // primeiro processo no modo usuário
mpmain(); // encerra esta configuração de processadores
}
void
mpstart(void)
{
// volatile static int first = 1;
volatile struct m_cpu *cpu;
volatile struct m_cpu *lim;
uint32_t *mpentrystk = (uint32_t *)MPENTRYSTK;
lim = &mpcputab[0] + mpncpu;
#if 0
if (first) {
kmemcpy((void *)MPENTRY,
mpentry, (uint8_t *)&mpend - (uint8_t *)&mpentry);
first = 0;
}
#endif
for (cpu = &mpcputab[0] ; cpu < lim ; cpu++) {
if (cpu == mpbootcpu) {
/* started already */
continue;
}
kprintf("starting CPU %ld @ 0x%lx\n", cpu->id, MPENTRY);
cpuinit((struct m_cpu *)cpu);
#if 0
apicinit(cpu->id);
ioapicinit(cpu->id);
#endif
*--mpentrystk = (uint32_t)cpu;
*--mpentrystk = MPENTRYSTK - cpu->id * MPSTKSIZE;
*--mpentrystk = (uint32_t)&kernpagedir;
apicstart(cpu->id, MPENTRY);
while (!cpu->started) {
;
}
}
return;
}
// Bootstrap processor starts running C code here.
// Allocate a real stack and switch to it, first
// doing some setup required for memory allocator to work.
int
main(void)
{
kinit1(end, P2V(4*1024*1024)); // phys page allocator
kvmalloc(); // kernel page table
mpinit(); // detect other processors
lapicinit(); // interrupt controller
seginit(); // segment descriptors
picinit(); // disable pic
ioapicinit(); // another interrupt controller
consoleinit(); // console hardware
uartinit(); // serial port
pinit(); // process table
shminit(); // shared memory
tvinit(); // trap vectors
binit(); // buffer cache
fileinit(); // file table
ideinit(); // disk
startothers(); // start other processors
kinit2(P2V(4*1024*1024), P2V(PHYSTOP)); // must come after startothers()
userinit(); // first user process
mpmain(); // finish this processor's setup
}
// Bootstrap processor starts running C code here.
// Allocate a real stack and switch to it, first
// doing some setup required for memory allocator to work.
int
main(void)
{
monitor_clear();
xylos_logo();
kinit1(end, P2V(4 * 1024 * 1024)); // phys page allocator, 16MB for kernel
kvmalloc(); // kernel page table
mpinit(); // collect info about this machine
lapicinit();
seginit(); // set up segments
cprintf("Initializing interrupts... ");
init_generic_irq_table();
picinit(); // interrupt controller
ioapicinit(); // another interrupt controller
cprintf_color(COLOR_BLACK, COLOR_LIGHT_GREEN, false, "done\n");
cprintf("Initializing console and serial... ");
consoleinit(); // I/O devices & their interrupts
uartinit(); // serial port
cprintf_color(COLOR_BLACK, COLOR_LIGHT_GREEN, false, "done\n");
cprintf("Setting up swap space disk... ");
swapinit();
cprintf_color(COLOR_BLACK, COLOR_LIGHT_GREEN, false, "done\n");
cprintf("Initializing tasking... ");
pinit(); // process table
tvinit(); // trap vectors
binit(); // buffer cache
cprintf_color(COLOR_BLACK, COLOR_LIGHT_GREEN, false, "done\n");
cprintf("Initializing pipe IPC... ");
init_pipe_ipc_system();
if(pipe_ipc_sanitycheck() == 0) {
cprintf_color(COLOR_BLACK, COLOR_LIGHT_GREEN, false, "done\n");
}
cprintf("Initializing direct IPC... ");
init_direct_ipc_table();
if(direct_ipc_sanitycheck() == 0) {
cprintf_color(COLOR_BLACK, COLOR_LIGHT_GREEN, false, "done\n");
}
cprintf("Mounting root filesystem... ");
fileinit(); // file table
ideinit(); // disk
cprintf_color(COLOR_BLACK, COLOR_LIGHT_GREEN, false, "done\n");
if(!ismp) {
cprintf("Starting up uniprocessor CPU... ");
timerinit(); // uniprocessor timer
cprintf_color(COLOR_BLACK, COLOR_LIGHT_GREEN, false, "done\n");
}
if(ismp) {
if(ncpu > 1) {
cprintf("Starting up %d CPU cores... ", ncpu);
} else {
cprintf("Starting up %d CPU core... ", ncpu);
}
}
startothers(); // start other processors
kinit2(P2V(4 * 1024 * 1024), P2V(PHYSTOP)); // 16MB to PHYSTOP [234MB]
if(ismp) {
cprintf_color(COLOR_BLACK, COLOR_LIGHT_GREEN, false, "done\n");
}
// detects and starts km drivers
auto_enable_nic();
// first user process
userinit();
// Finish setting up this processor in mpmain.
mpmain();
}
static void
pcmpinit(void)
{
uchar *p, *e;
Apic *apic;
void *va;
/*
* Map the local APIC.
*/
va = vmap(pcmp->lapicbase, 1024);
print("LAPIC: %.8lux %#p\n", pcmp->lapicbase, va);
if(va == nil)
panic("pcmpinit: cannot map lapic %.8lux", pcmp->lapicbase);
p = ((uchar*)pcmp)+PCMPsz;
e = ((uchar*)pcmp)+pcmp->length;
if(getconf("*dumpmp") != nil)
dumpmp(p, e);
if(getconf("*mp") != nil)
mpoverride(&p, &e);
/*
* Run through the table saving information needed for starting
* application processors and initialising any I/O APICs. The table
* is guaranteed to be in order such that only one pass is necessary.
*/
while(p < e) switch(*p){
default:
print("pcmpinit: unknown PCMP type 0x%uX (e-p 0x%luX)\n",
*p, e-p);
while(p < e){
print("%uX ", *p);
p++;
}
break;
case PcmpPROCESSOR:
if(apic = mkprocessor((PCMPprocessor*)p)){
apic->addr = va;
apic->paddr = pcmp->lapicbase;
}
p += PCMPprocessorsz;
continue;
case PcmpBUS:
mkbus((PCMPbus*)p);
p += PCMPbussz;
continue;
case PcmpIOAPIC:
if(apic = mkioapic((PCMPioapic*)p))
ioapicinit(apic, apic->apicno);
p += PCMPioapicsz;
continue;
case PcmpIOINTR:
mkiointr((PCMPintr*)p);
p += PCMPintrsz;
continue;
case PcmpLINTR:
mklintr((PCMPintr*)p);
p += PCMPintrsz;
continue;
}
/*
* Ininitalize local APIC and start application processors.
*/
mpinit();
}
void
mpinit(void)
{
int ncpu;
char *cp;
PCMP *pcmp;
uchar *e, *p;
Apic *apic, *bpapic;
i8259init();
syncclock();
if(_mp_ == 0)
return;
pcmp = KADDR(_mp_->physaddr);
/*
* Map the local APIC.
*/
if(mmukmap(pcmp->lapicbase, 0, 1024) == 0)
return;
bpapic = nil;
/*
* Run through the table saving information needed for starting
* application processors and initialising any I/O APICs. The table
* is guaranteed to be in order such that only one pass is necessary.
*/
p = ((uchar*)pcmp)+sizeof(PCMP);
e = ((uchar*)pcmp)+pcmp->length;
while(p < e) switch(*p){
default:
print("mpinit: unknown PCMP type 0x%uX (e-p 0x%luX)\n",
*p, e-p);
while(p < e){
print("%uX ", *p);
p++;
}
break;
case PcmpPROCESSOR:
if(apic = mkprocessor((PCMPprocessor*)p)){
/*
* Must take a note of bootstrap processor APIC
* now as it will be needed in order to start the
* application processors later and there's no
* guarantee that the bootstrap processor appears
* first in the table before the others.
*/
apic->addr = KADDR(pcmp->lapicbase);
if(apic->flags & PcmpBP)
bpapic = apic;
}
p += sizeof(PCMPprocessor);
continue;
case PcmpBUS:
mkbus((PCMPbus*)p);
p += sizeof(PCMPbus);
continue;
case PcmpIOAPIC:
if(apic = mkioapic((PCMPioapic*)p))
ioapicinit(apic, ((PCMPioapic*)p)->apicno);
p += sizeof(PCMPioapic);
continue;
case PcmpIOINTR:
mkiointr((PCMPintr*)p);
p += sizeof(PCMPintr);
continue;
case PcmpLINTR:
mklintr((PCMPintr*)p);
p += sizeof(PCMPintr);
continue;
}
/*
* No bootstrap processor, no need to go further.
*/
if(bpapic == 0)
return;
lapicinit(bpapic);
lock(&mprdthilock);
mprdthi |= (1<<bpapic->apicno)<<24;
unlock(&mprdthilock);
/*
* These interrupts are local to the processor
* and do not appear in the I/O APIC so it is OK
* to set them now.
*/
intrenable(IrqTIMER, lapicclock, 0, BUSUNKNOWN, "clock");
intrenable(IrqERROR, lapicerror, 0, BUSUNKNOWN, "lapicerror");
intrenable(IrqSPURIOUS, lapicspurious, 0, BUSUNKNOWN, "lapicspurious");
lapiconline();
checkmtrr();
/*
* Initialise the application processors.
*/
if(cp = getconf("*ncpu")){
ncpu = strtol(cp, 0, 0);
if(ncpu < 1)
ncpu = 1;
}
else
ncpu = MaxAPICNO;
memmove((void*)APBOOTSTRAP, apbootstrap, sizeof(apbootstrap));
for(apic = mpapic; apic <= &mpapic[MaxAPICNO]; apic++){
if(ncpu <= 1)
break;
if((apic->flags & (PcmpBP|PcmpEN)) == PcmpEN
&& apic->type == PcmpPROCESSOR){
mpstartap(apic);
conf.nmach++;
ncpu--;
}
}
/*
* we don't really know the number of processors till
* here.
*
* set conf.copymode here if nmach > 1.
* Should look for an ExtINT line and enable it.
*/
if(X86FAMILY(m->cpuidax) == 3 || conf.nmach > 1)
conf.copymode = 1;
}
int mpacpi(int ncleft)
{
char *already;
int np, bp;
Apic *apic;
Apicst *st;
Madt *mt;
/* If we don't have an mpisabusno yet, it's because the MP tables failed to
* parse. So we'll just take the last one available. I think we're
* supposed to parse the ACPI shit with the AML to figure out the buses and
* find a clear one, but f**k that. Note this busno is just for our own
* RDT/Rbus bookkeeping. */
if (mpisabusno == -1)
mpisabusno = Nbus - 1;
if (apics == nil)
return ncleft;
mt = apics->tbl;
if (mt == nil)
return ncleft;
print("APIC lapic paddr %#.8llx, flags %#.8x\n",
mt->lapicpa, mt->pcat);
np = 0;
//print("apics->st %p\n", apics->st);
for (int i = 0; i < apics->nchildren; i++) {
st = apics->children[i]->tbl;
already = "";
switch (st->type) {
case ASlapic:
print("ASlapic %d\n", st->lapic.id);
/* this table is supposed to have all of them if it exists */
if (st->lapic.id > Napic)
break;
apic = xlapic + st->lapic.id;
bp = (np++ == 0);
if (apic->useable) {
already = "(mp)";
} else if (ncleft != 0) {
ncleft--;
apicinit(st->lapic.id, mt->lapicpa, bp);
} else
already = "(off)";
print("apic proc %d/%d apicid %d %s\n", np - 1, apic->Lapic.machno,
st->lapic.id, already);
break;
case ASioapic:
print("ASioapic %d\n", st->ioapic.id);
if (st->ioapic.id > Napic){
print("ASioapic: %d is > %d, ignoring\n", st->ioapic.id, Napic);
break;
}
apic = xioapic + st->ioapic.id;
if (apic->useable) {
already = "(mp)";
goto pr1;
}
ioapicinit(st->ioapic.id, st->ioapic.ibase, st->ioapic.addr);
pr1:
apic->Ioapic.gsib = st->ioapic.ibase;
print("ioapic %d ", st->ioapic.id);
print("addr %p ibase %d %s\n", st->ioapic.addr, st->ioapic.ibase,
already);
break;
}
}
return ncleft;
}
int mpacpi(int ncleft)
{
char *already;
int np, bp;
struct apic *apic;
struct Apicst *st;
/* If we don't have an mpisabusno yet, it's because the MP tables failed to
* parse. So we'll just take the last one available. I think we're
* supposed to parse the ACPI shit with the AML to figure out the buses and
* find a clear one, but f**k that. Note this busno is just for our own
* RDT/Rbus bookkeeping. */
if (mpisabusno == -1)
mpisabusno = Nbus - 1;
if (apics == NULL)
return ncleft;
printd("APIC lapic paddr %#.8llux, flags %#.8ux\n",
apics->lapicpa, apics->pcat);
np = 0;
printd("apics->st %p\n", apics->st);
for (st = apics->st; st != NULL; st = st->next) {
already = "";
switch (st->type) {
case ASlapic:
printd("ASlapic %d\n", st->lapic.id);
/* this table is supposed to have all of them if it exists */
if (st->lapic.id > MaxAPICNO)
break;
apic = xlapic + st->lapic.id;
bp = (np++ == 0);
if (apic->useable) {
already = "(mp)";
} else if (ncleft != 0) {
ncleft--;
apicinit(st->lapic.id, apics->lapicpa, bp);
} else
already = "(off)";
printd("apic proc %d/%d apicid %d %s\n", np - 1, apic->machno,
st->lapic.id, already);
break;
case ASioapic:
printd("ASioapic %d\n", st->ioapic.id);
if (st->ioapic.id > Napic)
break;
apic = xioapic + st->ioapic.id;
if (apic->useable) {
apic->ibase = st->ioapic.ibase; /* gnarly */
already = "(mp)";
goto pr1;
}
ioapicinit(st->ioapic.id, st->ioapic.ibase, st->ioapic.addr);
pr1:
printd("ioapic %d ", st->ioapic.id);
printd("addr %p base %d %s\n", apic->paddr, apic->ibase,
already);
break;
}
}
return ncleft;
}
void
kinitlong(unsigned long pmemsz)
{
#if (NEWTMR)
uint32_t tmrcnt = 0;
#endif
/* initialise interrupt management */
#if (VBE)
trapinitprot();
#endif
/* initialise virtual memory */
vminitlong((uint64_t *)kernpagemapl4tab);
#if 0
/* FIXME: map possible device memory */
vmmapseg((uint32_t *)&_pagetab, DEVMEMBASE, DEVMEMBASE, 0xffffffffU,
PAGEPRES | PAGEWRITE | PAGENOCACHE);
#endif
// schedinit();
/* zero kernel BSS segment */
kbzero(&_bssvirt, (uint32_t)&_ebssvirt - (uint32_t)&_bssvirt);
/* set kernel I/O permission bitmap to all 1-bits */
kmemset(&kerniomap, 0xff, sizeof(kerniomap));
/* INITIALIZE CONSOLES AND SCREEN */
#if (VBE)
vbeinitscr();
#endif
#if (VBE) && (NEWFONT)
consinit(768 / vbefontw, 1024 / vbefonth);
#elif (VBE)
consinit(768 >> 3, 1024 >> 3);
#endif
/* TODO: use memory map from GRUB? */
// vminitphys((uintptr_t)&_epagetab, pmemsz);
vminitphys((uintptr_t)&_epagetab, pmemsz);
meminit(pmemsz);
tssinit(0);
#if (VBE) && (NEWFONT)
// consinit(768 / vbefontw, 1024 / vbefonth);
#elif (VBE)
consinit(768 >> 3, 1024 >> 3);
#endif
#if (SMBIOS)
smbiosinit();
#endif
#if (PS2DRV)
ps2init();
#endif
#if (VBE) && (PLASMA)
plasmaloop();
#endif
#if (VBE)
vbeprintinfo();
#endif
logoprint();
// vminitphys((uintptr_t)&_ebss, pmemsz - (unsigned long)&_ebss);
/* HID devices */
#if (PCI)
/* initialise PCI bus driver */
pciinit();
#endif
#if (ATA)
/* initialise ATA driver */
atainit();
#endif
#if (SB16)
/* initialise Soundblaster 16 driver */
sb16init();
#endif
#if (ACPI)
/* initialise ACPI subsystem */
acpiinit();
#endif
/* initialise block I/O buffer cache */
if (!bufinit()) {
kprintf("failed to allocate buffer cache\n");
while (1) {
;
}
}
/* allocate unused device regions (in 3.5G..4G) */
// pageaddzone(DEVMEMBASE, &vmshmq, 0xffffffffU - DEVMEMBASE + 1);
#if (SMP) || (APIC)
//#if (SMP)
/* multiprocessor initialisation */
// mpinit();
//#endif
if (mpncpu == 1) {
kprintf("found %ld processor\n", mpncpu);
} else {
kprintf("found %ld processors\n", mpncpu);
}
#if (HPET)
/* initialise high precision event timers */
hpetinit();
#endif
#if (NEWTMR)
tmrcnt = apicinitcpu(0);
#else
apicinitcpu(0);
#endif
#if (IOAPIC)
ioapicinit(0);
#endif
#endif /* SMP || APIC */
#if (SMP)
if (mpmultiproc) {
mpstart();
}
#endif
/* CPU interface */
taskinit();
// tssinit(0);
// machinit();
/* execution environment */
procinit(PROCKERN);
// k_curtask = &k_curproc->task;
// sysinit();
kprintf("DMA buffers (%ul x %ul kilobytes) @ 0x%p\n",
DMANCHAN, DMACHANBUFSIZE >> 10, DMABUFBASE);
kprintf("VM page tables @ 0x%p\n", (unsigned long)&_pagetab);
// kprintf("%ld kilobytes physical memory\n", pmemsz >> 10);
kprintf("%ld kilobytes kernel memory\n", (uint32_t)&_ebss >> 10);
kprintf("%ld kilobytes allocated physical memory (%ld wired, %ld total)\n",
(vmpagestat.nwired + vmpagestat.nmapped + vmpagestat.nbuf) << (PAGESIZELOG2 - 10),
vmpagestat.nwired << (PAGESIZELOG2 - 10),
vmpagestat.nphys << (PAGESIZELOG2 - 10));
k_curcpu = &cputab[0];
cpuinit(k_curcpu);
schedinit();
#if (APIC)
apicstarttmr(tmrcnt);
#else
pitinit();
#endif
schedloop();
/* NOTREACHED */
}
void
mpinit(void)
{
int ncpu, cpuson;
char *cp;
PCMP *pcmp;
uchar *e, *p;
Apic *apic, *bpapic;
void *va;
mpdebug = getconf("*debugmp") != nil;
i8259init();
syncclock();
bpapic = nil;
cpuson = 0;
if(_mp_ == 0) {
/*
* We can easily get processor info from ACPI, but
* interrupt routing, etc. would require interpreting AML.
*/
print("mpinit: no mp table found, assuming uniprocessor\n");
archrevert();
return;
}
pcmp = KADDR(_mp_->physaddr);
/*
* Map the local APIC.
*/
if((va = vmap(pcmp->lapicbase, 1024)) == nil)
return;
mppcmp = pcmp;
print("LAPIC: %#lux %#lux\n", pcmp->lapicbase, (ulong)va);
/*
* Run through the table saving information needed for starting
* application processors and initialising any I/O APICs. The table
* is guaranteed to be in order such that only one pass is necessary.
*/
p = ((uchar*)pcmp)+sizeof(PCMP);
e = ((uchar*)pcmp)+pcmp->length;
while(p < e) switch(*p){
default:
print("mpinit: unknown PCMP type 0x%uX (e-p 0x%luX)\n",
*p, e-p);
while(p < e){
print("%uX ", *p);
p++;
}
break;
case PcmpPROCESSOR:
if(apic = mkprocessor((PCMPprocessor*)p)){
/*
* Must take a note of bootstrap processor APIC
* now as it will be needed in order to start the
* application processors later and there's no
* guarantee that the bootstrap processor appears
* first in the table before the others.
*/
apic->addr = va;
apic->paddr = pcmp->lapicbase;
if(apic->flags & PcmpBP)
bpapic = apic;
cpuson++;
}
p += sizeof(PCMPprocessor);
continue;
case PcmpBUS:
mkbus((PCMPbus*)p);
p += sizeof(PCMPbus);
continue;
case PcmpIOAPIC:
if(apic = mkioapic((PCMPioapic*)p))
ioapicinit(apic, ((PCMPioapic*)p)->apicno);
p += sizeof(PCMPioapic);
continue;
case PcmpIOINTR:
mkiointr((PCMPintr*)p);
p += sizeof(PCMPintr);
continue;
case PcmpLINTR:
mklintr((PCMPintr*)p);
p += sizeof(PCMPintr);
continue;
}
dprint("mpinit: mp table describes %d cpus\n", cpuson);
/* For now, always scan ACPI's MADT for processors that MP missed. */
trympacpi();
if (bpapic == nil)
bpapic = bootapic;
/*
* No bootstrap processor, no need to go further.
*/
if(bpapic == 0)
return;
bpapic->online = 1;
lapicinit(bpapic);
/*
* These interrupts are local to the processor
* and do not appear in the I/O APIC so it is OK
* to set them now.
*/
intrenable(IrqTIMER, lapicclock, 0, BUSUNKNOWN, "clock");
intrenable(IrqERROR, lapicerror, 0, BUSUNKNOWN, "lapicerror");
intrenable(IrqSPURIOUS, lapicspurious, 0, BUSUNKNOWN, "lapicspurious");
lapiconline();
checkmtrr();
/*
* Initialise the application processors.
*/
if(cp = getconf("*ncpu")){
ncpu = strtol(cp, 0, 0);
if(ncpu < 1)
ncpu = 1;
else if(ncpu > MAXMACH)
ncpu = MAXMACH;
}
else
ncpu = MAXMACH;
memmove((void*)APBOOTSTRAP, apbootstrap, sizeof(apbootstrap));
for(apic = mpapic; apic <= &mpapic[MaxAPICNO]; apic++){
if(ncpu <= 1)
break;
if((apic->flags & (PcmpBP|PcmpEN)) == PcmpEN
&& apic->type == PcmpPROCESSOR){
mpstartap(apic);
conf.nmach++;
ncpu--;
}
}
/*
* we don't really know the number of processors till
* here.
*
* set conf.copymode here if nmach > 1.
* Should look for an ExtINT line and enable it.
*/
if(X86FAMILY(m->cpuidax) == 3 || conf.nmach > 1)
conf.copymode = 1;
}
