static void bcma_host_pci_write16(struct bcma_device *core, u16 offset,
u16 value)
{
offset += bcma_host_pci_provide_access_to_core(core);
iowrite16(value, core->bus->mmio + offset);
}
static inline void iaputword(struct intel8x0m *chip, u32 offset, u16 val)
{
iowrite16(val, chip->addr + offset);
}
void outw(u16 b, unsigned long port)
{
iowrite16(b, ioport_map(port, 2));
}
static int __devinit scoop_probe(struct platform_device *pdev)
{
struct scoop_dev *devptr;
struct scoop_config *inf;
struct resource *mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
int ret;
int temp;
if (!mem)
return -EINVAL;
devptr = kzalloc(sizeof(struct scoop_dev), GFP_KERNEL);
if (!devptr)
return -ENOMEM;
spin_lock_init(&devptr->scoop_lock);
inf = pdev->dev.platform_data;
devptr->base = ioremap(mem->start, mem->end - mem->start + 1);
if (!devptr->base) {
ret = -ENOMEM;
goto err_ioremap;
}
platform_set_drvdata(pdev, devptr);
printk("Sharp Scoop Device found at 0x%08x -> 0x%8p\n",(unsigned int)mem->start, devptr->base);
iowrite16(0x0140, devptr->base + SCOOP_MCR);
reset_scoop(&pdev->dev);
iowrite16(0x0000, devptr->base + SCOOP_CPR);
iowrite16(inf->io_dir & 0xffff, devptr->base + SCOOP_GPCR);
iowrite16(inf->io_out & 0xffff, devptr->base + SCOOP_GPWR);
devptr->suspend_clr = inf->suspend_clr;
devptr->suspend_set = inf->suspend_set;
devptr->gpio.base = -1;
if (inf->gpio_base != 0) {
devptr->gpio.label = dev_name(&pdev->dev);
devptr->gpio.base = inf->gpio_base;
devptr->gpio.ngpio = 12; /* PA11 = 0, PA12 = 1, etc. up to PA22 = 11 */
devptr->gpio.set = scoop_gpio_set;
devptr->gpio.get = scoop_gpio_get;
devptr->gpio.direction_input = scoop_gpio_direction_input;
devptr->gpio.direction_output = scoop_gpio_direction_output;
ret = gpiochip_add(&devptr->gpio);
if (ret)
goto err_gpio;
}
return 0;
if (devptr->gpio.base != -1)
temp = gpiochip_remove(&devptr->gpio);
err_gpio:
platform_set_drvdata(pdev, NULL);
err_ioremap:
iounmap(devptr->base);
kfree(devptr);
return ret;
}
int mif_test_dpram(char *dp_name, void __iomem *start, u16 bytes)
{
u16 i;
u16 words = bytes >> 1;
u16 __iomem *dst = (u16 __iomem *)start;
u16 val;
int err_cnt = 0;
mif_err("%s: start 0x%p, bytes %d\n", dp_name, start, bytes);
mif_err("%s: 0/6 stage ...\n", dp_name);
for (i = 1; i <= 100; i++) {
iowrite16(0x1234, dst);
val = ioread16(dst);
if (val != 0x1234) {
mif_err("%s: [0x0000] read 0x%04X != written 0x1234 "
"(try# %d)\n", dp_name, val, i);
err_cnt++;
}
}
if (err_cnt > 0) {
mif_err("%s: FAIL!!!\n", dp_name);
return -EINVAL;
}
mif_err("%s: 1/6 stage ...\n", dp_name);
dst = (u16 __iomem *)start;
for (i = 0; i < words; i++) {
iowrite16(0, dst);
dst++;
}
dst = (u16 __iomem *)start;
for (i = 0; i < words; i++) {
val = ioread16(dst);
if (val != 0x0000) {
mif_err("%s: ERR! [0x%04X] read 0x%04X != written "
"0x0000\n", dp_name, i, val);
err_cnt++;
}
dst++;
}
if (err_cnt > 0) {
mif_err("%s: FAIL!!!\n", dp_name);
return -EINVAL;
}
mif_err("%s: 2/6 stage ...\n", dp_name);
dst = (u16 __iomem *)start;
for (i = 0; i < words; i++) {
iowrite16(0xFFFF, dst);
dst++;
}
dst = (u16 __iomem *)start;
for (i = 0; i < words; i++) {
val = ioread16(dst);
if (val != 0xFFFF) {
mif_err("%s: ERR! [0x%04X] read 0x%04X != written "
"0xFFFF\n", dp_name, i, val);
err_cnt++;
}
dst++;
}
if (err_cnt > 0) {
mif_err("%s: FAIL!!!\n", dp_name);
return -EINVAL;
}
mif_err("%s: 3/6 stage ...\n", dp_name);
dst = (u16 __iomem *)start;
for (i = 0; i < words; i++) {
iowrite16(0x00FF, dst);
dst++;
}
dst = (u16 __iomem *)start;
for (i = 0; i < words; i++) {
val = ioread16(dst);
if (val != 0x00FF) {
mif_err("%s: ERR! [0x%04X] read 0x%04X != written "
"0x00FF\n", dp_name, i, val);
err_cnt++;
}
dst++;
}
if (err_cnt > 0) {
mif_err("%s: FAIL!!!\n", dp_name);
return -EINVAL;
}
mif_err("%s: 4/6 stage ...\n", dp_name);
dst = (u16 __iomem *)start;
for (i = 0; i < words; i++) {
iowrite16(0x0FF0, dst);
dst++;
}
dst = (u16 __iomem *)start;
for (i = 0; i < words; i++) {
val = ioread16(dst);
if (val != 0x0FF0) {
mif_err("%s: ERR! [0x%04X] read 0x%04X != written "
"0x0FF0\n", dp_name, i, val);
err_cnt++;
}
dst++;
}
if (err_cnt > 0) {
mif_err("%s: FAIL!!!\n", dp_name);
return -EINVAL;
}
mif_err("%s: 5/6 stage ...\n", dp_name);
dst = (u16 __iomem *)start;
for (i = 0; i < words; i++) {
iowrite16(0xFF00, dst);
dst++;
}
dst = (u16 __iomem *)start;
for (i = 0; i < words; i++) {
val = ioread16(dst);
if (val != 0xFF00) {
mif_err("%s: ERR! [0x%04X] read 0x%04X != written "
"0xFF00\n", dp_name, i, val);
err_cnt++;
}
dst++;
}
mif_err("%s: 6/6 stage ...\n", dp_name);
dst = (u16 __iomem *)start;
for (i = 0; i < words; i++) {
iowrite16((i & 0xFFFF), dst);
dst++;
}
dst = (u16 __iomem *)start;
for (i = 0; i < words; i++) {
val = ioread16(dst);
if (val != (i & 0xFFFF)) {
mif_err("%s: ERR! [0x%04X] read 0x%04X != written "
"0x%04X\n", dp_name, i, val, (i & 0xFFFF));
err_cnt++;
}
dst++;
}
if (err_cnt > 0) {
mif_err("%s: FAIL!!!\n", dp_name);
return -EINVAL;
}
mif_err("%s: PASS!!!\n", dp_name);
dst = (u16 __iomem *)start;
for (i = 0; i < words; i++) {
iowrite16(0, dst);
dst++;
}
return 0;
}
static inline void cmc221_idpram_reset(struct dpram_link_device *dpld)
{
iowrite16(1, dpld->sfr.reset);
}
static void cmc221_idpram_clr_int2ap(struct dpram_link_device *dpld)
{
iowrite16(0xFFFF, dpld->sfr.clr_int2ap);
}
static inline void o2scr_write(struct o2scr_info *info, int reg, u16 val)
{
return iowrite16(val, info->mem + reg);
}
static int __devinit tc6393xb_probe(struct platform_device *dev)
{
struct tc6393xb_platform_data *tcpd = dev->dev.platform_data;
struct tc6393xb *tc6393xb;
struct resource *iomem, *rscr;
int ret, temp;
iomem = platform_get_resource(dev, IORESOURCE_MEM, 0);
if (!iomem)
return -EINVAL;
tc6393xb = kzalloc(sizeof *tc6393xb, GFP_KERNEL);
if (!tc6393xb) {
ret = -ENOMEM;
goto err_kzalloc;
}
spin_lock_init(&tc6393xb->lock);
platform_set_drvdata(dev, tc6393xb);
ret = platform_get_irq(dev, 0);
if (ret >= 0)
tc6393xb->irq = ret;
else
goto err_noirq;
tc6393xb->iomem = iomem;
tc6393xb->irq_base = tcpd->irq_base;
tc6393xb->clk = clk_get(&dev->dev, "CLK_CK3P6MI");
if (IS_ERR(tc6393xb->clk)) {
ret = PTR_ERR(tc6393xb->clk);
goto err_clk_get;
}
rscr = &tc6393xb->rscr;
rscr->name = "tc6393xb-core";
rscr->start = iomem->start;
rscr->end = iomem->start + 0xff;
rscr->flags = IORESOURCE_MEM;
ret = request_resource(iomem, rscr);
if (ret)
goto err_request_scr;
tc6393xb->scr = ioremap(rscr->start, resource_size(rscr));
if (!tc6393xb->scr) {
ret = -ENOMEM;
goto err_ioremap;
}
ret = clk_enable(tc6393xb->clk);
if (ret)
goto err_clk_enable;
ret = tcpd->enable(dev);
if (ret)
goto err_enable;
iowrite8(0, tc6393xb->scr + SCR_FER);
iowrite16(tcpd->scr_pll2cr, tc6393xb->scr + SCR_PLL2CR);
iowrite16(SCR_CCR_UNK1 | SCR_CCR_HCLK_48,
tc6393xb->scr + SCR_CCR);
iowrite16(SCR_MCR_RDY_OPENDRAIN | SCR_MCR_RDY_UNK | SCR_MCR_RDY_EN |
SCR_MCR_INT_OPENDRAIN | SCR_MCR_INT_UNK | SCR_MCR_INT_EN |
BIT(15), tc6393xb->scr + SCR_MCR);
iowrite16(tcpd->scr_gper, tc6393xb->scr + SCR_GPER);
iowrite8(0, tc6393xb->scr + SCR_IRR);
iowrite8(0xbf, tc6393xb->scr + SCR_IMR);
printk(KERN_INFO "Toshiba tc6393xb revision %d at 0x%08lx, irq %d\n",
tmio_ioread8(tc6393xb->scr + SCR_REVID),
(unsigned long) iomem->start, tc6393xb->irq);
tc6393xb->gpio.base = -1;
if (tcpd->gpio_base >= 0) {
ret = tc6393xb_register_gpio(tc6393xb, tcpd->gpio_base);
if (ret)
goto err_gpio_add;
}
tc6393xb_attach_irq(dev);
if (tcpd->setup) {
ret = tcpd->setup(dev);
if (ret)
goto err_setup;
}
tc6393xb_cells[TC6393XB_CELL_NAND].platform_data = tcpd->nand_data;
tc6393xb_cells[TC6393XB_CELL_NAND].pdata_size =
sizeof(*tcpd->nand_data);
tc6393xb_cells[TC6393XB_CELL_FB].platform_data = tcpd->fb_data;
tc6393xb_cells[TC6393XB_CELL_FB].pdata_size = sizeof(*tcpd->fb_data);
ret = mfd_add_devices(&dev->dev, dev->id,
tc6393xb_cells, ARRAY_SIZE(tc6393xb_cells),
iomem, tcpd->irq_base);
if (!ret)
return 0;
if (tcpd->teardown)
tcpd->teardown(dev);
err_setup:
tc6393xb_detach_irq(dev);
err_gpio_add:
if (tc6393xb->gpio.base != -1)
temp = gpiochip_remove(&tc6393xb->gpio);
tcpd->disable(dev);
err_enable:
clk_disable(tc6393xb->clk);
err_clk_enable:
iounmap(tc6393xb->scr);
err_ioremap:
release_resource(&tc6393xb->rscr);
err_request_scr:
clk_put(tc6393xb->clk);
err_noirq:
err_clk_get:
kfree(tc6393xb);
err_kzalloc:
return ret;
}
int softing_load_app_fw(const char *file, struct softing *card)
{
const struct firmware *fw;
const uint8_t *mem, *end, *dat;
int ret, j;
uint16_t type, len;
uint32_t addr, start_addr = 0;
unsigned int sum, rx_sum;
int8_t type_end = 0, type_entrypoint = 0;
ret = reject_firmware(&fw, file, &card->pdev->dev);
if (ret) {
dev_alert(&card->pdev->dev, "reject_firmware(%s) got %i\n",
file, ret);
return ret;
}
dev_dbg(&card->pdev->dev, "firmware(%s) got %lu bytes\n",
file, (unsigned long)fw->size);
/* parse the firmware */
mem = fw->data;
end = &mem[fw->size];
/* look for header record */
ret = fw_parse(&mem, &type, &addr, &len, &dat);
if (ret)
goto failed;
ret = -EINVAL;
if (type != 0xffff) {
dev_alert(&card->pdev->dev, "firmware starts with type 0x%x\n",
type);
goto failed;
}
if (strncmp("Structured Binary Format, Softing GmbH", dat, len)) {
dev_alert(&card->pdev->dev, "firmware string '%.*s' fault\n",
len, dat);
goto failed;
}
/* ok, we had a header */
while (mem < end) {
ret = fw_parse(&mem, &type, &addr, &len, &dat);
if (ret)
goto failed;
if (type == 3) {
/* start address */
start_addr = addr;
type_entrypoint = 1;
continue;
} else if (type == 1) {
/* eof */
type_end = 1;
break;
} else if (type != 0) {
dev_alert(&card->pdev->dev,
"unknown record type 0x%04x\n", type);
ret = -EINVAL;
goto failed;
}
/* regualar data */
for (sum = 0, j = 0; j < len; ++j)
sum += dat[j];
/* work in 16bit (target) */
sum &= 0xffff;
memcpy_toio(&card->dpram[card->pdat->app.offs], dat, len);
iowrite32(card->pdat->app.offs + card->pdat->app.addr,
&card->dpram[DPRAM_COMMAND + 2]);
iowrite32(addr, &card->dpram[DPRAM_COMMAND + 6]);
iowrite16(len, &card->dpram[DPRAM_COMMAND + 10]);
iowrite8(1, &card->dpram[DPRAM_COMMAND + 12]);
ret = softing_bootloader_command(card, 1, "loading app.");
if (ret < 0)
goto failed;
/* verify checksum */
rx_sum = ioread16(&card->dpram[DPRAM_RECEIPT + 2]);
if (rx_sum != sum) {
dev_alert(&card->pdev->dev, "SRAM seems to be damaged"
", wanted 0x%04x, got 0x%04x\n", sum, rx_sum);
ret = -EIO;
goto failed;
}
}
if (!type_end || !type_entrypoint)
goto failed;
/* start application in card */
iowrite32(start_addr, &card->dpram[DPRAM_COMMAND + 2]);
iowrite8(1, &card->dpram[DPRAM_COMMAND + 6]);
ret = softing_bootloader_command(card, 3, "start app.");
if (ret < 0)
goto failed;
ret = 0;
failed:
release_firmware(fw);
if (ret < 0)
dev_info(&card->pdev->dev, "firmware %s failed\n", file);
return ret;
}
int softing_startstop(struct net_device *dev, int up)
{
int ret;
struct softing *card;
struct softing_priv *priv;
struct net_device *netdev;
int bus_bitmask_start;
int j, error_reporting;
struct can_frame msg;
const struct can_bittiming *bt;
priv = netdev_priv(dev);
card = priv->card;
if (!card->fw.up)
return -EIO;
ret = mutex_lock_interruptible(&card->fw.lock);
if (ret)
return ret;
bus_bitmask_start = 0;
if (dev && up)
/* prepare to start this bus as well */
bus_bitmask_start |= (1 << priv->index);
/* bring netdevs down */
for (j = 0; j < ARRAY_SIZE(card->net); ++j) {
netdev = card->net[j];
if (!netdev)
continue;
priv = netdev_priv(netdev);
if (dev != netdev)
netif_stop_queue(netdev);
if (netif_running(netdev)) {
if (dev != netdev)
bus_bitmask_start |= (1 << j);
priv->tx.pending = 0;
priv->tx.echo_put = 0;
priv->tx.echo_get = 0;
/*
* this bus' may just have called open_candev()
* which is rather stupid to call close_candev()
* already
* but we may come here from busoff recovery too
* in which case the echo_skb _needs_ flushing too.
* just be sure to call open_candev() again
*/
close_candev(netdev);
}
priv->can.state = CAN_STATE_STOPPED;
}
card->tx.pending = 0;
softing_enable_irq(card, 0);
ret = softing_reset_chip(card);
if (ret)
goto failed;
if (!bus_bitmask_start)
/* no busses to be brought up */
goto card_done;
if ((bus_bitmask_start & 1) && (bus_bitmask_start & 2)
&& (softing_error_reporting(card->net[0])
!= softing_error_reporting(card->net[1]))) {
dev_alert(&card->pdev->dev,
"err_reporting flag differs for busses\n");
goto invalid;
}
error_reporting = 0;
if (bus_bitmask_start & 1) {
netdev = card->net[0];
priv = netdev_priv(netdev);
error_reporting += softing_error_reporting(netdev);
/* init chip 1 */
bt = &priv->can.bittiming;
iowrite16(bt->brp, &card->dpram[DPRAM_FCT_PARAM + 2]);
iowrite16(bt->sjw, &card->dpram[DPRAM_FCT_PARAM + 4]);
iowrite16(bt->phase_seg1 + bt->prop_seg,
&card->dpram[DPRAM_FCT_PARAM + 6]);
iowrite16(bt->phase_seg2, &card->dpram[DPRAM_FCT_PARAM + 8]);
iowrite16((priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) ? 1 : 0,
&card->dpram[DPRAM_FCT_PARAM + 10]);
ret = softing_fct_cmd(card, 1, "initialize_chip[0]");
if (ret < 0)
goto failed;
/* set mode */
iowrite16(0, &card->dpram[DPRAM_FCT_PARAM + 2]);
iowrite16(0, &card->dpram[DPRAM_FCT_PARAM + 4]);
ret = softing_fct_cmd(card, 3, "set_mode[0]");
if (ret < 0)
goto failed;
/* set filter */
/* 11bit id & mask */
iowrite16(0x0000, &card->dpram[DPRAM_FCT_PARAM + 2]);
iowrite16(0x07ff, &card->dpram[DPRAM_FCT_PARAM + 4]);
/* 29bit id.lo & mask.lo & id.hi & mask.hi */
iowrite16(0x0000, &card->dpram[DPRAM_FCT_PARAM + 6]);
iowrite16(0xffff, &card->dpram[DPRAM_FCT_PARAM + 8]);
iowrite16(0x0000, &card->dpram[DPRAM_FCT_PARAM + 10]);
iowrite16(0x1fff, &card->dpram[DPRAM_FCT_PARAM + 12]);
ret = softing_fct_cmd(card, 7, "set_filter[0]");
if (ret < 0)
goto failed;
/* set output control */
iowrite16(priv->output, &card->dpram[DPRAM_FCT_PARAM + 2]);
ret = softing_fct_cmd(card, 5, "set_output[0]");
if (ret < 0)
goto failed;
}
if (bus_bitmask_start & 2) {
netdev = card->net[1];
priv = netdev_priv(netdev);
error_reporting += softing_error_reporting(netdev);
/* init chip2 */
bt = &priv->can.bittiming;
iowrite16(bt->brp, &card->dpram[DPRAM_FCT_PARAM + 2]);
iowrite16(bt->sjw, &card->dpram[DPRAM_FCT_PARAM + 4]);
iowrite16(bt->phase_seg1 + bt->prop_seg,
&card->dpram[DPRAM_FCT_PARAM + 6]);
iowrite16(bt->phase_seg2, &card->dpram[DPRAM_FCT_PARAM + 8]);
iowrite16((priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) ? 1 : 0,
&card->dpram[DPRAM_FCT_PARAM + 10]);
ret = softing_fct_cmd(card, 2, "initialize_chip[1]");
if (ret < 0)
goto failed;
/* set mode2 */
iowrite16(0, &card->dpram[DPRAM_FCT_PARAM + 2]);
iowrite16(0, &card->dpram[DPRAM_FCT_PARAM + 4]);
ret = softing_fct_cmd(card, 4, "set_mode[1]");
if (ret < 0)
goto failed;
/* set filter2 */
/* 11bit id & mask */
iowrite16(0x0000, &card->dpram[DPRAM_FCT_PARAM + 2]);
iowrite16(0x07ff, &card->dpram[DPRAM_FCT_PARAM + 4]);
/* 29bit id.lo & mask.lo & id.hi & mask.hi */
iowrite16(0x0000, &card->dpram[DPRAM_FCT_PARAM + 6]);
iowrite16(0xffff, &card->dpram[DPRAM_FCT_PARAM + 8]);
iowrite16(0x0000, &card->dpram[DPRAM_FCT_PARAM + 10]);
iowrite16(0x1fff, &card->dpram[DPRAM_FCT_PARAM + 12]);
ret = softing_fct_cmd(card, 8, "set_filter[1]");
if (ret < 0)
goto failed;
/* set output control2 */
iowrite16(priv->output, &card->dpram[DPRAM_FCT_PARAM + 2]);
ret = softing_fct_cmd(card, 6, "set_output[1]");
if (ret < 0)
goto failed;
}
/* enable_error_frame */
/*
* Error reporting is switched off at the moment since
* the receiving of them is not yet 100% verified
* This should be enabled sooner or later
*
if (error_reporting) {
ret = softing_fct_cmd(card, 51, "enable_error_frame");
if (ret < 0)
goto failed;
}
*/
/* initialize interface */
iowrite16(1, &card->dpram[DPRAM_FCT_PARAM + 2]);
iowrite16(1, &card->dpram[DPRAM_FCT_PARAM + 4]);
iowrite16(1, &card->dpram[DPRAM_FCT_PARAM + 6]);
iowrite16(1, &card->dpram[DPRAM_FCT_PARAM + 8]);
iowrite16(1, &card->dpram[DPRAM_FCT_PARAM + 10]);
iowrite16(1, &card->dpram[DPRAM_FCT_PARAM + 12]);
iowrite16(1, &card->dpram[DPRAM_FCT_PARAM + 14]);
iowrite16(1, &card->dpram[DPRAM_FCT_PARAM + 16]);
iowrite16(1, &card->dpram[DPRAM_FCT_PARAM + 18]);
iowrite16(1, &card->dpram[DPRAM_FCT_PARAM + 20]);
ret = softing_fct_cmd(card, 17, "initialize_interface");
if (ret < 0)
goto failed;
/* enable_fifo */
ret = softing_fct_cmd(card, 36, "enable_fifo");
if (ret < 0)
goto failed;
/* enable fifo tx ack */
ret = softing_fct_cmd(card, 13, "fifo_tx_ack[0]");
if (ret < 0)
goto failed;
/* enable fifo tx ack2 */
ret = softing_fct_cmd(card, 14, "fifo_tx_ack[1]");
if (ret < 0)
goto failed;
/* start_chip */
ret = softing_fct_cmd(card, 11, "start_chip");
if (ret < 0)
goto failed;
iowrite8(0, &card->dpram[DPRAM_INFO_BUSSTATE]);
iowrite8(0, &card->dpram[DPRAM_INFO_BUSSTATE2]);
if (card->pdat->generation < 2) {
iowrite8(0, &card->dpram[DPRAM_V2_IRQ_TOHOST]);
/* flush the DPRAM caches */
wmb();
}
softing_initialize_timestamp(card);
/*
* do socketcan notifications/status changes
* from here, no errors should occur, or the failed: part
* must be reviewed
*/
memset(&msg, 0, sizeof(msg));
msg.can_id = CAN_ERR_FLAG | CAN_ERR_RESTARTED;
msg.can_dlc = CAN_ERR_DLC;
for (j = 0; j < ARRAY_SIZE(card->net); ++j) {
if (!(bus_bitmask_start & (1 << j)))
continue;
netdev = card->net[j];
if (!netdev)
continue;
priv = netdev_priv(netdev);
priv->can.state = CAN_STATE_ERROR_ACTIVE;
open_candev(netdev);
if (dev != netdev) {
/* notify other busses on the restart */
softing_netdev_rx(netdev, &msg, ktime_set(0, 0));
++priv->can.can_stats.restarts;
}
netif_wake_queue(netdev);
}
/* enable interrupts */
ret = softing_enable_irq(card, 1);
if (ret)
goto failed;
card_done:
mutex_unlock(&card->fw.lock);
return 0;
invalid:
ret = -EINVAL;
failed:
softing_enable_irq(card, 0);
softing_reset_chip(card);
mutex_unlock(&card->fw.lock);
/* bring all other interfaces down */
for (j = 0; j < ARRAY_SIZE(card->net); ++j) {
netdev = card->net[j];
if (!netdev)
continue;
dev_close(netdev);
}
return ret;
}
static inline void xiic_setreg16(struct xiic_i2c *i2c, int reg, u16 value)
{
iowrite16(value, i2c->base + reg);
}
static inline void
t6963c_write_cmd_port(u8 data)
{
iowrite16(data, t6963c_database + 2);
}
void hw_cursor_setData(struct lynx_cursor * cursor,
u16 rop,const u8* pcol,const u8* pmsk)
{
int i,j,count,pitch,offset;
u8 color,mask,opr;
u16 data;
void __iomem *pbuffer, *pstart;
/* in byte*/
pitch = cursor->w >> 3;
/* in byte */
count = pitch * cursor->h;
/* in byte */
offset = cursor->maxW * 2 / 8;
data = 0;
pstart = cursor->vstart;
pbuffer = pstart;
/*
if(odd &1){
hw_cursor_setData2(cursor,rop,pcol,pmsk);
}
odd++;
if(odd > 0xfffffff0)
odd=0;
*/
for(i=0;i<count;i++)
{
color = *pcol++;
mask = *pmsk++;
data = 0;
/* either method below works well,
* but method 2 shows no lag
* and method 1 seems a bit wrong*/
#if 0
if(rop == ROP_XOR)
opr = mask ^ color;
else
opr = mask & color;
for(j=0;j<8;j++)
{
if(opr & (0x80 >> j))
{ //use fg color,id = 2
data |= 2 << (j*2);
}else{
//use bg color,id = 1
data |= 1 << (j*2);
}
}
#else
for(j=0;j<8;j++){
if(mask & (0x80>>j)){
if(rop == ROP_XOR)
opr = mask ^ color;
else
opr = mask & color;
/* 2 stands for forecolor and 1 for backcolor */
data |= ((opr & (0x80>>j))?2:1)<<(j*2);
}
}
#endif
iowrite16(data, pbuffer);
/* assume pitch is 1,2,4,8,...*/
#if 0
if(!((i+1)&(pitch-1))) /* below line equal to is line */
#else
if((i+1) % pitch == 0)
#endif
{
/* need a return */
pstart += offset;
pbuffer = pstart;
}else{
pbuffer += sizeof(u16);
}
}
static inline void w5300_write_direct(struct w5300_priv *priv,
u16 addr, u16 data)
{
iowrite16(data, priv->base + (addr << CONFIG_WIZNET_BUS_SHIFT));
}
static int __devinit sh_keysc_probe(struct platform_device *pdev)
{
struct sh_keysc_priv *priv;
struct sh_keysc_info *pdata;
struct resource *res;
struct input_dev *input;
char clk_name[8];
int i;
int irq, error;
if (!pdev->dev.platform_data) {
dev_err(&pdev->dev, "no platform data defined\n");
error = -EINVAL;
goto err0;
}
error = -ENXIO;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (res == NULL) {
dev_err(&pdev->dev, "failed to get I/O memory\n");
goto err0;
}
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
dev_err(&pdev->dev, "failed to get irq\n");
goto err0;
}
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
if (priv == NULL) {
dev_err(&pdev->dev, "failed to allocate driver data\n");
error = -ENOMEM;
goto err0;
}
platform_set_drvdata(pdev, priv);
memcpy(&priv->pdata, pdev->dev.platform_data, sizeof(priv->pdata));
pdata = &priv->pdata;
priv->iomem_base = ioremap_nocache(res->start, res_size(res));
if (priv->iomem_base == NULL) {
dev_err(&pdev->dev, "failed to remap I/O memory\n");
error = -ENXIO;
goto err1;
}
snprintf(clk_name, sizeof(clk_name), "keysc%d", pdev->id);
priv->clk = clk_get(&pdev->dev, clk_name);
if (IS_ERR(priv->clk)) {
dev_err(&pdev->dev, "cannot get clock \"%s\"\n", clk_name);
error = PTR_ERR(priv->clk);
goto err2;
}
priv->input = input_allocate_device();
if (!priv->input) {
dev_err(&pdev->dev, "failed to allocate input device\n");
error = -ENOMEM;
goto err3;
}
input = priv->input;
input->evbit[0] = BIT_MASK(EV_KEY);
input->name = pdev->name;
input->phys = "sh-keysc-keys/input0";
input->dev.parent = &pdev->dev;
input->id.bustype = BUS_HOST;
input->id.vendor = 0x0001;
input->id.product = 0x0001;
input->id.version = 0x0100;
input->keycode = pdata->keycodes;
input->keycodesize = sizeof(pdata->keycodes[0]);
input->keycodemax = ARRAY_SIZE(pdata->keycodes);
error = request_irq(irq, sh_keysc_isr, 0, pdev->name, pdev);
if (error) {
dev_err(&pdev->dev, "failed to request IRQ\n");
goto err4;
}
for (i = 0; i < SH_KEYSC_MAXKEYS; i++)
__set_bit(pdata->keycodes[i], input->keybit);
__clear_bit(KEY_RESERVED, input->keybit);
error = input_register_device(input);
if (error) {
dev_err(&pdev->dev, "failed to register input device\n");
goto err5;
}
clk_enable(priv->clk);
iowrite16((sh_keysc_mode[pdata->mode].kymd << 8) |
pdata->scan_timing, priv->iomem_base + KYCR1_OFFS);
iowrite16(0, priv->iomem_base + KYOUTDR_OFFS);
iowrite16(KYCR2_IRQ_LEVEL, priv->iomem_base + KYCR2_OFFS);
device_init_wakeup(&pdev->dev, 1);
return 0;
err5:
free_irq(irq, pdev);
err4:
input_free_device(input);
err3:
clk_put(priv->clk);
err2:
iounmap(priv->iomem_base);
err1:
platform_set_drvdata(pdev, NULL);
kfree(priv);
err0:
return error;
}
/* Allocate memory for one device */
static int nozomi_card_init(struct pci_dev *pdev,
const struct pci_device_id *ent)
{
resource_size_t start;
int ret;
struct nozomi *dc = NULL;
int ndev_idx;
int i;
dev_dbg(&pdev->dev, "Init, new card found\n");
for (ndev_idx = 0; ndev_idx < ARRAY_SIZE(ndevs); ndev_idx++)
if (!ndevs[ndev_idx])
break;
if (ndev_idx >= ARRAY_SIZE(ndevs)) {
dev_err(&pdev->dev, "no free tty range for this card left\n");
ret = -EIO;
goto err;
}
dc = kzalloc(sizeof(struct nozomi), GFP_KERNEL);
if (unlikely(!dc)) {
dev_err(&pdev->dev, "Could not allocate memory\n");
ret = -ENOMEM;
goto err_free;
}
dc->pdev = pdev;
ret = pci_enable_device(dc->pdev);
if (ret) {
dev_err(&pdev->dev, "Failed to enable PCI Device\n");
goto err_free;
}
ret = pci_request_regions(dc->pdev, NOZOMI_NAME);
if (ret) {
dev_err(&pdev->dev, "I/O address 0x%04x already in use\n",
(int) /* nozomi_private.io_addr */ 0);
goto err_disable_device;
}
start = pci_resource_start(dc->pdev, 0);
if (start == 0) {
dev_err(&pdev->dev, "No I/O address for card detected\n");
ret = -ENODEV;
goto err_rel_regs;
}
/* Find out what card type it is */
nozomi_get_card_type(dc);
dc->base_addr = ioremap_nocache(start, dc->card_type);
if (!dc->base_addr) {
dev_err(&pdev->dev, "Unable to map card MMIO\n");
ret = -ENODEV;
goto err_rel_regs;
}
dc->send_buf = kmalloc(SEND_BUF_MAX, GFP_KERNEL);
if (!dc->send_buf) {
dev_err(&pdev->dev, "Could not allocate send buffer?\n");
ret = -ENOMEM;
goto err_free_sbuf;
}
for (i = PORT_MDM; i < MAX_PORT; i++) {
if (kfifo_alloc(&dc->port[i].fifo_ul, FIFO_BUFFER_SIZE_UL,
GFP_KERNEL)) {
dev_err(&pdev->dev,
"Could not allocate kfifo buffer\n");
ret = -ENOMEM;
goto err_free_kfifo;
}
}
spin_lock_init(&dc->spin_mutex);
nozomi_setup_private_data(dc);
/* Disable all interrupts */
dc->last_ier = 0;
writew(dc->last_ier, dc->reg_ier);
ret = request_irq(pdev->irq, &interrupt_handler, IRQF_SHARED,
NOZOMI_NAME, dc);
if (unlikely(ret)) {
dev_err(&pdev->dev, "can't request irq %d\n", pdev->irq);
goto err_free_kfifo;
}
DBG1("base_addr: %p", dc->base_addr);
make_sysfs_files(dc);
dc->index_start = ndev_idx * MAX_PORT;
ndevs[ndev_idx] = dc;
pci_set_drvdata(pdev, dc);
/* Enable RESET interrupt */
dc->last_ier = RESET;
iowrite16(dc->last_ier, dc->reg_ier);
dc->state = NOZOMI_STATE_ENABLED;
for (i = 0; i < MAX_PORT; i++) {
struct device *tty_dev;
struct port *port = &dc->port[i];
port->dc = dc;
tty_port_init(&port->port);
port->port.ops = &noz_tty_port_ops;
tty_dev = tty_port_register_device(&port->port, ntty_driver,
dc->index_start + i, &pdev->dev);
if (IS_ERR(tty_dev)) {
ret = PTR_ERR(tty_dev);
dev_err(&pdev->dev, "Could not allocate tty?\n");
tty_port_destroy(&port->port);
goto err_free_tty;
}
}
return 0;
err_free_tty:
for (i = 0; i < MAX_PORT; ++i) {
tty_unregister_device(ntty_driver, dc->index_start + i);
tty_port_destroy(&dc->port[i].port);
}
err_free_kfifo:
for (i = 0; i < MAX_PORT; i++)
kfifo_free(&dc->port[i].fifo_ul);
err_free_sbuf:
kfree(dc->send_buf);
iounmap(dc->base_addr);
err_rel_regs:
pci_release_regions(pdev);
err_disable_device:
pci_disable_device(pdev);
err_free:
kfree(dc);
err:
return ret;
}
static irqreturn_t sh_keysc_isr(int irq, void *dev_id)
{
struct platform_device *pdev = dev_id;
struct sh_keysc_priv *priv = platform_get_drvdata(pdev);
struct sh_keysc_info *pdata = &priv->pdata;
unsigned long keys, keys1, keys0, mask;
unsigned char keyin_set, tmp;
int i, k;
dev_dbg(&pdev->dev, "isr!\n");
keys1 = ~0;
keys0 = 0;
do {
keys = 0;
keyin_set = 0;
iowrite16(KYCR2_IRQ_DISABLED, priv->iomem_base + KYCR2_OFFS);
for (i = 0; i < sh_keysc_mode[pdata->mode].keyout; i++) {
iowrite16(0xfff ^ (3 << (i * 2)),
priv->iomem_base + KYOUTDR_OFFS);
udelay(pdata->delay);
tmp = ioread16(priv->iomem_base + KYINDR_OFFS);
keys |= tmp << (sh_keysc_mode[pdata->mode].keyin * i);
tmp ^= (1 << sh_keysc_mode[pdata->mode].keyin) - 1;
keyin_set |= tmp;
}
iowrite16(0, priv->iomem_base + KYOUTDR_OFFS);
iowrite16(KYCR2_IRQ_LEVEL | (keyin_set << 8),
priv->iomem_base + KYCR2_OFFS);
if (pdata->kycr2_delay)
udelay(pdata->kycr2_delay);
keys ^= ~0;
keys &= (1 << (sh_keysc_mode[pdata->mode].keyin *
sh_keysc_mode[pdata->mode].keyout)) - 1;
keys1 &= keys;
keys0 |= keys;
dev_dbg(&pdev->dev, "keys 0x%08lx\n", keys);
} while (ioread16(priv->iomem_base + KYCR2_OFFS) & 0x01);
dev_dbg(&pdev->dev, "last_keys 0x%08lx keys0 0x%08lx keys1 0x%08lx\n",
priv->last_keys, keys0, keys1);
for (i = 0; i < SH_KEYSC_MAXKEYS; i++) {
k = pdata->keycodes[i];
if (!k)
continue;
mask = 1 << i;
if (!((priv->last_keys ^ keys0) & mask))
continue;
if ((keys1 | keys0) & mask) {
input_event(priv->input, EV_KEY, k, 1);
priv->last_keys |= mask;
}
if (!(keys1 & mask)) {
input_event(priv->input, EV_KEY, k, 0);
priv->last_keys &= ~mask;
}
}
input_sync(priv->input);
return IRQ_HANDLED;
}
static inline void cmc221_idpram_send_msg(struct dpram_link_device *dpld,
u16 msg)
{
iowrite16(msg, dpld->sfr.msg2cp);
}
static void sh_cmt_write16(void __iomem *base, unsigned long offs,
unsigned long value)
{
iowrite16(value, base + (offs << 1));
}
void write_scoop_reg(struct device *dev, unsigned short reg, unsigned short data)
{
struct scoop_dev *sdev = dev_get_drvdata(dev);
iowrite16(data, sdev->base + reg);
}
static void igp_write_short(struct gm965temp_data *data, unsigned long offset,
u16 val)
{
iowrite16(val, data->igp_mmio + offset);
}
static inline void if_cs_write16(struct if_cs_card *card, uint reg, u16 val)
{
if (debug_output)
printk(KERN_INFO "outw %08x>%04x\n", reg, val);
iowrite16(val, card->iobase + reg);
}
static void sh_keysc_write(struct sh_keysc_priv *p, int reg_nr,
unsigned long value)
{
iowrite16(value, p->iomem_base + (reg_nr << 2));
}
/* Handle the 21143 uniquely: do autoselect with NWay, not the EEPROM list
of available transceivers. */
void t21142_media_task(struct work_struct *work)
{
struct tulip_private *tp =
container_of(work, struct tulip_private, media_work);
struct net_device *dev = tp->dev;
void __iomem *ioaddr = tp->base_addr;
int csr12 = ioread32(ioaddr + CSR12);
int next_tick = 60*HZ;
int new_csr6 = 0;
int csr14 = ioread32(ioaddr + CSR14);
/* CSR12[LS10,LS100] are not reliable during autonegotiation */
if ((csr14 & 0x80) && (csr12 & 0x7000) != 0x5000)
csr12 |= 6;
if (tulip_debug > 2)
dev_info(&dev->dev, "21143 negotiation status %08x, %s\n",
csr12, medianame[dev->if_port]);
if (tulip_media_cap[dev->if_port] & MediaIsMII) {
if (tulip_check_duplex(dev) < 0) {
netif_carrier_off(dev);
next_tick = 3*HZ;
} else {
netif_carrier_on(dev);
next_tick = 60*HZ;
}
} else if (tp->nwayset) {
/* Don't screw up a negotiated session! */
if (tulip_debug > 1)
dev_info(&dev->dev,
"Using NWay-set %s media, csr12 %08x\n",
medianame[dev->if_port], csr12);
} else if (tp->medialock) {
;
} else if (dev->if_port == 3) {
if (csr12 & 2) { /* No 100mbps link beat, revert to 10mbps. */
if (tulip_debug > 1)
dev_info(&dev->dev,
"No 21143 100baseTx link beat, %08x, trying NWay\n",
csr12);
t21142_start_nway(dev);
next_tick = 3*HZ;
}
} else if ((csr12 & 0x7000) != 0x5000) {
/* Negotiation failed. Search media types. */
if (tulip_debug > 1)
dev_info(&dev->dev,
"21143 negotiation failed, status %08x\n",
csr12);
if (!(csr12 & 4)) { /* 10mbps link beat good. */
new_csr6 = 0x82420000;
dev->if_port = 0;
iowrite32(0, ioaddr + CSR13);
iowrite32(0x0003FFFF, ioaddr + CSR14);
iowrite16(t21142_csr15[dev->if_port], ioaddr + CSR15);
iowrite32(t21142_csr13[dev->if_port], ioaddr + CSR13);
} else {
/* Select 100mbps port to check for link beat. */
new_csr6 = 0x83860000;
dev->if_port = 3;
iowrite32(0, ioaddr + CSR13);
iowrite32(0x0003FFFF, ioaddr + CSR14);
iowrite16(8, ioaddr + CSR15);
iowrite32(1, ioaddr + CSR13);
}
if (tulip_debug > 1)
dev_info(&dev->dev, "Testing new 21143 media %s\n",
medianame[dev->if_port]);
if (new_csr6 != (tp->csr6 & ~0x00D5)) {
tp->csr6 &= 0x00D5;
tp->csr6 |= new_csr6;
iowrite32(0x0301, ioaddr + CSR12);
tulip_restart_rxtx(tp);
}
next_tick = 3*HZ;
}
/* mod_timer synchronizes us with potential add_timer calls
* from interrupts.
*/
mod_timer(&tp->timer, RUN_AT(next_tick));
}
static inline void ks8842_select_bank(struct ks8842_adapter *adapter, u16 bank)
{
iowrite16(bank, adapter->hw_addr + REG_SELECT_BANK);
}
void usbhs_write(struct usbhs_priv *priv, u32 reg, u16 data)
{
iowrite16(data, priv->base + reg);
}
static inline void ks8842_write16(struct ks8842_adapter *adapter, u16 bank,
u16 value, int offset)
{
ks8842_select_bank(adapter, bank);
iowrite16(value, adapter->hw_addr + offset);
}
long ioctl_apci(struct file *filp, unsigned int cmd, unsigned long arg)
#endif
{
int count;
int status;
struct apci_my_info *ddata = filp->private_data;
info_struct info;
iopack io_pack;
unsigned long device_index, flags;
if( !ddata ) {
apci_error("no ddata.\n");
return 0;
}
apci_devel("apci_wait_for_irq_ioctl value is %u\n", (int)apci_wait_for_irq_ioctl );
apci_devel("apci_get_base_address value is %x\n", (int)apci_get_base_address );
apci_devel("inside ioctl.\n");
switch (cmd) {
struct apci_my_info *child;
case apci_get_devices_ioctl:
apci_debug("entering get_devices\n");
if (filp->private_data == NULL) return 0;
apci_debug("private_data was not null\n");
count = 0;
list_for_each_entry( child, &head.driver_list , driver_list )
count ++;
apci_debug("get_devices returning %d\n", count);
return count;
break;
case apci_get_device_info_ioctl:
apci_debug("entering get_device_info \n");
status = access_ok(VERIFY_WRITE, arg,
sizeof(info_struct));
if (status == 0) return -EACCES;
status = copy_from_user(&info, (info_struct *) arg, sizeof(info_struct));
info.dev_id = ddata->dev_id;
for (count = 0; count < 6; count++) {
info.base_addresses[count] =
ddata->regions[count].start;
}
status = copy_to_user((info_struct *) arg, &info, sizeof(info_struct));
break;
case apci_write_ioctl:
status = access_ok (VERIFY_WRITE, arg, sizeof(iopack));
if (status == 0) {
apci_error("access_ok failed\n");
return -EACCES; /* TODO: FIND appropriate return value */
}
status = copy_from_user(&io_pack, (iopack *) arg,
sizeof(iopack));
count = 0;
/* while (count < io_pack.device_index) { */
/* if (ddata != NULL) { */
/* ddata = ddata->next; */
/* } */
/* count++; */
/* } */
/* if (ddata == NULL) return -ENXIO; /\* invalid device index *\/ */
switch(is_valid_addr(ddata, io_pack.bar,io_pack.offset)) {
case IO:
apci_info("performing I/O write to %X\n",
ddata->regions[io_pack.bar].start + io_pack.offset);
switch (io_pack.size) {
case BYTE:
apci_devel("writing byte to %X\n", ddata->regions[io_pack.bar].start + io_pack.offset);
outb(io_pack.data, ddata->regions[io_pack.bar].start + io_pack.offset);
break;
case WORD:
apci_devel("writing word to %X\n", ddata->regions[io_pack.bar].start + io_pack.offset);
outw(io_pack.data, ddata->regions[io_pack.bar].start + io_pack.offset);
break;
case DWORD:
apci_devel("writing dword to %X\n", ddata->regions[io_pack.bar].start + io_pack.offset);
outl(io_pack.data, ddata->regions[io_pack.bar].start + io_pack.offset);
break;
};
break;
case MEM:
switch(io_pack.size) {
case BYTE:
iowrite8(io_pack.data, ddata->regions[io_pack.bar].mapped_address + io_pack.offset);
break;
case WORD:
iowrite16(io_pack.data, ddata->regions[io_pack.bar].mapped_address + io_pack.offset);
break;
case DWORD:
iowrite32(io_pack.data, ddata->regions[io_pack.bar].mapped_address + io_pack.offset);
break;
};
break;
case INVALID:
return -EFAULT;
break;
};
break;
case apci_read_ioctl:
status = access_ok(VERIFY_WRITE, arg, sizeof(iopack));
if (status == 0) return -EACCES; /* TODO: Find a better return code */
status = copy_from_user(&io_pack, (iopack *) arg, sizeof(iopack));
count = 0;
if (ddata == NULL) return -ENXIO; /* invalid device index */
switch (is_valid_addr(ddata, io_pack.bar, io_pack.offset)) {
case IO:
switch (io_pack.size) {
case BYTE:
io_pack.data = inb(ddata->regions[io_pack.bar].start + io_pack.offset);
break;
case WORD:
io_pack.data = inw(ddata->regions[io_pack.bar].start + io_pack.offset);
break;
case DWORD:
io_pack.data = inl(ddata->regions[io_pack.bar].start + io_pack.offset);
break;
};
break;
case MEM:
switch (io_pack.size) {
case BYTE:
io_pack.data = ioread8(ddata->regions[io_pack.bar].mapped_address + io_pack.offset);
break;
case WORD:
io_pack.data = ioread16(ddata->regions[io_pack.bar].mapped_address + io_pack.offset);
break;
case DWORD:
io_pack.data = ioread32(ddata->regions[io_pack.bar].mapped_address + io_pack.offset);
break;
};
break;
case INVALID:
return -EFAULT;
break;
};
apci_info("performed read from %X\n",
ddata->regions[io_pack.bar].start + io_pack.offset);
status = copy_to_user((iopack *)arg, &io_pack,
sizeof(iopack));
break;
case apci_wait_for_irq_ioctl:
apci_info("enter wait_for_IRQ.\n");
device_index = arg;
apci_info("Acquiring spin lock\n");
spin_lock_irqsave(&(ddata->irq_lock), flags);
if (ddata->waiting_for_irq == 1) {
/* if we are already waiting for an IRQ on
* this device.
*/
spin_unlock_irqrestore (&(ddata->irq_lock), flags);
return -EALREADY; /* TODO: find a better return code */
} else {
ddata->waiting_for_irq = 1;
ddata->irq_cancelled = 0;
}
spin_unlock_irqrestore (&(ddata->irq_lock),
flags);
apci_info("Released spin lock\n");
wait_event_interruptible(ddata->wait_queue, ddata->waiting_for_irq == 0);
if (ddata->irq_cancelled == 1) return -ECANCELED;
break;
case apci_cancel_wait_ioctl:
apci_info("Cancel wait_for_irq.\n");
device_index = arg;
spin_lock_irqsave(&(ddata->irq_lock), flags);
if (ddata->waiting_for_irq == 0) {
spin_unlock_irqrestore(&(ddata->irq_lock), flags);
return -EALREADY;
}
ddata->irq_cancelled = 1;
ddata->waiting_for_irq = 0;
spin_unlock_irqrestore(&(ddata->irq_lock), flags);
wake_up_interruptible(&(ddata->wait_queue));
break;
case apci_get_base_address:
apci_debug("Getting base address");
/* status = copy_from_user(&info, (info_struct *) arg, sizeof(info_struct)); */
info.dev_id = ddata->dev_id;
status = copy_to_user((info_struct *) arg, &ddata->plx_region.start, sizeof( io_region ));
break;
};
return 0;
}
static ssize_t module_write(struct file *filp, const char __user *buf, size_t count,loff_t *f_pos){
ssize_t retval = 1;
int * ptr;
unsigned int checkData;
checkData = __copy_from_user(&fromUser,buf,READ_BIT_FROM_USER);
if(checkData){
printk(KERN_ALERT "Cant copy from user !!! \n");
return -EFAULT;
}
printk(KERN_ALERT "Value From User Is : fromUser %d",(int)fromUser);
//Disables the timer completely before any configuration changes.
ptr = ioremap_nocache(TCLR,TOUCH_LONG);
iowrite32(0x0,ptr);
iounmap(ptr);
//Change the PAD multiplexing to allow PWM10 off this pin instead of its current configuration as GPIO_145.
ptr = ioremap_nocache(CONTROL_PADCONF_UART2_CTS,TOUCH_SHORT);
iowrite16(0x0002,ptr);
iounmap(ptr);
//Set the frequency of the PWM signal to 1024 Hz.
ptr = ioremap_nocache(TLDR,TOUCH_LONG);
iowrite32(0xFFFFFFE0,ptr);
iounmap(ptr);
switch((int)fromUser){
case BRIGHTNESS_LEVEL_1:
printk(KERN_ALERT "Change to LEVEL 1\n");
//This sets the duty cycle of the PWM signal to 0%, ON time one half of cycle time.
ptr = ioremap_nocache(TMAR,TOUCH_LONG);
iowrite32(0xFFFFFFFF,ptr);
iounmap(ptr);
break;
case BRIGHTNESS_LEVEL_2:
printk(KERN_ALERT "Change to LEVEL 2\n");
//This sets the duty cycle of the PWM signal to 25%, ON time one half of cycle time.
ptr = ioremap_nocache(TMAR,TOUCH_LONG);
//iowrite32(0xFFFFFFFE,ptr);
iowrite32(0xFFFFFFFE,ptr);
iounmap(ptr);
break;
case BRIGHTNESS_LEVEL_3:
printk(KERN_ALERT "Change to LEVEL 3\n");
//This sets the duty cycle of the PWM signal to 50%, ON time one half of cycle time.
ptr = ioremap_nocache(TMAR,TOUCH_LONG);
iowrite32(0xFFFFFFEF,ptr);
iounmap(ptr);
break;
case BRIGHTNESS_LEVEL_4:
printk(KERN_ALERT "Change to LEVEL 3\n");
//This sets the duty cycle of the PWM signal to 75%, ON time one half of cycle time.
ptr = ioremap_nocache(TMAR,TOUCH_LONG);
iowrite32(0xFFFFFEFF,ptr);
iounmap(ptr);
break;
case BRIGHTNESS_LEVEL_5:
printk(KERN_ALERT "Change to LEVEL 5\n");
//This sets the duty cycle of the PWM signal to 100%, ON time one half of cycle time.
ptr = ioremap_nocache(TMAR,TOUCH_LONG);
iowrite32(0x0,ptr);
iounmap(ptr);
break;
default:
printk(KERN_ALERT "Input from user -ERROR\n");
break;
}
//This primes the timer counter for the first cycle. Primed with the same value as the frequency.
ptr = ioremap_nocache(TCRR,TOUCH_LONG);
iowrite32(0xFFFFFFE0,ptr);
iounmap(ptr);
//This starts the timer in PWM mode.
ptr = ioremap_nocache(TCLR,TOUCH_LONG);
iowrite32(0x01843,ptr);
iounmap(ptr);
return retval;
}
