void __init tcc8k_init_irq(void)
{
int irqno;
/* Mask and clear all interrupts */
PIC0_IEN = 0x00000000;
PIC0_CREQ = 0xffffffff;
PIC1_IEN = 0x00000000;
PIC1_CREQ = 0xffffffff;
PIC0_MEN0 = 0x00000003;
PIC1_MEN1 = 0x00000003;
PIC1_MEN = 0x00000003;
/* let all IRQs be level triggered */
PIC0_TMODE = 0xffffffff;
PIC1_TMODE = 0xffffffff;
/* all IRQs are IRQs (not FIQs) */
PIC0_IRQSEL = 0xffffffff;
PIC1_IRQSEL = 0xffffffff;
for (irqno = 0; irqno < NR_IRQS; irqno++) {
if (irqno < 32)
irq_set_chip(irqno, &tcc8000_irq_chip0);
else
irq_set_chip(irqno, &tcc8000_irq_chip1);
irq_set_handler(irqno, handle_level_irq);
set_irq_flags(irqno, IRQF_VALID);
}
}
void __init init_IRQ(void)
{
unsigned int irq;
request_resource(&iomem_resource, &irq_resource);
/* disable all IRQs */
writel(0, INTC_ICMR);
/* all IRQs are IRQ, not REAL */
writel(0, INTC_ICLR);
/* clear all GPIO edge detects */
writel(FMASK(8, 0) & ~FIELD(1, 1, GPI_SOFF_REQ), GPIO_GPIR);
writel(0, GPIO_GFER);
writel(0, GPIO_GRER);
writel(0x0FFFFFFF, GPIO_GEDR);
writel(1, INTC_ICCR);
for (irq = 0; irq < IRQ_GPIOHIGH; irq++) {
irq_set_chip(irq, &puv3_low_gpio_chip);
irq_set_handler(irq, handle_edge_irq);
irq_modify_status(irq,
IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN,
0);
}
for (irq = IRQ_GPIOHIGH + 1; irq < IRQ_GPIO0; irq++) {
irq_set_chip(irq, &puv3_normal_chip);
irq_set_handler(irq, handle_level_irq);
irq_modify_status(irq,
IRQ_NOREQUEST | IRQ_NOAUTOEN,
IRQ_NOPROBE);
}
for (irq = IRQ_GPIO0; irq <= IRQ_GPIO27; irq++) {
irq_set_chip(irq, &puv3_high_gpio_chip);
irq_set_handler(irq, handle_edge_irq);
irq_modify_status(irq,
IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN,
0);
}
/*
* Install handler for GPIO 0-27 edge detect interrupts
*/
irq_set_chip(IRQ_GPIOHIGH, &puv3_normal_chip);
irq_set_chained_handler(IRQ_GPIOHIGH, puv3_gpio_handler);
#ifdef CONFIG_PUV3_GPIO
puv3_init_gpio();
#endif
}
static void __init gic_basic_init(int numintrs, int numvpes,
struct gic_intr_map *intrmap, int mapsize)
{
unsigned int i, cpu;
/* Setup defaults */
for (i = 0; i < numintrs; i++) {
GIC_SET_POLARITY(i, GIC_POL_POS);
GIC_SET_TRIGGER(i, GIC_TRIG_LEVEL);
GIC_CLR_INTR_MASK(i);
if (i < GIC_NUM_INTRS)
gic_irq_flags[i] = 0;
}
/* Setup specifics */
for (i = 0; i < mapsize; i++) {
cpu = intrmap[i].cpunum;
if (cpu == GIC_UNUSED)
continue;
if (cpu == 0 && i != 0 && intrmap[i].flags == 0)
continue;
gic_setup_intr(i,
intrmap[i].cpunum,
intrmap[i].pin,
intrmap[i].polarity,
intrmap[i].trigtype,
intrmap[i].flags);
}
vpe_local_setup(numvpes);
for (i = _irqbase; i < (_irqbase + numintrs); i++)
irq_set_chip(i, &gic_irq_controller);
}
/*
* This function should be called during kernel startup to initialize
* the machine vector table.
*/
void __init init_IRQ(void)
{
int i;
/* set up the vectors */
for (i = 72; i < 256; ++i)
_ramvec[i] = (e_vector) bad_interrupt;
_ramvec[32] = system_call;
_ramvec[65] = (e_vector) inthandler1;
_ramvec[66] = (e_vector) inthandler2;
_ramvec[67] = (e_vector) inthandler3;
_ramvec[68] = (e_vector) inthandler4;
_ramvec[69] = (e_vector) inthandler5;
_ramvec[70] = (e_vector) inthandler6;
_ramvec[71] = (e_vector) inthandler7;
IVR = 0x40; /* Set DragonBall IVR (interrupt base) to 64 */
/* turn off all interrupts */
IMR = ~0;
for (i = 0; (i < NR_IRQS); i++) {
irq_set_chip(i, &intc_irq_chip);
irq_set_handler(i, handle_level_irq);
}
}
static int s3c2412_irq_add(struct device *dev, struct subsys_interface *sif)
{
unsigned int irqno;
for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
irq_set_chip_and_handler(irqno, &s3c2412_irq_eint0t4,
handle_edge_irq);
set_irq_flags(irqno, IRQF_VALID);
}
irq_set_chained_handler(IRQ_S3C2412_CFSDI, s3c2412_irq_demux_cfsdi);
for (irqno = IRQ_S3C2412_SDI; irqno <= IRQ_S3C2412_CF; irqno++) {
irq_set_chip_and_handler(irqno, &s3c2412_irq_cfsdi,
handle_level_irq);
set_irq_flags(irqno, IRQF_VALID);
}
s3c2412_irq_rtc_chip = s3c_irq_chip;
s3c2412_irq_rtc_chip.irq_set_wake = s3c2412_irq_rtc_wake;
irq_set_chip(IRQ_RTC, &s3c2412_irq_rtc_chip);
return 0;
}
/**
* irq_sim_init - Initialize the interrupt simulator: allocate a range of
* dummy interrupts.
*
* @sim: The interrupt simulator object to initialize.
* @num_irqs: Number of interrupts to allocate
*
* Returns 0 on success and a negative error number on failure.
*/
int irq_sim_init(struct irq_sim *sim, unsigned int num_irqs)
{
int i;
sim->irqs = kmalloc_array(num_irqs, sizeof(*sim->irqs), GFP_KERNEL);
if (!sim->irqs)
return -ENOMEM;
sim->irq_base = irq_alloc_descs(-1, 0, num_irqs, 0);
if (sim->irq_base < 0) {
kfree(sim->irqs);
return sim->irq_base;
}
for (i = 0; i < num_irqs; i++) {
sim->irqs[i].irqnum = sim->irq_base + i;
sim->irqs[i].enabled = false;
irq_set_chip(sim->irq_base + i, &irq_sim_irqchip);
irq_set_chip_data(sim->irq_base + i, &sim->irqs[i]);
irq_set_handler(sim->irq_base + i, &handle_simple_irq);
irq_modify_status(sim->irq_base + i,
IRQ_NOREQUEST | IRQ_NOAUTOEN, IRQ_NOPROBE);
}
init_irq_work(&sim->work_ctx.work, irq_sim_handle_irq);
sim->irq_count = num_irqs;
return 0;
}
void __init gemini_init_irq(void)
{
unsigned int i, mode = 0, level = 0;
/*
* Disable the idle handler by default since it is buggy
* For more info see arch/arm/mach-gemini/idle.c
*/
disable_hlt();
request_resource(&iomem_resource, &irq_resource);
for (i = 0; i < NR_IRQS; i++) {
irq_set_chip(i, &gemini_irq_chip);
if((i >= IRQ_TIMER1 && i <= IRQ_TIMER3) || (i >= IRQ_SERIRQ0 && i <= IRQ_SERIRQ1)) {
irq_set_handler(i, handle_edge_irq);
mode |= 1 << i;
level |= 1 << i;
} else {
irq_set_handler(i, handle_level_irq);
}
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
}
/* Disable all interrupts */
__raw_writel(0, IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE)));
__raw_writel(0, FIQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE)));
/* Set interrupt mode */
__raw_writel(mode, IRQ_TMODE(IO_ADDRESS(GEMINI_INTERRUPT_BASE)));
__raw_writel(level, IRQ_TLEVEL(IO_ADDRESS(GEMINI_INTERRUPT_BASE)));
}
/* ARM Interrupt Controller Initialization */
void __init m2_init_irq(void)
{
unsigned int irq;
/* Disable all interrupt requests */
WRITE_CBUS_REG(A9_0_IRQ_IN0_INTR_MASK, 0);
WRITE_CBUS_REG(A9_0_IRQ_IN1_INTR_MASK, 0);
WRITE_CBUS_REG(A9_0_IRQ_IN2_INTR_MASK, 0);
WRITE_CBUS_REG(A9_0_IRQ_IN3_INTR_MASK, 0);
/* Clear all interrupts */
WRITE_CBUS_REG(A9_0_IRQ_IN0_INTR_STAT_CLR, ~0);
WRITE_CBUS_REG(A9_0_IRQ_IN1_INTR_STAT_CLR, ~0);
WRITE_CBUS_REG(A9_0_IRQ_IN2_INTR_STAT_CLR, ~0);
WRITE_CBUS_REG(A9_0_IRQ_IN3_INTR_STAT_CLR, ~0);
/* Set all interrupts to IRQ */
WRITE_CBUS_REG(A9_0_IRQ_IN0_INTR_FIRQ_SEL, 0);
WRITE_CBUS_REG(A9_0_IRQ_IN1_INTR_FIRQ_SEL, 0);
WRITE_CBUS_REG(A9_0_IRQ_IN2_INTR_FIRQ_SEL, 0);
WRITE_CBUS_REG(A9_0_IRQ_IN3_INTR_FIRQ_SEL, 0);
/* set up genirq dispatch */
for (irq = 0; irq < NR_IRQS; irq++) {
irq_set_chip(irq, &m2_irq_chip);
irq_set_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
}
}
static int s3c2412_irq_add(struct sys_device *sysdev)
{
unsigned int irqno;
for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
irq_set_chip_and_handler(irqno, &s3c2412_irq_eint0t4,
handle_edge_irq);
set_irq_flags(irqno, IRQF_VALID);
}
/* add demux support for CF/SDI */
irq_set_chained_handler(IRQ_S3C2412_CFSDI, s3c2412_irq_demux_cfsdi);
for (irqno = IRQ_S3C2412_SDI; irqno <= IRQ_S3C2412_CF; irqno++) {
irq_set_chip_and_handler(irqno, &s3c2412_irq_cfsdi,
handle_level_irq);
set_irq_flags(irqno, IRQF_VALID);
}
/* change RTC IRQ's set wake method */
s3c2412_irq_rtc_chip = s3c_irq_chip;
s3c2412_irq_rtc_chip.irq_set_wake = s3c2412_irq_rtc_wake;
irq_set_chip(IRQ_RTC, &s3c2412_irq_rtc_chip);
return 0;
}
static void __init visws_pre_intr_init(void)
{
int i;
set_piix4_virtual_irq_type();
for (i = 0; i < CO_IRQ_APIC0 + CO_APIC_LAST + 1; i++) {
struct irq_chip *chip = NULL;
if (i == 0)
chip = &cobalt_irq_type;
else if (i == CO_IRQ_IDE0)
chip = &cobalt_irq_type;
else if (i == CO_IRQ_IDE1)
>chip = &cobalt_irq_type;
else if (i == CO_IRQ_8259)
chip = &piix4_master_irq_type;
else if (i < CO_IRQ_APIC0)
chip = &piix4_virtual_irq_type;
else if (IS_CO_APIC(i))
chip = &cobalt_irq_type;
if (chip)
irq_set_chip(i, chip);
}
void
irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
irq_flow_handler_t handle, const char *name)
{
irq_set_chip(irq, chip);
__irq_set_handler(irq, handle, 0, name);
}
static struct mcuio_soft_hc *__setup_shc(const struct mcuio_soft_hc_ops *ops,
void *priv)
{
struct mcuio_soft_hc *shc = kzalloc(sizeof(*shc), GFP_KERNEL);
if (!shc)
return ERR_PTR(-ENOMEM);
init_kthread_worker(&shc->irq_kworker);
shc->irq_kworker_task = kthread_run(kthread_worker_fn,
&shc->irq_kworker,
"shc_irq");
if (IS_ERR(shc->irq_kworker_task)) {
pr_err("failed to create irq tsk for shc\n");
return ERR_PTR(PTR_ERR(shc->irq_kworker_task));
}
init_kthread_work(&shc->do_irq, __do_irq);
shc->ops = ops;
shc->priv = priv;
shc->rx_circ_buf.head = shc->rx_circ_buf.tail = 0;
shc->rx_circ_buf.buf = shc->rx_buf;
shc->chip.name = "MCUIO-SHC";
shc->chip.irq_mask = mcuio_soft_hc_irq_mask;
shc->chip.irq_unmask = mcuio_soft_hc_irq_unmask;
shc->irqno = irq_alloc_desc(0);
irq_set_chip(shc->irqno, &shc->chip);
irq_set_handler(shc->irqno, &handle_simple_irq);
irq_modify_status(shc->irqno,
IRQ_NOREQUEST | IRQ_NOAUTOEN,
IRQ_NOPROBE);
return shc;
}
void __init pnx4008_init_irq(void)
{
unsigned int i;
/* configure IRQ's */
for (i = 0; i < NR_IRQS; i++) {
set_irq_flags(i, IRQF_VALID);
irq_set_chip(i, &pnx4008_irq_chip);
pnx4008_set_irq_type(irq_get_irq_data(i), pnx4008_irq_type[i]);
}
/* configure and enable IRQ 0,1,30,31 (cascade interrupts) */
pnx4008_set_irq_type(irq_get_irq_data(SUB1_IRQ_N),
pnx4008_irq_type[SUB1_IRQ_N]);
pnx4008_set_irq_type(irq_get_irq_data(SUB2_IRQ_N),
pnx4008_irq_type[SUB2_IRQ_N]);
pnx4008_set_irq_type(irq_get_irq_data(SUB1_FIQ_N),
pnx4008_irq_type[SUB1_FIQ_N]);
pnx4008_set_irq_type(irq_get_irq_data(SUB2_FIQ_N),
pnx4008_irq_type[SUB2_FIQ_N]);
/* mask all others */
__raw_writel((1 << SUB2_FIQ_N) | (1 << SUB1_FIQ_N) |
(1 << SUB2_IRQ_N) | (1 << SUB1_IRQ_N),
INTC_ER(MAIN_BASE_INT));
__raw_writel(0, INTC_ER(SIC1_BASE_INT));
__raw_writel(0, INTC_ER(SIC2_BASE_INT));
}
static int pod_gpio_remove(struct platform_device *pdev)
{
struct resource *resource_memory, *resource_irq;
struct pod_gpio_chip *cg_chip = dev_get_drvdata(&pdev->dev);
unsigned int irq;
/* Remove the GPIO chip */
if (gpiochip_remove(&cg_chip->chip))
dev_err(&pdev->dev, "gpio_chip remove failed\n");
if (cg_chip->reg_base)
iounmap(cg_chip->reg_base);
kfree(cg_chip);
resource_memory = platform_get_resource(pdev, IORESOURCE_MEM, 0);
resource_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
release_mem_region(resource_memory->start,
resource_size(resource_memory));
for (irq = IRQ_GPIO_POD(0) ; irq < IRQ_GPIO_POD(16) ; irq++) {
irq_set_chip(irq, NULL);
irq_set_handler(irq, NULL);
set_irq_flags(irq, 0);
}
free_irq(resource_irq->start, cg_chip);
dev_set_drvdata(&pdev->dev, NULL);
return 0;
}
static int cs75xx_gpio_remove(struct platform_device *pdev)
{
int i, j;
gpio_dbgmsg("Function: %s\n", __func__);
/* disable irq and deregister to gpiolib */
for (i = 0; i < GPIO_BANK_NUM; i++) {
/* disable, unmask and clear all interrupts */
__raw_writel(0x0, cs75xx_gpio_base[i] + CS75XX_GPIO_IE);
__raw_writel(~0x0, cs75xx_gpio_base[i] + CS75XX_GPIO_INT);
for (j = GPIO_IRQ_BASE + i * GPIO_BANK_SIZE;
j < GPIO_IRQ_BASE + (i + 1) * GPIO_BANK_SIZE; j++) {
irq_set_chip(j, NULL);
irq_set_handler(j, NULL);
set_irq_flags(j, 0);
}
irq_set_chained_handler(cs75xx_irq_gpio[i], NULL);
irq_set_handler_data(cs75xx_irq_gpio[i], NULL);
}
BUG_ON(gpiochip_remove(&cs75xx_gpio_chip));
for (i = 0; i < GPIO_BANK_NUM; i++)
__raw_writel(0x0, cs75xx_global_base + CS75XX_GPIO_MUX_0 + i*4); // disable valid gpio pin
return 0;
}
void __init gemini_init_irq(void)
{
unsigned int i, mode = 0, level = 0;
/*
*/
disable_hlt();
request_resource(&iomem_resource, &irq_resource);
for (i = 0; i < NR_IRQS; i++) {
irq_set_chip(i, &gemini_irq_chip);
if((i >= IRQ_TIMER1 && i <= IRQ_TIMER3) || (i >= IRQ_SERIRQ0 && i <= IRQ_SERIRQ1)) {
irq_set_handler(i, handle_edge_irq);
mode |= 1 << i;
level |= 1 << i;
} else {
irq_set_handler(i, handle_level_irq);
}
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
}
/* */
__raw_writel(0, IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE)));
__raw_writel(0, FIQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE)));
/* */
__raw_writel(mode, IRQ_TMODE(IO_ADDRESS(GEMINI_INTERRUPT_BASE)));
__raw_writel(level, IRQ_TLEVEL(IO_ADDRESS(GEMINI_INTERRUPT_BASE)));
}
void __init gic_platform_init(int irqs, struct irq_chip *irq_controller)
{
int i;
for (i = gic_irq_base; i < (gic_irq_base + irqs); i++){
irq_set_chip(i, irq_controller);
}
}
void __init mv88de3100_init_irq(void)
{
int i;
gic_init(0, 29, __io(MEMMAP_GIC_DIST_BASE), __io(MEMMAP_GIC_CPU_BASE));
// gic_dist_init(0, __io(MEMMAP_GIC_DIST_BASE), 29);
// gic_cpu_init(0, __io(MEMMAP_GIC_CPU_BASE));
for (i = GALOIS_APB_IRQ_START; i < GALOIS_SM_IRQ_START; i++)
irq_set_chip(i, &apb_irq_chip);
for (i = GALOIS_SM_IRQ_START; i < NR_IRQS; i++)
irq_set_chip(i, &sm_irq_chip);
irq_set_chained_handler(IRQ_ICTLINST0CPUIRQ, apb_irq_demux);
irq_set_chained_handler(IRQ_SM2SOCHWINT0, sm_irq_demux);
}
/*
* All of the FPGA interrupt request inputs except for the touchscreen are
* edge-sensitive; the touchscreen is level-sensitive. The edge-sensitive
* interrupts are acknowledged as a side-effect of reading the interrupt
* status register from the FPGA. The edge-sensitive interrupt inputs
* cause a problem with level interrupt requests, such as Ethernet. The
* problem occurs when a level interrupt request is asserted while its
* interrupt input is masked in the FPGA, which results in a missed
* interrupt.
*
* In an attempt to workaround the problem with missed interrupts, the
* mask_ack routine for all of the FPGA interrupts has been changed from
* fpga_mask_ack_irq() to fpga_ack_irq() so that the specific FPGA interrupt
* being serviced is left unmasked. We can do this because the FPGA cascade
* interrupt is installed with the IRQF_DISABLED flag, which leaves all
* interrupts masked at the CPU while an FPGA interrupt handler executes.
*
* Limited testing indicates that this workaround appears to be effective
* for the smc9194 Ethernet driver used on the Innovator. It should work
* on other FPGA interrupts as well, but any drivers that explicitly mask
* interrupts at the interrupt controller via disable_irq/enable_irq
* could pose a problem.
*/
void omap1510_fpga_init_irq(void)
{
int i, res;
__raw_writeb(0, OMAP1510_FPGA_IMR_LO);
__raw_writeb(0, OMAP1510_FPGA_IMR_HI);
__raw_writeb(0, INNOVATOR_FPGA_IMR2);
for (i = OMAP_FPGA_IRQ_BASE; i < OMAP_FPGA_IRQ_END; i++) {
if (i == OMAP1510_INT_FPGA_TS) {
/*
* The touchscreen interrupt is level-sensitive, so
* we'll use the regular mask_ack routine for it.
*/
irq_set_chip(i, &omap_fpga_irq_ack);
}
else {
/*
* All FPGA interrupts except the touchscreen are
* edge-sensitive, so we won't mask them.
*/
irq_set_chip(i, &omap_fpga_irq);
}
irq_set_handler(i, handle_edge_irq);
set_irq_flags(i, IRQF_VALID);
}
/*
* The FPGA interrupt line is connected to GPIO13. Claim this pin for
* the ARM.
*
* NOTE: For general GPIO/MPUIO access and interrupts, please see
* gpio.[ch]
*/
res = gpio_request(13, "FPGA irq");
if (res) {
pr_err("%s failed to get gpio\n", __func__);
return;
}
gpio_direction_input(13);
irq_set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING);
irq_set_chained_handler(OMAP1510_INT_FPGA, innovator_fpga_IRQ_demux);
}
void init_IRQ(void)
{
int i;
for (i = 0; (i < NR_IRQS); i++) {
irq_set_chip(i, &intc_irq_chip);
irq_set_handler(i, handle_level_irq);
}
}
void __init init_IRQ(void)
{
int irq, eirq;
/* Mask all interrupt sources */
__raw_writeb(0xff, MCFINTC0_SIMR);
if (MCFINTC1_SIMR)
__raw_writeb(0xff, MCFINTC1_SIMR);
eirq = MCFINT_VECBASE + 64 + (MCFINTC1_ICR0 ? 64 : 0);
for (irq = MCFINT_VECBASE; (irq < eirq); irq++) {
if ((irq >= EINT1) && (irq <= EINT7))
irq_set_chip(irq, &intc_irq_chip_edge_port);
else
irq_set_chip(irq, &intc_irq_chip);
irq_set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
irq_set_handler(irq, handle_level_irq);
}
}
static int cp_intc_host_map(struct irq_domain *h, unsigned int virq,
irq_hw_number_t hw)
{
pr_debug("cp_intc_host_map(%d, 0x%lx)\n", virq, hw);
irq_set_chip(virq, &cp_intc_irq_chip);
set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
irq_set_handler(virq, handle_edge_irq);
return 0;
}
void __init init_IRQ(void)
{
int irq;
__raw_writel(0x1, MCFICM_INTC0 + MCFINTC_IMRL);
#ifdef MCFICM_INTC1
__raw_writel(0x1, MCFICM_INTC1 + MCFINTC_IMRL);
#endif
for (irq = MCFINT_VECBASE; (irq < MCFINT_VECBASE + NR_VECS); irq++) {
if ((irq >= EINT1) && (irq <=EINT7))
irq_set_chip(irq, &intc_irq_chip_edge_port);
else
irq_set_chip(irq, &intc_irq_chip);
irq_set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
irq_set_handler(irq, handle_level_irq);
}
}
void __init msp_per_irq_init(void)
{
int i;
/* Mask/clear interrupts. */
*PER_INT_MSK_REG = 0x00000000;
*PER_INT_STS_REG = 0xFFFFFFFF;
/* initialize all the IRQ descriptors */
for (i = MSP_PER_INTBASE; i < MSP_PER_INTBASE + 32; i++) {
irq_set_chip(i, &msp_per_irq_controller);
}
}
static int pci_irq_host_map(struct irq_domain *h, unsigned int virq,
irq_hw_number_t hw)
{ unsigned int irq;
DBG("%s(%d, 0x%lx)\n", __func__, virq, hw);
if ((virq >= 1) && (virq <= 4)){
irq = virq + IRQ_PCI_INTAD_BASE - 1;
irq_set_status_flags(irq, IRQ_LEVEL);
irq_set_chip(irq, &tsi108_pci_irq);
}
return 0;
}
/**
* m68k_setup_user_interrupt
* @vec: first user vector interrupt to handle
* @cnt: number of active user vector interrupts
*
* setup user vector interrupts, this includes activating the specified range
* of interrupts, only then these interrupts can be requested (note: this is
* different from auto vector interrupts).
*/
void __init m68k_setup_user_interrupt(unsigned int vec, unsigned int cnt)
{
int i;
BUG_ON(IRQ_USER + cnt > NR_IRQS);
m68k_first_user_vec = vec;
for (i = 0; i < cnt; i++)
irq_set_chip(IRQ_USER + i, &user_irq_chip);
*user_irqvec_fixup = vec - IRQ_USER;
flush_icache();
}
static int regmap_irq_map(struct irq_domain *h, unsigned int virq,
irq_hw_number_t hw)
{
struct regmap_irq_chip_data *data = h->host_data;
irq_set_chip_data(virq, data);
irq_set_chip(virq, &data->irq_chip);
irq_set_nested_thread(virq, 1);
irq_set_noprobe(virq);
return 0;
}
static int __init mcf_intc2_init(void)
{
int irq;
/* GPIO interrupt sources */
for (irq = MCFINTC2_GPIOIRQ0; (irq <= MCFINTC2_GPIOIRQ7); irq++) {
irq_set_chip(irq, &intc2_irq_gpio_chip);
irq_set_handler(irq, handle_edge_irq);
}
return 0;
}
void __init init_IRQ(void)
{
int irq;
mcf_maskimr(0xffffffff);
for (irq = 0; (irq < NR_IRQS); irq++) {
irq_set_chip(irq, &intc_irq_chip);
irq_set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
irq_set_handler(irq, handle_level_irq);
}
}
/**
* m68k_setup_irq_controller
* @chip: irq chip which controls specified irq
* @handle: flow handler which handles specified irq
* @irq: first irq to be managed by the controller
* @cnt: number of irqs to be managed by the controller
*
* Change the controller for the specified range of irq, which will be used to
* manage these irq. auto/user irq already have a default controller, which can
* be changed as well, but the controller probably should use m68k_irq_startup/
* m68k_irq_shutdown.
*/
void m68k_setup_irq_controller(struct irq_chip *chip,
irq_flow_handler_t handle, unsigned int irq,
unsigned int cnt)
{
int i;
for (i = 0; i < cnt; i++) {
irq_set_chip(irq + i, chip);
if (handle)
irq_set_handler(irq + i, handle);
}
}
