static uint32_t feature_flags() {
        uint32_t result = 0;
        if (_cpuid_info.std_cpuid1_edx.bits.cmpxchg8 != 0)
            result |= CPU_CX8;
        if (_cpuid_info.std_cpuid1_edx.bits.cmov != 0)
            result |= CPU_CMOV;
        if (_cpuid_info.std_cpuid1_edx.bits.fxsr != 0 || (is_amd() &&
                _cpuid_info.ext_cpuid1_edx.bits.fxsr != 0))
            result |= CPU_FXSR;
        // HT flag is set for multi-core processors also.
        if (threads_per_core() > 1)
            result |= CPU_HT;
        if (_cpuid_info.std_cpuid1_edx.bits.mmx != 0 || (is_amd() &&
                _cpuid_info.ext_cpuid1_edx.bits.mmx != 0))
            result |= CPU_MMX;
        if (_cpuid_info.std_cpuid1_edx.bits.sse != 0)
            result |= CPU_SSE;
        if (_cpuid_info.std_cpuid1_edx.bits.sse2 != 0)
            result |= CPU_SSE2;
        if (_cpuid_info.std_cpuid1_ecx.bits.sse3 != 0)
            result |= CPU_SSE3;
        if (_cpuid_info.std_cpuid1_ecx.bits.ssse3 != 0)
            result |= CPU_SSSE3;
        if (_cpuid_info.std_cpuid1_ecx.bits.sse4_1 != 0)
            result |= CPU_SSE4_1;
        if (_cpuid_info.std_cpuid1_ecx.bits.sse4_2 != 0)
            result |= CPU_SSE4_2;
        if (_cpuid_info.std_cpuid1_ecx.bits.popcnt != 0)
            result |= CPU_POPCNT;
        if (_cpuid_info.std_cpuid1_ecx.bits.avx != 0 &&
                _cpuid_info.std_cpuid1_ecx.bits.osxsave != 0 &&
                _cpuid_info.xem_xcr0_eax.bits.sse != 0 &&
                _cpuid_info.xem_xcr0_eax.bits.ymm != 0) {
            result |= CPU_AVX;
            if (_cpuid_info.sef_cpuid7_ebx.bits.avx2 != 0)
                result |= CPU_AVX2;
        }
        if (_cpuid_info.std_cpuid1_edx.bits.tsc != 0)
            result |= CPU_TSC;
        if (_cpuid_info.ext_cpuid7_edx.bits.tsc_invariance != 0)
            result |= CPU_TSCINV;

        // AMD features.
        if (is_amd()) {
            if ((_cpuid_info.ext_cpuid1_edx.bits.tdnow != 0) ||
                    (_cpuid_info.ext_cpuid1_ecx.bits.prefetchw != 0))
                result |= CPU_3DNOW_PREFETCH;
            if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt != 0)
                result |= CPU_LZCNT;
            if (_cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0)
                result |= CPU_SSE4A;
        }

        return result;
    }
 static intx prefetch_data_size()  {
   intx result = 0;
   if (is_intel()) {
     result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1);
   } else if (is_amd()) {
     result = _cpuid_info.ext_cpuid5_ecx.bits.L1_line_size;
   }
   if (result < 32) // not defined ?
     result = 32;   // 32 bytes by default on x86 and other x64
   return result;
 }
 static uint cores_per_cpu()  {
     uint result = 1;
     if (is_intel()) {
         if (supports_processor_topology()) {
             result = _cpuid_info.tpl_cpuidB1_ebx.bits.logical_cpus /
                      _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus;
         } else {
             result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1);
         }
     } else if (is_amd()) {
         result = (_cpuid_info.ext_cpuid8_ecx.bits.cores_per_cpu + 1);
     }
     return result;
 }
  static intx allocate_prefetch_distance() {
    // This method should be called before allocate_prefetch_style().
    //
    // Hardware prefetching (distance/size in bytes):
    // Pentium 3 -  64 /  32
    // Pentium 4 - 256 / 128
    // Athlon    -  64 /  32 ????
    // Opteron   - 128 /  64 only when 2 sequential cache lines accessed
    // Core      - 128 /  64
    //
    // Software prefetching (distance in bytes / instruction with best score):
    // Pentium 3 - 128 / prefetchnta
    // Pentium 4 - 512 / prefetchnta
    // Athlon    - 128 / prefetchnta
    // Opteron   - 256 / prefetchnta
    // Core      - 256 / prefetchnta
    // It will be used only when AllocatePrefetchStyle > 0

    intx count = AllocatePrefetchDistance;
    if (count < 0) {   // default ?
      if (is_amd()) {  // AMD
        if (supports_sse2())
          count = 256; // Opteron
        else
          count = 128; // Athlon
      } else {         // Intel
        if (supports_sse2())
          if (cpu_family() == 6) {
            count = 256; // Pentium M, Core, Core2
          } else {
            count = 512; // Pentium 4
          }
        else
          count = 128; // Pentium 3 (and all other old CPUs)
      }
    }
    return count;
  }
 static bool supports_tscinv() {
   return supports_tscinv_bit() &&
          ( (is_amd() && !is_amd_Barcelona()) ||
            is_intel_tsc_synched_at_init() );
 }
 static bool is_amd_Barcelona()  { return is_amd() &&
                                          extended_cpu_family() == CPU_FAMILY_AMD_11H; }
 static bool supports_mmx_ext()  { return is_amd() && _cpuid_info.ext_cpuid1_edx.bits.mmx_amd != 0; }
  static uint32_t feature_flags() {
    uint32_t result = 0;
    if (_cpuid_info.std_cpuid1_edx.bits.cmpxchg8 != 0)
      result |= CPU_CX8;
    if (_cpuid_info.std_cpuid1_edx.bits.cmov != 0)
      result |= CPU_CMOV;
    if (_cpuid_info.std_cpuid1_edx.bits.fxsr != 0 || (is_amd() &&
        _cpuid_info.ext_cpuid1_edx.bits.fxsr != 0))
      result |= CPU_FXSR;
    // HT flag is set for multi-core processors also.
    if (threads_per_core() > 1)
      result |= CPU_HT;
    if (_cpuid_info.std_cpuid1_edx.bits.mmx != 0 || (is_amd() &&
        _cpuid_info.ext_cpuid1_edx.bits.mmx != 0))
      result |= CPU_MMX;
    if (_cpuid_info.std_cpuid1_edx.bits.sse != 0)
      result |= CPU_SSE;
    if (_cpuid_info.std_cpuid1_edx.bits.sse2 != 0)
      result |= CPU_SSE2;
    if (_cpuid_info.std_cpuid1_ecx.bits.sse3 != 0)
      result |= CPU_SSE3;
    if (_cpuid_info.std_cpuid1_ecx.bits.ssse3 != 0)
      result |= CPU_SSSE3;
    if (_cpuid_info.std_cpuid1_ecx.bits.sse4_1 != 0)
      result |= CPU_SSE4_1;
    if (_cpuid_info.std_cpuid1_ecx.bits.sse4_2 != 0)
      result |= CPU_SSE4_2;
    if (_cpuid_info.std_cpuid1_ecx.bits.popcnt != 0)
      result |= CPU_POPCNT;
    if (_cpuid_info.std_cpuid1_ecx.bits.avx != 0 &&
        _cpuid_info.std_cpuid1_ecx.bits.osxsave != 0 &&
        _cpuid_info.xem_xcr0_eax.bits.sse != 0 &&
        _cpuid_info.xem_xcr0_eax.bits.ymm != 0) {
      result |= CPU_AVX;
      if (_cpuid_info.sef_cpuid7_ebx.bits.avx2 != 0)
        result |= CPU_AVX2;
    }
    if(_cpuid_info.sef_cpuid7_ebx.bits.bmi1 != 0)
      result |= CPU_BMI1;
    if (_cpuid_info.std_cpuid1_edx.bits.tsc != 0)
      result |= CPU_TSC;
    if (_cpuid_info.ext_cpuid7_edx.bits.tsc_invariance != 0)
      result |= CPU_TSCINV;
    if (_cpuid_info.std_cpuid1_ecx.bits.aes != 0)
      result |= CPU_AES;
    if (_cpuid_info.sef_cpuid7_ebx.bits.erms != 0)
      result |= CPU_ERMS;
    if (_cpuid_info.std_cpuid1_ecx.bits.clmul != 0)
      result |= CPU_CLMUL;
    if (_cpuid_info.sef_cpuid7_ebx.bits.rtm != 0)
      result |= CPU_RTM;

    // AMD features.
    if (is_amd()) {
      if ((_cpuid_info.ext_cpuid1_edx.bits.tdnow != 0) ||
          (_cpuid_info.ext_cpuid1_ecx.bits.prefetchw != 0))
        result |= CPU_3DNOW_PREFETCH;
      if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt != 0)
        result |= CPU_LZCNT;
      if (_cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0)
        result |= CPU_SSE4A;
    }
    // Intel features.
    if(is_intel()) {
      if(_cpuid_info.sef_cpuid7_ebx.bits.adx != 0)
         result |= CPU_ADX;
      if(_cpuid_info.sef_cpuid7_ebx.bits.bmi2 != 0)
        result |= CPU_BMI2;
      if(_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0)
        result |= CPU_LZCNT;
      // for Intel, ecx.bits.misalignsse bit (bit 8) indicates support for prefetchw
      if (_cpuid_info.ext_cpuid1_ecx.bits.misalignsse != 0) {
        result |= CPU_3DNOW_PREFETCH;
      }
    }

    return result;
  }
void VM_Version::get_processor_features() {

    _cpu = 4; // 486 by default
    _model = 0;
    _stepping = 0;
    _cpuFeatures = 0;
    _logical_processors_per_package = 1;

    if (!Use486InstrsOnly) {
        // Get raw processor info
        getPsrInfo_stub(&_cpuid_info);
        assert_is_initialized();
        _cpu = extended_cpu_family();
        _model = extended_cpu_model();
        _stepping = cpu_stepping();

        if (cpu_family() > 4) { // it supports CPUID
            _cpuFeatures = feature_flags();
            // Logical processors are only available on P4s and above,
            // and only if hyperthreading is available.
            _logical_processors_per_package = logical_processor_count();
        }
    }

    _supports_cx8 = supports_cmpxchg8();

#ifdef _LP64
    // OS should support SSE for x64 and hardware should support at least SSE2.
    if (!VM_Version::supports_sse2()) {
        vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported");
    }
    // in 64 bit the use of SSE2 is the minimum
    if (UseSSE < 2) UseSSE = 2;
#endif

#ifdef AMD64
    // flush_icache_stub have to be generated first.
    // That is why Icache line size is hard coded in ICache class,
    // see icache_x86.hpp. It is also the reason why we can't use
    // clflush instruction in 32-bit VM since it could be running
    // on CPU which does not support it.
    //
    // The only thing we can do is to verify that flushed
    // ICache::line_size has correct value.
    guarantee(_cpuid_info.std_cpuid1_edx.bits.clflush != 0, "clflush is not supported");
    // clflush_size is size in quadwords (8 bytes).
    guarantee(_cpuid_info.std_cpuid1_ebx.bits.clflush_size == 8, "such clflush size is not supported");
#endif

    // If the OS doesn't support SSE, we can't use this feature even if the HW does
    if (!os::supports_sse())
        _cpuFeatures &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4A|CPU_SSE4_1|CPU_SSE4_2);

    if (UseSSE < 4) {
        _cpuFeatures &= ~CPU_SSE4_1;
        _cpuFeatures &= ~CPU_SSE4_2;
    }

    if (UseSSE < 3) {
        _cpuFeatures &= ~CPU_SSE3;
        _cpuFeatures &= ~CPU_SSSE3;
        _cpuFeatures &= ~CPU_SSE4A;
    }

    if (UseSSE < 2)
        _cpuFeatures &= ~CPU_SSE2;

    if (UseSSE < 1)
        _cpuFeatures &= ~CPU_SSE;

    if (UseAVX < 2)
        _cpuFeatures &= ~CPU_AVX2;

    if (UseAVX < 1)
        _cpuFeatures &= ~CPU_AVX;

    if (logical_processors_per_package() == 1) {
        // HT processor could be installed on a system which doesn't support HT.
        _cpuFeatures &= ~CPU_HT;
    }

    char buf[256];
    jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
                 cores_per_cpu(), threads_per_core(),
                 cpu_family(), _model, _stepping,
                 (supports_cmov() ? ", cmov" : ""),
                 (supports_cmpxchg8() ? ", cx8" : ""),
                 (supports_fxsr() ? ", fxsr" : ""),
                 (supports_mmx()  ? ", mmx"  : ""),
                 (supports_sse()  ? ", sse"  : ""),
                 (supports_sse2() ? ", sse2" : ""),
                 (supports_sse3() ? ", sse3" : ""),
                 (supports_ssse3()? ", ssse3": ""),
                 (supports_sse4_1() ? ", sse4.1" : ""),
                 (supports_sse4_2() ? ", sse4.2" : ""),
                 (supports_popcnt() ? ", popcnt" : ""),
                 (supports_avx()    ? ", avx" : ""),
                 (supports_avx2()   ? ", avx2" : ""),
                 (supports_mmx_ext() ? ", mmxext" : ""),
                 (supports_3dnow_prefetch() ? ", 3dnowpref" : ""),
                 (supports_lzcnt()   ? ", lzcnt": ""),
                 (supports_sse4a()   ? ", sse4a": ""),
                 (supports_ht() ? ", ht": ""),
                 (supports_tsc() ? ", tsc": ""),
                 (supports_tscinv_bit() ? ", tscinvbit": ""),
                 (supports_tscinv() ? ", tscinv": ""));
    _features_str = strdup(buf);

    // UseSSE is set to the smaller of what hardware supports and what
    // the command line requires.  I.e., you cannot set UseSSE to 2 on
    // older Pentiums which do not support it.
    if (UseSSE > 4) UseSSE=4;
    if (UseSSE < 0) UseSSE=0;
    if (!supports_sse4_1()) // Drop to 3 if no SSE4 support
        UseSSE = MIN2((intx)3,UseSSE);
    if (!supports_sse3()) // Drop to 2 if no SSE3 support
        UseSSE = MIN2((intx)2,UseSSE);
    if (!supports_sse2()) // Drop to 1 if no SSE2 support
        UseSSE = MIN2((intx)1,UseSSE);
    if (!supports_sse ()) // Drop to 0 if no SSE  support
        UseSSE = 0;

    if (UseAVX > 2) UseAVX=2;
    if (UseAVX < 0) UseAVX=0;
    if (!supports_avx2()) // Drop to 1 if no AVX2 support
        UseAVX = MIN2((intx)1,UseAVX);
    if (!supports_avx ()) // Drop to 0 if no AVX  support
        UseAVX = 0;

    // On new cpus instructions which update whole XMM register should be used
    // to prevent partial register stall due to dependencies on high half.
    //
    // UseXmmLoadAndClearUpper == true  --> movsd(xmm, mem)
    // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem)
    // UseXmmRegToRegMoveAll == true  --> movaps(xmm, xmm), movapd(xmm, xmm).
    // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm),  movsd(xmm, xmm).

    if( is_amd() ) { // AMD cpus specific settings
        if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) {
            // Use it on new AMD cpus starting from Opteron.
            UseAddressNop = true;
        }
        if( supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift) ) {
            // Use it on new AMD cpus starting from Opteron.
            UseNewLongLShift = true;
        }
        if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
            if( supports_sse4a() ) {
                UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron
            } else {
                UseXmmLoadAndClearUpper = false;
            }
        }
        if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
            if( supports_sse4a() ) {
                UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h'
            } else {
                UseXmmRegToRegMoveAll = false;
            }
        }
        if( FLAG_IS_DEFAULT(UseXmmI2F) ) {
            if( supports_sse4a() ) {
                UseXmmI2F = true;
            } else {
                UseXmmI2F = false;
            }
        }
        if( FLAG_IS_DEFAULT(UseXmmI2D) ) {
            if( supports_sse4a() ) {
                UseXmmI2D = true;
            } else {
                UseXmmI2D = false;
            }
        }
        if( FLAG_IS_DEFAULT(UseSSE42Intrinsics) ) {
            if( supports_sse4_2() && UseSSE >= 4 ) {
                UseSSE42Intrinsics = true;
            }
        }

        // Use count leading zeros count instruction if available.
        if (supports_lzcnt()) {
            if (FLAG_IS_DEFAULT(UseCountLeadingZerosInstruction)) {
                UseCountLeadingZerosInstruction = true;
            }
        }

        // some defaults for AMD family 15h
        if ( cpu_family() == 0x15 ) {
            // On family 15h processors default is no sw prefetch
            if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
                AllocatePrefetchStyle = 0;
            }
            // Also, if some other prefetch style is specified, default instruction type is PREFETCHW
            if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
                AllocatePrefetchInstr = 3;
            }
            // On family 15h processors use XMM and UnalignedLoadStores for Array Copy
            if( FLAG_IS_DEFAULT(UseXMMForArrayCopy) ) {
                UseXMMForArrayCopy = true;
            }
            if( FLAG_IS_DEFAULT(UseUnalignedLoadStores) && UseXMMForArrayCopy ) {
                UseUnalignedLoadStores = true;
            }
        }

    }

    if( is_intel() ) { // Intel cpus specific settings
        if( FLAG_IS_DEFAULT(UseStoreImmI16) ) {
            UseStoreImmI16 = false; // don't use it on Intel cpus
        }
        if( cpu_family() == 6 || cpu_family() == 15 ) {
            if( FLAG_IS_DEFAULT(UseAddressNop) ) {
                // Use it on all Intel cpus starting from PentiumPro
                UseAddressNop = true;
            }
        }
        if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
            UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus
        }
        if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
            if( supports_sse3() ) {
                UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus
            } else {
                UseXmmRegToRegMoveAll = false;
            }
        }
        if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus
#ifdef COMPILER2
            if( FLAG_IS_DEFAULT(MaxLoopPad) ) {
                // For new Intel cpus do the next optimization:
                // don't align the beginning of a loop if there are enough instructions
                // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
                // in current fetch line (OptoLoopAlignment) or the padding
                // is big (> MaxLoopPad).
                // Set MaxLoopPad to 11 for new Intel cpus to reduce number of
                // generated NOP instructions. 11 is the largest size of one
                // address NOP instruction '0F 1F' (see Assembler::nop(i)).
                MaxLoopPad = 11;
            }
#endif // COMPILER2
            if( FLAG_IS_DEFAULT(UseXMMForArrayCopy) ) {
                UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus
            }
            if( supports_sse4_2() && supports_ht() ) { // Newest Intel cpus
                if( FLAG_IS_DEFAULT(UseUnalignedLoadStores) && UseXMMForArrayCopy ) {
                    UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
                }
            }
            if( supports_sse4_2() && UseSSE >= 4 ) {
                if( FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
                    UseSSE42Intrinsics = true;
                }
            }
        }
    }

    // Use population count instruction if available.
    if (supports_popcnt()) {
        if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
            UsePopCountInstruction = true;
        }
    } else if (UsePopCountInstruction) {
        warning("POPCNT instruction is not available on this CPU");
        FLAG_SET_DEFAULT(UsePopCountInstruction, false);
    }

#ifdef COMPILER2
    if (UseFPUForSpilling) {
        if (UseSSE < 2) {
            // Only supported with SSE2+
            FLAG_SET_DEFAULT(UseFPUForSpilling, false);
        }
    }
#endif

    assert(0 <= ReadPrefetchInstr && ReadPrefetchInstr <= 3, "invalid value");
    assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 3, "invalid value");

    // set valid Prefetch instruction
    if( ReadPrefetchInstr < 0 ) ReadPrefetchInstr = 0;
    if( ReadPrefetchInstr > 3 ) ReadPrefetchInstr = 3;
    if( ReadPrefetchInstr == 3 && !supports_3dnow_prefetch() ) ReadPrefetchInstr = 0;
    if( !supports_sse() && supports_3dnow_prefetch() ) ReadPrefetchInstr = 3;

    if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0;
    if( AllocatePrefetchInstr > 3 ) AllocatePrefetchInstr = 3;
    if( AllocatePrefetchInstr == 3 && !supports_3dnow_prefetch() ) AllocatePrefetchInstr=0;
    if( !supports_sse() && supports_3dnow_prefetch() ) AllocatePrefetchInstr = 3;

    // Allocation prefetch settings
    intx cache_line_size = prefetch_data_size();
    if( cache_line_size > AllocatePrefetchStepSize )
        AllocatePrefetchStepSize = cache_line_size;

    assert(AllocatePrefetchLines > 0, "invalid value");
    if( AllocatePrefetchLines < 1 )     // set valid value in product VM
        AllocatePrefetchLines = 3;
    assert(AllocateInstancePrefetchLines > 0, "invalid value");
    if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM
        AllocateInstancePrefetchLines = 1;

    AllocatePrefetchDistance = allocate_prefetch_distance();
    AllocatePrefetchStyle    = allocate_prefetch_style();

    if( is_intel() && cpu_family() == 6 && supports_sse3() ) {
        if( AllocatePrefetchStyle == 2 ) { // watermark prefetching on Core
#ifdef _LP64
            AllocatePrefetchDistance = 384;
#else
            AllocatePrefetchDistance = 320;
#endif
        }
        if( supports_sse4_2() && supports_ht() ) { // Nehalem based cpus
            AllocatePrefetchDistance = 192;
            AllocatePrefetchLines = 4;
#ifdef COMPILER2
            if (AggressiveOpts && FLAG_IS_DEFAULT(UseFPUForSpilling)) {
                FLAG_SET_DEFAULT(UseFPUForSpilling, true);
            }
#endif
        }
    }
    assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value");

#ifdef _LP64
    // Prefetch settings
    PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
    PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
    PrefetchFieldsAhead         = prefetch_fields_ahead();
#endif

#ifndef PRODUCT
    if (PrintMiscellaneous && Verbose) {
        tty->print_cr("Logical CPUs per core: %u",
                      logical_processors_per_package());
        tty->print("UseSSE=%d",UseSSE);
        if (UseAVX > 0) {
            tty->print("  UseAVX=%d",UseAVX);
        }
        tty->cr();
        tty->print("Allocation");
        if (AllocatePrefetchStyle <= 0 || UseSSE == 0 && !supports_3dnow_prefetch()) {
            tty->print_cr(": no prefetching");
        } else {
            tty->print(" prefetching: ");
            if (UseSSE == 0 && supports_3dnow_prefetch()) {
                tty->print("PREFETCHW");
            } else if (UseSSE >= 1) {
                if (AllocatePrefetchInstr == 0) {
                    tty->print("PREFETCHNTA");
                } else if (AllocatePrefetchInstr == 1) {
                    tty->print("PREFETCHT0");
                } else if (AllocatePrefetchInstr == 2) {
                    tty->print("PREFETCHT2");
                } else if (AllocatePrefetchInstr == 3) {
                    tty->print("PREFETCHW");
                }
            }
            if (AllocatePrefetchLines > 1) {
                tty->print_cr(" at distance %d, %d lines of %d bytes", AllocatePrefetchDistance, AllocatePrefetchLines, AllocatePrefetchStepSize);
            } else {
                tty->print_cr(" at distance %d, one line of %d bytes", AllocatePrefetchDistance, AllocatePrefetchStepSize);
            }
        }

        if (PrefetchCopyIntervalInBytes > 0) {
            tty->print_cr("PrefetchCopyIntervalInBytes %d", PrefetchCopyIntervalInBytes);
        }
        if (PrefetchScanIntervalInBytes > 0) {
            tty->print_cr("PrefetchScanIntervalInBytes %d", PrefetchScanIntervalInBytes);
        }
        if (PrefetchFieldsAhead > 0) {
            tty->print_cr("PrefetchFieldsAhead %d", PrefetchFieldsAhead);
        }
    }
#endif // !PRODUCT
}