static int init_logic(struct fpga_model* model, int y, int x, int idx)
{
	struct fpga_tile* tile;
	const char* pre;
	int i, j, rc;

	RC_CHECK(model);
	tile = YX_TILE(model, y, x);
	if (tile->devs[idx].subtype == LOGIC_M)
		pre = "M_";
	else if (tile->devs[idx].subtype == LOGIC_L)
		pre = "L_";
	else if (tile->devs[idx].subtype == LOGIC_X) {
		pre = is_atx(X_FABRIC_LOGIC_XL_COL|X_CENTER_LOGIC_COL, model, x)
			? "XX_" : "X_";
	} else FAIL(EINVAL);

	tile->devs[idx].pinw = calloc((LO_LAST+1)
		*sizeof(tile->devs[idx].pinw[0]), /*elsize*/ 1);
	if (!tile->devs[idx].pinw) FAIL(ENOMEM);
	tile->devs[idx].num_pinw_total = LO_LAST+1;
	tile->devs[idx].num_pinw_in = LI_LAST+1;

	for (i = 0; i < 4; i++) { // 'A' to 'D'
		for (j = 0; j < 6; j++) {
			rc = add_connpt_name(model, y, x, pf("%s%c%i", pre, 'A'+i, j+1),
				/*dup_warn*/ 1,
				&tile->devs[idx].pinw[LI_A1+i*6+j], 0);
			if (rc) FAIL(rc);
		}
		rc = add_connpt_name(model, y, x, pf("%s%cX", pre, 'A'+i),
			/*dup_warn*/ 1,
			&tile->devs[idx].pinw[LI_AX+i], 0);
		if (rc) FAIL(rc);
		if (tile->devs[idx].subtype == LOGIC_M) {
			rc = add_connpt_name(model, y, x, pf("%s%cI", pre, 'A'+i),
				/*dup_warn*/ 1,
				&tile->devs[idx].pinw[LI_AI+i], 0);
			if (rc) FAIL(rc);
		} else
			tile->devs[idx].pinw[LI_AI+i] = STRIDX_NO_ENTRY;
		rc = add_connpt_name(model, y, x, pf("%s%c", pre, 'A'+i),
			/*dup_warn*/ 1,
			&tile->devs[idx].pinw[LO_A+i], 0);
		if (rc) FAIL(rc);
		rc = add_connpt_name(model, y, x, pf("%s%cMUX", pre, 'A'+i),
			/*dup_warn*/ 1,
			&tile->devs[idx].pinw[LO_AMUX+i], 0);
		if (rc) FAIL(rc);
		rc = add_connpt_name(model, y, x, pf("%s%cQ", pre, 'A'+i),
			/*dup_warn*/ 1,
			&tile->devs[idx].pinw[LO_AQ+i], 0);
		if (rc) FAIL(rc);
	}
	rc = add_connpt_name(model, y, x, pf("%sCLK", pre),
		/*dup_warn*/ 1,
		&tile->devs[idx].pinw[LI_CLK], 0);
	if (rc) FAIL(rc);
	rc = add_connpt_name(model, y, x, pf("%sCE", pre),
		/*dup_warn*/ 1,
		&tile->devs[idx].pinw[LI_CE], 0);
	if (rc) FAIL(rc);
	rc = add_connpt_name(model, y, x, pf("%sSR", pre),
		/*dup_warn*/ 1,
		&tile->devs[idx].pinw[LI_SR], 0);
	if (rc) FAIL(rc);
	if (tile->devs[idx].subtype == LOGIC_M) {
		rc = add_connpt_name(model, y, x, pf("%sWE", pre),
			/*dup_warn*/ 1,
			&tile->devs[idx].pinw[LI_WE], 0);
		if (rc) FAIL(rc);
	} else
		tile->devs[idx].pinw[LI_WE] = STRIDX_NO_ENTRY;
	if (tile->devs[idx].subtype != LOGIC_X) {
		// Wire connections will go to some CIN later
		// (and must not warn about duplicates), but we
		// have to add the connection point here so
		// that pinw[LI_CIN] is initialized.
		rc = add_connpt_name(model, y, x, pf("%sCIN", pre),
			/*dup_warn*/ 1,
			&tile->devs[idx].pinw[LI_CIN], 0);
		if (rc) FAIL(rc);
	} else
		tile->devs[idx].pinw[LI_CIN] = STRIDX_NO_ENTRY;
	if (tile->devs[idx].subtype == LOGIC_M) {
		rc = add_connpt_name(model, y, x, "M_COUT",
			/*dup_warn*/ 1,
			&tile->devs[idx].pinw[LO_COUT], 0);
		if (rc) FAIL(rc);
	} else if (tile->devs[idx].subtype == LOGIC_L) {
		rc = add_connpt_name(model, y, x, "XL_COUT",
			/*dup_warn*/ 1,
			&tile->devs[idx].pinw[LO_COUT], 0);
		if (rc) FAIL(rc);
	} else 
		tile->devs[idx].pinw[LO_COUT] = STRIDX_NO_ENTRY;

	return 0;
fail:
	return rc;
}
Exemple #2
0
int init_ports(struct fpga_model* model, int dup_warn)
{
	int x, y, i, j, k, row_num, row_pos, rc;

	// inner and outer IO tiles (ILOGIC/ILOGIC/IODELAY)
	for (x = LEFT_SIDE_WIDTH; x < model->x_width - RIGHT_SIDE_WIDTH; x++) {
		if (has_device(model, TOP_OUTER_IO, x, DEV_ILOGIC)) {
			rc = init_iologic_ports(model, TOP_OUTER_IO, x, TOP_S, dup_warn);
			if (rc) goto xout;
		}
		if (has_device(model, TOP_INNER_IO, x, DEV_ILOGIC)) {
			rc = init_iologic_ports(model, TOP_INNER_IO, x, TOP_S, dup_warn);
			if (rc) goto xout;
		}
		if (has_device(model, model->y_height - BOT_INNER_IO, x, DEV_ILOGIC)) {
			rc = init_iologic_ports(model, model->y_height - BOT_INNER_IO, x, BOTTOM_S, dup_warn);
			if (rc) goto xout;
		}
		if (has_device(model, model->y_height - BOT_OUTER_IO, x, DEV_ILOGIC)) {
			rc = init_iologic_ports(model, model->y_height - BOT_OUTER_IO, x, BOTTOM_S, dup_warn);
			if (rc) goto xout;
		}
	}
	for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
		if (has_device(model, y, LEFT_IO_DEVS, DEV_ILOGIC)) {
			rc = init_iologic_ports(model, y, LEFT_IO_DEVS, LEFT_S, dup_warn);
			if (rc) goto xout;
		}
		if (has_device(model, y, model->x_width - RIGHT_IO_DEVS_O, DEV_ILOGIC)) {
			rc = init_iologic_ports(model, y, model->x_width - RIGHT_IO_DEVS_O, RIGHT_S, dup_warn);
			if (rc) goto xout;
		}
	}

	for (x = 0; x < model->x_width; x++) {
		// VCC, GND and fans
		if (is_atx(X_ROUTING_COL, model, x)) {
			for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
				if (is_aty(Y_ROW_HORIZ_AXSYMM|Y_CHIP_HORIZ_REGS,
						model, y))
					continue;
				rc = add_connpt_name(model, y, x, "VCC_WIRE",
					dup_warn, 0, 0);
				if (rc) goto xout;
				rc = add_connpt_name(model, y, x, "GND_WIRE",
					dup_warn, 0, 0);
				if (rc) goto xout;
				rc = add_connpt_name(model, y, x, "KEEP1_WIRE",
					dup_warn, 0, 0);
				if (rc) goto xout;
				rc = add_connpt_name(model, y, x, "FAN",
					dup_warn, 0, 0);
				if (rc) goto xout;
				rc = add_connpt_name(model, y, x, "FAN_B",
					dup_warn, 0, 0);
				if (rc) goto xout;

				if (!is_atyx(YX_IO_ROUTING, model, y, x)) {
					for (i = 0; i <= 1; i++) {
						rc = add_connpt_name(model, y, x, pf("GFAN%i", i),
							dup_warn, 0, 0);
						if (rc) goto xout;
					}
				} else {
					if (!is_atx(X_CENTER_ROUTING_COL, model, x)
					    || is_aty(Y_TOPBOT_IO_RANGE, model, y)) {
						// In the center those 2 wires are connected
						// to the PLL, but elsewhere? Not clear what they
						// connect to...
						rc = add_connpt_name(model, y, x,
							logicin_s(X_A5, 1 /* routing_io */),
							dup_warn, 0, 0);
						if (rc) goto xout;
						rc = add_connpt_name(model, y, x,
							logicin_s(X_B4, 1 /* routing_io */),
							dup_warn, 0, 0);
						if (rc) goto xout;
					}
				}
			}
		}

		// logicin
		if (is_atx(X_FABRIC_LOGIC_XL_ROUTING_COL
			  |X_CENTER_ROUTING_COL, model, x)) {
			
			for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
				static const int n[] = { 36, 44, 53, 61, 62 };

				if (is_aty(Y_TOPBOT_IO_RANGE, model, y)
				     && !is_atx(X_ROUTING_NO_IO, model, x))
					continue;
				if (is_aty(Y_ROW_HORIZ_AXSYMM|Y_CHIP_HORIZ_REGS,
					model, y))
					continue;
				if (is_atx(X_CENTER_ROUTING_COL, model, x)
				    && (is_aty(Y_ROW_HORIZ_AXSYMM|Y_CHIP_HORIZ_REGS,
						model, y+1)
				        || is_aty(Y_ROW_HORIZ_AXSYMM, model, y-1)))
					continue;

				for (i = 0; i < sizeof(n)/sizeof(*n); i++) {
					rc = add_connpt_name(model, y, x,
						pf("LOGICIN_B%i", n[i]), dup_warn, 0, 0);
					if (rc) goto xout;
				}
			}
		}

		// bram
		if (is_atx(X_FABRIC_BRAM_COL, model, x)) {
			for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
				if (YX_TILE(model, y, x)->flags & TF_BRAM_DEV) {

					static const char* pass_str[3] = {"RAMB16BWER", "RAMB8BWER_0", "RAMB8BWER_1"};
					// pass 0 is ramb16, pass 1 and 2 are for ramb8
					for (i = 0; i <= 2; i++) {
						for (j = 'A'; j <= 'B'; j++) {
							rc = add_connpt_name(model, y, x, pf("%s_CLK%c", pass_str[i], j),
								dup_warn, 0, 0);
							if (rc) goto xout;
							rc = add_connpt_name(model, y, x, pf("%s_EN%c", pass_str[i], j),
								dup_warn, 0, 0);
							if (rc) goto xout;
							rc = add_connpt_name(model, y, x, pf("%s_REGCE%c", pass_str[i], j),
								dup_warn, 0, 0);
							if (rc) goto xout;
							rc = add_connpt_name(model, y, x, pf("%s_RST%c", pass_str[i], j),
								dup_warn, 0, 0);
							if (rc) goto xout;
							for (k = 0; k <= (!i ? 3 : 1); k++) {
								rc = add_connpt_name(model, y, x, pf("%s_DIP%c%i", pass_str[i], j, k),
									dup_warn, 0, 0);
								if (rc) goto xout;
								rc = add_connpt_name(model, y, x, pf("%s_DOP%c%i", pass_str[i], j, k),
									dup_warn, 0, 0);
								if (rc) goto xout;
								rc = add_connpt_name(model, y, x, pf("%s_WE%c%i", pass_str[i], j, k),
									dup_warn, 0, 0);
								if (rc) goto xout;
							}
							for (k = 0; k <= (!i ? 13 : 12); k++) {
								rc = add_connpt_name(model, y, x, pf("%s_ADDR%c%i", pass_str[i], j, k),
									dup_warn, 0, 0);
								if (rc) goto xout;
							}
							for (k = 0; k <= (!i ? 31 : 15); k++) {
								rc = add_connpt_name(model, y, x, pf("%s_DI%c%i", pass_str[i], j, k),
									dup_warn, 0, 0);
								if (rc) goto xout;
								rc = add_connpt_name(model, y, x, pf("%s_DO%c%i", pass_str[i], j, k),
									dup_warn, 0, 0);
								if (rc) goto xout;
							}
						}
					}
				}
			}
		}
		// macc
		if (is_atx(X_FABRIC_MACC_COL, model, x)) {
			for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
				if (YX_TILE(model, y, x)->flags & TF_MACC_DEV) {
					static const char* pref[] = {"CE", "RST", ""};
					static const char* seq[] = {"A", "B", "C", "D", "M", "P", "OPMODE", ""};

					is_in_row(model, y, &row_num, &row_pos);
					if (!row_num && row_pos == LAST_POS_IN_ROW) {
						rc = add_connpt_name(model, y, x, "CARRYIN_DSP48A1_SITE",
							dup_warn, 0, 0);
						if (rc) goto xout;
						for (i = 0; i <= 47; i++) {
							rc = add_connpt_name(model, y, x, pf("PCIN%i_DSP48A1_SITE", i),
								dup_warn, 0, 0);
							if (rc) goto xout;
						}
					}

					rc = add_connpt_name(model, y, x, "CLK_DSP48A1_SITE",
						dup_warn, 0, 0);
					if (rc) goto xout;
					rc = add_connpt_name(model, y, x, "CARRYOUT_DSP48A1_SITE",
						dup_warn, 0, 0);
					if (rc) goto xout;
					rc = add_connpt_name(model, y, x, "CARRYOUTF_DSP48A1_SITE",
						dup_warn, 0, 0);
					if (rc) goto xout;

					for (i = 0; pref[i][0]; i++) {
						rc = add_connpt_name(model, y, x, pf("%sCARRYIN_DSP48A1_SITE", pref[i]),
							dup_warn, 0, 0);
						if (rc) goto xout;
						for (j = 0; seq[j][0]; j++) {
							rc = add_connpt_name(model, y, x, pf("%s%s_DSP48A1_SITE", pref[i], seq[j]),
								dup_warn, 0, 0);
							if (rc) goto xout;
						}
					}
						
					for (i = 0; i <= 17; i++) {
						rc = add_connpt_name(model, y, x, pf("A%i_DSP48A1_SITE", i),
							dup_warn, 0, 0);
						if (rc) goto xout;
						rc = add_connpt_name(model, y, x, pf("B%i_DSP48A1_SITE", i),
							dup_warn, 0, 0);
						if (rc) goto xout;
						rc = add_connpt_name(model, y, x, pf("D%i_DSP48A1_SITE", i),
							dup_warn, 0, 0);
						if (rc) goto xout;
						rc = add_connpt_name(model, y, x, pf("BCOUT%i_DSP48A1_SITE", i),
							dup_warn, 0, 0);
						if (rc) goto xout;
					}
					for (i = 0; i <= 47; i++) {
						rc = add_connpt_name(model, y, x, pf("C%i_DSP48A1_SITE", i),
							dup_warn, 0, 0);
						if (rc) goto xout;
						rc = add_connpt_name(model, y, x, pf("P%i_DSP48A1_SITE", i),
							dup_warn, 0, 0);
						if (rc) goto xout;
						rc = add_connpt_name(model, y, x, pf("PCOUT%i_DSP48A1_SITE", i),
							dup_warn, 0, 0);
						if (rc) goto xout;
					}
					for (i = 0; i <= 35; i++) {
						rc = add_connpt_name(model, y, x, pf("M%i_DSP48A1_SITE", i),
							dup_warn, 0, 0);
						if (rc) goto xout;
					}
					for (i = 0; i <= 7; i++) {
						rc = add_connpt_name(model, y, x, pf("OPMODE%i_DSP48A1_SITE", i),
							dup_warn, 0, 0);
						if (rc) goto xout;
					}
				}
			}
		}
	}
	return 0;
xout:
	return rc;
}
int init_devices(struct fpga_model* model)
{
	int x, y, i, j, rc;

	RC_CHECK(model);
	// DCM, PLL
	for (i = 0; i < model->die->num_rows; i++) {
		y = TOP_IO_TILES + HALF_ROW-1 + i*ROW_SIZE;
		if (y > model->center_y) y++; // central regs
		x = model->center_x-CENTER_CMTPLL_O;
		if (i%2) {
			if ((rc = add_dev(model, y, x, DEV_DCM, 0))) goto fail;
			if ((rc = add_dev(model, y, x, DEV_DCM, 0))) goto fail;
		} else
			if ((rc = add_dev(model, y, x, DEV_PLL, 0))) goto fail;
	}

	// BSCAN
	y = TOP_IO_TILES;
	x = model->x_width-RIGHT_IO_DEVS_O;
	if ((rc = add_dev(model, y, x, DEV_BSCAN, 0))) goto fail;
	if ((rc = add_dev(model, y, x, DEV_BSCAN, 0))) goto fail;

	// BSCAN, OCT_CALIBRATE
	y = TOP_IO_TILES+1;
	x = model->x_width-RIGHT_IO_DEVS_O;
	if ((rc = add_dev(model, y, x, DEV_BSCAN, 0))) goto fail;
	if ((rc = add_dev(model, y, x, DEV_BSCAN, 0))) goto fail;
	if ((rc = add_dev(model, y, x, DEV_OCT_CALIBRATE, 0))) goto fail;

	// ICAP, SPI_ACCESS, OCT_CALIBRATE
	y = model->y_height-BOT_IO_TILES-1;
	x = model->x_width-RIGHT_IO_DEVS_O;
	if ((rc = add_dev(model, y, x, DEV_ICAP, 0))) goto fail;
	if ((rc = add_dev(model, y, x, DEV_SPI_ACCESS, 0))) goto fail;
	if ((rc = add_dev(model, y, x, DEV_OCT_CALIBRATE, 0))) goto fail;

	// STARTUP, POST_CRC_INTERNAL, SLAVE_SPI, SUSPEND_SYNC
	y = model->y_height-BOT_IO_TILES-2;
	x = model->x_width-RIGHT_IO_DEVS_O;
	if ((rc = add_dev(model, y, x, DEV_STARTUP, 0))) goto fail;
	if ((rc = add_dev(model, y, x, DEV_POST_CRC_INTERNAL, 0))) goto fail;
	if ((rc = add_dev(model, y, x, DEV_SLAVE_SPI, 0))) goto fail;
	if ((rc = add_dev(model, y, x, DEV_SUSPEND_SYNC, 0))) goto fail;

	// MCB
	if ((rc = add_dev(model, model->die->mcb_ypos, LEFT_MCB_COL, DEV_MCB, 0))) goto fail;
	if ((rc = add_dev(model, model->die->mcb_ypos, model->x_width-RIGHT_MCB_O, DEV_MCB, 0))) goto fail;

	// OCT_CALIBRATE
	x = LEFT_IO_DEVS;
	if ((rc = add_dev(model, TOP_IO_TILES, x, DEV_OCT_CALIBRATE, 0)))
		FAIL(rc);
	if ((rc = add_dev(model, TOP_IO_TILES, x, DEV_OCT_CALIBRATE, 0)))
		FAIL(rc);
	if ((rc = add_dev(model, model->y_height-BOT_IO_TILES-1, x,
		DEV_OCT_CALIBRATE, 0))) FAIL(rc);
	if ((rc = add_dev(model, model->y_height-BOT_IO_TILES-1, x,
		DEV_OCT_CALIBRATE, 0))) FAIL(rc);

	// DNA, PMV
	x = LEFT_IO_DEVS;
	y = TOP_IO_TILES;
	if ((rc = add_dev(model, y, x, DEV_DNA, 0))) FAIL(rc);
	if ((rc = add_dev(model, y, x, DEV_PMV, 0))) FAIL(rc);

	// PCILOGIC_SE
	if ((rc = add_dev(model, model->center_y, LEFT_IO_ROUTING,
		DEV_PCILOGIC_SE, 0))) FAIL(rc);
	if ((rc = add_dev(model, model->center_y, model->x_width
		- RIGHT_IO_DEVS_O, DEV_PCILOGIC_SE, 0))) FAIL(rc);

	// BUFGMUX
	y = model->center_y;
	x = model->center_x;
	for (i = 0; i < 16; i++)
		if ((rc = add_dev(model, y, x, DEV_BUFGMUX, 0))) goto fail;

	// BUFIO, BUFIO_FB, BUFPLL, BUFPLL_MCB
	y = TOP_OUTER_ROW;
	x = model->center_x-CENTER_CMTPLL_O;
	if ((rc = add_dev(model, y, x, DEV_BUFPLL, 0))) goto fail;
	if ((rc = add_dev(model, y, x, DEV_BUFPLL, 0))) goto fail;
	if ((rc = add_dev(model, y, x, DEV_BUFPLL_MCB, 0))) goto fail;
	for (j = 0; j < 8; j++) {
		if ((rc = add_dev(model, y, x, DEV_BUFIO, 0))) goto fail;
		if ((rc = add_dev(model, y, x, DEV_BUFIO_FB, 0))) goto fail;
	}
	y = model->center_y;
	x = LEFT_OUTER_COL;
	if ((rc = add_dev(model, y, x, DEV_BUFPLL, 0))) goto fail;
	if ((rc = add_dev(model, y, x, DEV_BUFPLL, 0))) goto fail;
	if ((rc = add_dev(model, y, x, DEV_BUFPLL_MCB, 0))) goto fail;
	for (j = 0; j < 8; j++) {
		if ((rc = add_dev(model, y, x, DEV_BUFIO, 0))) goto fail;
		if ((rc = add_dev(model, y, x, DEV_BUFIO_FB, 0))) goto fail;
	}
	y = model->center_y;
	x = model->x_width - RIGHT_OUTER_O;
	if ((rc = add_dev(model, y, x, DEV_BUFPLL, 0))) goto fail;
	if ((rc = add_dev(model, y, x, DEV_BUFPLL, 0))) goto fail;
	if ((rc = add_dev(model, y, x, DEV_BUFPLL_MCB, 0))) goto fail;
	for (j = 0; j < 8; j++) {
		if ((rc = add_dev(model, y, x, DEV_BUFIO, 0))) goto fail;
		if ((rc = add_dev(model, y, x, DEV_BUFIO_FB, 0))) goto fail;
	}
	y = model->y_height - BOT_OUTER_ROW;
	x = model->center_x-CENTER_CMTPLL_O;
	if ((rc = add_dev(model, y, x, DEV_BUFPLL, 0))) goto fail;
	if ((rc = add_dev(model, y, x, DEV_BUFPLL, 0))) goto fail;
	if ((rc = add_dev(model, y, x, DEV_BUFPLL_MCB, 0))) goto fail;
	for (j = 0; j < 8; j++) {
		if ((rc = add_dev(model, y, x, DEV_BUFIO, 0))) goto fail;
		if ((rc = add_dev(model, y, x, DEV_BUFIO_FB, 0))) goto fail;
	}
	
	// BUFH
	for (i = 0; i < model->die->num_rows; i++) {
		y = TOP_IO_TILES + HALF_ROW + i*ROW_SIZE;
		if (y > model->center_y) y++; // central regs
		x = model->center_x;
		for (j = 0; j < 32; j++)
			if ((rc = add_dev(model, y, x, DEV_BUFH, 0))) goto fail;
	}

	// BRAM
	for (x = 0; x < model->x_width; x++) {
		if (!is_atx(X_FABRIC_BRAM_COL, model, x))
			continue;
		for (y = TOP_IO_TILES; y < model->y_height-BOT_IO_TILES; y++) {
			if (!(YX_TILE(model, y, x)->flags & TF_BRAM_DEV))
				continue;
			if ((rc = add_dev(model, y, x, DEV_BRAM16, 0)))
				goto fail;
			if ((rc = add_dev(model, y, x, DEV_BRAM8, 0)))
				goto fail;
			if ((rc = add_dev(model, y, x, DEV_BRAM8, 0)))
				goto fail;
		}
	}

	// MACC
	for (x = 0; x < model->x_width; x++) {
		if (!is_atx(X_FABRIC_MACC_COL, model, x))
			continue;
		for (y = TOP_IO_TILES; y < model->y_height-BOT_IO_TILES; y++) {
			if (!(YX_TILE(model, y, x)->flags & TF_MACC_DEV))
				continue;
			if ((rc = add_dev(model, y, x, DEV_MACC, 0))) goto fail;
		}
	}

	// ILOGIC/OLOGIC/IODELAY
	for (x = LEFT_SIDE_WIDTH; x < model->x_width - RIGHT_SIDE_WIDTH; x++) {
		if (!is_atx(X_FABRIC_LOGIC_COL|X_CENTER_LOGIC_COL, model, x)
		    || is_atx(X_ROUTING_NO_IO, model, x-1))
			continue;
		for (i = 0; i <= 1; i++) {
			y = TOP_IO_TILES+i;
			for (j = 0; j <= 1; j++) {
				if ((rc = add_dev(model, y, x, DEV_ILOGIC, 0)))
					goto fail;
				if ((rc = add_dev(model, y, x, DEV_OLOGIC, 0)))
					goto fail;
				if ((rc = add_dev(model, y, x, DEV_IODELAY, 0)))
					goto fail;
			}
			y = model->y_height-BOT_IO_TILES-i-1;
			for (j = 0; j <= 1; j++) {
				if ((rc = add_dev(model, y, x, DEV_ILOGIC, 0)))
					goto fail;
				if ((rc = add_dev(model, y, x, DEV_OLOGIC, 0)))
					goto fail;
				if ((rc = add_dev(model, y, x, DEV_IODELAY, 0)))
					goto fail;
			}
		}
	}
	for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
		if (is_aty(Y_LEFT_WIRED, model, y)) {
			x = LEFT_IO_DEVS;
			for (j = 0; j <= 1; j++) {
				if ((rc = add_dev(model, y, x, DEV_ILOGIC, 0)))
					goto fail;
				if ((rc = add_dev(model, y, x, DEV_OLOGIC, 0)))
					goto fail;
				if ((rc = add_dev(model, y, x, DEV_IODELAY, 0)))
					goto fail;
			}
		}
		if (is_aty(Y_RIGHT_WIRED, model, y)) {
			x = model->x_width-RIGHT_IO_DEVS_O;
			for (j = 0; j <= 1; j++) {
				if ((rc = add_dev(model, y, x, DEV_ILOGIC, 0)))
					goto fail;
				if ((rc = add_dev(model, y, x, DEV_OLOGIC, 0)))
					goto fail;
				if ((rc = add_dev(model, y, x, DEV_IODELAY, 0)))
					goto fail;
			}
		}
	}
	// IOB
	for (x = 0; x < model->x_width; x++) {
		// Note that the order of sub-types IOBM and IOBS must match
		// the order in the control.c sitename arrays.
		if (is_atx(X_OUTER_LEFT, model, x)) {
			for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
				if (!is_aty(Y_LEFT_WIRED, model, y))
					continue;
				if ((rc = add_dev(model, y, x, DEV_IOB, IOBM))) goto fail;
				if ((rc = add_dev(model, y, x, DEV_IOB, IOBS))) goto fail;
			}
		}
		if (is_atx(X_OUTER_RIGHT, model, x)) {
			for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
				if (!is_aty(Y_RIGHT_WIRED, model, y))
					continue;
				if ((rc = add_dev(model, y, x, DEV_IOB, IOBM))) goto fail;
				if ((rc = add_dev(model, y, x, DEV_IOB, IOBS))) goto fail;
			}
		}
		if (is_atx(X_FABRIC_LOGIC_ROUTING_COL|X_CENTER_ROUTING_COL, model, x)
		    && !is_atx(X_ROUTING_NO_IO, model, x)) {
			y = TOP_OUTER_ROW;
			if ((rc = add_dev(model, y, x, DEV_IOB, IOBM))) goto fail;
			if ((rc = add_dev(model, y, x, DEV_IOB, IOBS))) goto fail;
			if ((rc = add_dev(model, y, x, DEV_IOB, IOBM))) goto fail;
			if ((rc = add_dev(model, y, x, DEV_IOB, IOBS))) goto fail;

			y = model->y_height-BOT_OUTER_ROW;
			if ((rc = add_dev(model, y, x, DEV_IOB, IOBM))) goto fail;
			if ((rc = add_dev(model, y, x, DEV_IOB, IOBS))) goto fail;
			if ((rc = add_dev(model, y, x, DEV_IOB, IOBS))) goto fail;
			if ((rc = add_dev(model, y, x, DEV_IOB, IOBM))) goto fail;
		}
	}

	// TIEOFF
	y = model->center_y;
	x = LEFT_OUTER_COL;
	if ((rc = add_dev(model, y, x, DEV_TIEOFF, 0))) goto fail;
	y = model->center_y;
	x = model->x_width-RIGHT_OUTER_O;
	if ((rc = add_dev(model, y, x, DEV_TIEOFF, 0))) goto fail;
	y = TOP_OUTER_ROW;
	x = model->center_x-1;
	if ((rc = add_dev(model, y, x, DEV_TIEOFF, 0))) goto fail;
	y = model->y_height-BOT_OUTER_ROW;
	x = model->center_x-CENTER_CMTPLL_O;
	if ((rc = add_dev(model, y, x, DEV_TIEOFF, 0))) goto fail;

	for (x = 0; x < model->x_width; x++) {
		if (is_atx(X_LEFT_IO_DEVS_COL, model, x)) {
			for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
				if (!is_aty(Y_LEFT_WIRED, model, y))
					continue;
				if ((rc = add_dev(model, y, x, DEV_TIEOFF, 0))) goto fail;
			}
		}
		if (is_atx(X_RIGHT_IO_DEVS_COL, model, x)) {
			for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
				if (!is_aty(Y_RIGHT_WIRED, model, y))
					continue;
				if ((rc = add_dev(model, y, x, DEV_TIEOFF, 0))) goto fail;
			}
		}
		if (is_atx(X_CENTER_CMTPLL_COL, model, x)) {
			for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
				if (!(YX_TILE(model, y, x)->flags & TF_PLL_DEV))
					continue;
				if ((rc = add_dev(model, y, x, DEV_TIEOFF, 0))) goto fail;
				
			}
		}
		if (is_atx(X_ROUTING_COL, model, x)) {
			for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
				if (is_aty(Y_ROW_HORIZ_AXSYMM|Y_CHIP_HORIZ_REGS,
						model, y))
					continue;
				if ((rc = add_dev(model, y, x, DEV_TIEOFF, 0))) goto fail;
			}
		}
		if (is_atx(X_FABRIC_LOGIC_COL|X_CENTER_LOGIC_COL, model, x)
		    && !is_atx(X_ROUTING_NO_IO, model, x-1)) {
			for (i = 0; i <= 1; i++) {
				y = TOP_IO_TILES+i;
				if ((rc = add_dev(model, y, x, DEV_TIEOFF, 0))) goto fail;
				y = model->y_height-BOT_IO_TILES-i-1;
				if ((rc = add_dev(model, y, x, DEV_TIEOFF, 0))) goto fail;
			}
		}
	}
	// LOGIC
	for (x = 0; x < model->x_width; x++) {
		if (!is_atx(X_FABRIC_LOGIC_COL|X_CENTER_LOGIC_COL, model, x))
			continue;
		for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
			// M and L are at index 0 (DEV_LOG_M_OR_L),
			// X is at index 1 (DEV_LOG_X).
			if (YX_TILE(model, y, x)->flags & TF_LOGIC_XM_DEV) {
				if ((rc = add_dev(model, y, x, DEV_LOGIC, LOGIC_M))) goto fail;
				if ((rc = add_dev(model, y, x, DEV_LOGIC, LOGIC_X))) goto fail;
			}
			if (YX_TILE(model, y, x)->flags & TF_LOGIC_XL_DEV) {
				if ((rc = add_dev(model, y, x, DEV_LOGIC, LOGIC_L))) goto fail;
				if ((rc = add_dev(model, y, x, DEV_LOGIC, LOGIC_X))) goto fail;
			}
		}
	}
	return 0;
fail:
	return rc;
}