int gpu_dvfs_decide_max_clock(struct exynos_context *platform) { int table_id; int level; if (!platform) return -1; table_id = cal_get_table_ver(); if (table_id < 0) return -1; if (table_id >= GPU_DVFS_TABLE_LIST_SIZE(available_max_clock)) table_id = GPU_DVFS_TABLE_LIST_SIZE(available_max_clock)-1; level = available_max_clock[table_id]; platform->gpu_max_clock = MIN(platform->gpu_max_clock, platform->table[level].clock); if (is_max_limit_sample()) platform->gpu_max_clock = MIN(platform->gpu_max_clock, platform->table[GPU_L3].clock); return 0; }
int exynos5_init_asv(struct asv_common *asv_info) { asv_info->ops_cal = &exynos5_asv_ops_common_cal; asv_info->ops_cal->init(); /* CAL initiallize */ if (asv_info->ops_cal->get_ids != NULL) pr_info("ASV: EGL IDS: %d \n", asv_info->ops_cal->get_ids()); if (asv_info->ops_cal->get_table_ver != NULL) pr_info("ASV: ASV Table Ver : %d \n", asv_info->ops_cal->get_table_ver()); if (is_max_limit_sample()) pr_info("ASV: ATL max frequency limited\n"); if (asv_info->ops_cal->is_fused_sp_gr()) pr_info("ASV: Use Speed Group\n"); else { pr_info("ASV: Use not Speed Group\n"); if (asv_info->ops_cal->get_asv_gr != NULL) pr_info("ASV: ASV_Group : %d \n", asv_info->ops_cal->get_asv_gr()); } register_syscore_ops(&exynos5_asv_syscore_ops); asv_info->regist_asv_member = exynos5_regist_asv_member; exynos5_set_asv_level_nr(asv_info); return 0; }