void board_BeforeAgesa(struct sysinfo *cb)
{
u8 byte;
/* Enable the AcpiMmio space */
outb(0x24, 0xcd6);
outb(0x1, 0xcd7);
/* Set LPC decode enables. */
pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
pci_write_config32(dev, 0x44, 0xff03ffd5);
if (CONFIG(POST_DEVICE_PCI_PCIE))
hudson_pci_port80();
if (CONFIG(POST_DEVICE_LPC))
hudson_lpc_port80();
/* enable SIO LPC decode */
byte = pci_read_config8(dev, 0x48);
byte |= 3; /* 2e, 2f */
pci_write_config8(dev, 0x48, byte);
/* enable serial decode */
byte = pci_read_config8(dev, 0x44);
byte |= (1 << 6); /* 0x3f8 */
pci_write_config8(dev, 0x44, byte);
/* run ite */
sbxxx_enable_48mhzout();
ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48);
ite_kill_watchdog(GPIO_DEV);
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
}
void mainboard_config_superio(void)
{
setup_sio_gpios();
/* Early SuperIO setup */
it8772f_ac_resume_southbridge(DUMMY_DEV);
ite_kill_watchdog(GPIO_DEV);
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
}
void mainboard_pre_console_init(void)
{
/* Early SuperIO setup */
it8772f_ac_resume_southbridge(IT8772F_SUPERIO_DEV);
ite_kill_watchdog(IT8772F_GPIO_DEV);
ite_enable_serial(IT8772F_SERIAL_DEV, CONFIG_TTYS0_BASE);
/* Turn On Power LED */
set_power_led(LED_ON);
}
void main(unsigned long bist)
{
/* Enable multifunction for northbridge. */
pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
enable_smbus();
smbus_fixup(&ctrl);
report_bist_failure(bist);
ddr_ram_setup(&ctrl);
}
void main(unsigned long bist)
{
ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24);
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
report_bist_failure(bist);
enable_smbus();
dump_spd_registers();
sdram_set_registers();
sdram_set_spd_registers();
sdram_enable();
dump_spd_registers();
}
void mb_enable_lpc(void)
{
/* Disable Serial IRQ */
pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);
/* Decode range */
pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC,
pci_read_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC) | 0x0010);
pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN | KBC_LPC_EN
| FDD_LPC_EN | LPT_LPC_EN | COMB_LPC_EN
| COMA_LPC_EN);
/* Environment Controller */
pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x00fc0a01);
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
}
void pch_enable_lpc(void)
{
/*
* Enable:
* EC Decode Range PortA30/A20
* SuperIO Port2E/2F
* PS/2 Keyboard/Mouse Port60/64
* FDD Port3F0h-3F5h and Port3F7h
*/
pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN |
CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN);
pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x3c0a01);
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
pci_write_config32(PCH_LPC_DEV, 0xac, 0x10000);
/* Initialize SuperIO */
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
it8728f_b75md3h_disable_reboot(SUPERIO_GPIO);
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
// Node 0
DIMM0, DIMM2, 0, 0,
DIMM1, DIMM3, 0, 0,
// Node 1
DIMM4, DIMM6, 0, 0,
DIMM5, DIMM7, 0, 0,
};
struct sys_info *sysinfo = &sysinfo_car;
int needs_reset = 0;
unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
sio_setup();
}
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
#if 0
uint8_t tmp = 0;
pnp_enter_ext_func_mode(SERIAL_DEV);
/* The following line will set CLKIN to 24 MHz, external */
pnp_write_config(SERIAL_DEV, IT8716F_CONFIG_REG_CLOCKSEL, 0x11);
tmp = pnp_read_config(SERIAL_DEV, IT8716F_CONFIG_REG_SWSUSP);
/* Is serial flash enabled? Then enable writing to serial flash. */
if (tmp & 0x0e) {
pnp_write_config(SERIAL_DEV, IT8716F_CONFIG_REG_SWSUSP, tmp | 0x10);
pnp_set_logical_device(GPIO_DEV);
/* Set Serial Flash interface to 0x0820 */
pnp_write_config(GPIO_DEV, 0x64, 0x08);
pnp_write_config(GPIO_DEV, 0x65, 0x20);
}
it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
pnp_exit_ext_func_mode(SERIAL_DEV);
#endif
ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48);
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
setup_mb_resource_map();
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
setup_coherent_ht_domain(); // routing table and start other core0
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
// It is said that we should start core1 after all core0 launched
/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
* So here need to make sure last core0 is started, esp for two way system,
* (there may be apic id conflicts in that case)
*/
start_other_cores();
wait_all_other_cores_started(bsp_apicid);
#endif
/* it will set up chains and store link pair for optimization later */
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if CONFIG_SET_FIDVID
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
}
enable_fid_change();
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
init_fidvid_bsp(bsp_apicid);
// show final fid and vid
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
}
#endif
init_timer(); // Need to use TMICT to synconize FID/VID
needs_reset |= optimize_link_coherent_ht();
needs_reset |= optimize_link_incoherent_ht(sysinfo);
needs_reset |= mcp55_early_setup_x();
// fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) {
print_info("ht reset -\n");
soft_reset();
}
allow_all_aps_stop(bsp_apicid);
//It's the time to set ctrl in sysinfo now;
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
enable_smbus();
/* all ap stopped? */
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
}
void main(unsigned long bist)
{
int boot_mode = 0;
int cbmem_was_initted;
struct pei_data pei_data = {
.pei_version = PEI_VERSION,
.mchbar = (uintptr_t)DEFAULT_MCHBAR,
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
.smbusbar = SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = CONFIG_HPET_ADDRESS,
.rcba = (uintptr_t)DEFAULT_RCBABASE,
.pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE,
.thermalbase = 0xfed08000,
.system_type = 0, // 0 Mobile, 1 Desktop/Server
.tseg_size = CONFIG_SMM_TSEG_SIZE,
.spd_addresses = { 0xa0, 0x00,0xa4,0x00 },
.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
.ec_present = 0,
// 0 = leave channel enabled
// 1 = disable dimm 0 on channel
// 2 = disable dimm 1 on channel
// 3 = disable dimm 0+1 on channel
.dimm_channel0_disabled = 2,
.dimm_channel1_disabled = 2,
.max_ddr3_freq = 1333,
.usb_port_config = {
{ 1, 0, 0x0080 }, /* P0: Front port (OC0) */
{ 1, 1, 0x0040 }, /* P1: Back port (OC1) */
{ 1, 0, 0x0040 }, /* P2: MINIPCIE1 (no OC) */
{ 1, 0, 0x0040 }, /* P3: MMC (no OC) */
{ 1, 2, 0x0080 }, /* P4: Front port (OC2) */
{ 0, 0, 0x0000 }, /* P5: Empty */
{ 0, 0, 0x0000 }, /* P6: Empty */
{ 0, 0, 0x0000 }, /* P7: Empty */
{ 1, 4, 0x0040 }, /* P8: Back port (OC4) */
{ 1, 4, 0x0040 }, /* P9: MINIPCIE3 (no OC) */
{ 1, 4, 0x0040 }, /* P10: BLUETOOTH (no OC) */
{ 0, 4, 0x0000 }, /* P11: Empty */
{ 1, 6, 0x0040 }, /* P12: Back port (OC6) */
{ 1, 5, 0x0040 }, /* P13: Back port (OC5) */
},
};
timestamp_init(get_initial_timestamp());
timestamp_add_now(TS_START_ROMSTAGE);
if (bist == 0)
enable_lapic();
pch_enable_lpc();
/* Enable GPIOs */
pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1);
pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
setup_pch_gpios(&stumpy_gpio_map);
setup_sio_gpios();
/* Early SuperIO setup */
it8772f_ac_resume_southbridge(DUMMY_DEV);
ite_kill_watchdog(GPIO_DEV);
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
init_bootmode_straps();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
if (MCHBAR16(SSKPD) == 0xCAFE) {
printk(BIOS_DEBUG, "soft reset detected\n");
boot_mode = 1;
/* System is not happy after keyboard reset... */
printk(BIOS_DEBUG, "Issuing CF9 warm reset\n");
outb(0x6, 0xcf9);
halt();
}
/* Perform some early chipset initialization required
* before RAM initialization can work
*/
sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
boot_mode = southbridge_detect_s3_resume() ? 2 : 0;
post_code(0x38);
/* Enable SPD ROMs and DDR-III DRAM */
enable_smbus();
/* Prepare USB controller early in S3 resume */
if (boot_mode == 2) {
/*
* For Stumpy the back USB ports are reset on resume
* so default to resetting the controller to make the
* kernel happy. There is a CMOS flag to disable the
* controller reset in case the kernel can tolerate
* the device power loss better in the future.
*/
u8 magic = cmos_read(CMOS_USB_RESET_DISABLE);
if (magic == USB_RESET_DISABLE_MAGIC) {
printk(BIOS_DEBUG, "USB Controller Reset Disabled\n");
enable_usb_bar();
} else {
printk(BIOS_DEBUG, "USB Controller Reset Enabled\n");
}
} else {
/* Ensure USB reset on resume is enabled at boot */
cmos_write(0, CMOS_USB_RESET_DISABLE);
}
post_code(0x39);
pei_data.boot_mode = boot_mode;
timestamp_add_now(TS_BEFORE_INITRAM);
sdram_initialize(&pei_data);
timestamp_add_now(TS_AFTER_INITRAM);
post_code(0x3a);
/* Perform some initialization that must run before stage2 */
early_pch_init();
post_code(0x3b);
rcba_config();
post_code(0x3c);
quick_ram_check();
post_code(0x3e);
cbmem_was_initted = !cbmem_recovery(boot_mode==2);
if (boot_mode!=2)
save_mrc_data(&pei_data);
if (boot_mode==2 && !cbmem_was_initted) {
/* Failed S3 resume, reset to come up cleanly */
outb(0x6, 0xcf9);
halt();
}
northbridge_romstage_finalize(boot_mode==2);
post_code(0x3f);
if (CONFIG_LPC_TPM) {
init_tpm(boot_mode == 2);
}
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
int needs_reset = 0;
u32 bsp_apicid = 0;
msr_t msr;
struct cpuid_result cpuid1;
struct sys_info *sysinfo = &sysinfo_car;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
/* sb600_lpc_port80(); */
sb600_pci_port80();
}
technexion_post_code_init();
technexion_post_code(LED_MESSAGE_START);
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
enable_rs690_dev8();
sb600_lpc_init();
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
ite_kill_watchdog(GPIO_DEV);
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
printk(BIOS_DEBUG, "bsp_apicid=0x%x\n", bsp_apicid);
setup_tim5690_resource_map();
setup_coherent_ht_domain();
#if CONFIG_LOGICAL_CPUS
/* It is said that we should start core1 after all core0 launched */
wait_all_core0_started();
start_other_cores();
#endif
wait_all_aps_started(bsp_apicid);
ht_setup_chains_x(sysinfo);
/* run _early_setup before soft-reset. */
rs690_early_setup();
sb600_early_setup();
/* Check to see if processor is capable of changing FIDVID */
/* otherwise it will throw a GP# when reading FIDVID_STATUS */
cpuid1 = cpuid(0x80000007);
if ((cpuid1.edx & 0x6) == 0x6) {
/* Read FIDVID_STATUS */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
enable_fid_change();
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
init_fidvid_bsp(bsp_apicid);
/* show final fid and vid */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
} else {
printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
}
needs_reset = optimize_link_coherent_ht();
needs_reset |= optimize_link_incoherent_ht(sysinfo);
rs690_htinit();
printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
if (needs_reset) {
printk(BIOS_INFO, "ht reset -\n");
soft_reset();
}
speaker_init(255);
speaker_on_nodelay();
allow_all_aps_stop(bsp_apicid);
/* It's the time to set ctrl now; */
printk(BIOS_DEBUG, "sysinfo->nodes: %2x sysinfo->ctrl: %p spd_addr: %p\n",
sysinfo->nodes, sysinfo->ctrl, spd_addr);
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
technexion_post_code(LED_MESSAGE_RAM);
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
speaker_off_nodelay();
rs690_before_pci_init();
sb600_before_pci_init();
post_cache_as_ram();
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
// Node 0
DIMM0, DIMM2, 0, 0,
DIMM1, DIMM3, 0, 0,
// Node 1
DIMM4, DIMM6, 0, 0,
DIMM5, DIMM7, 0, 0,
};
unsigned bsp_apicid = 0;
int needs_reset = 0;
struct sys_info *sysinfo = &sysinfo_car;
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
it8712f_kill_watchdog();
it8712f_enable_3vsbsw();
console_init();
enable_rom_decode();
printk(BIOS_INFO, "now booting... \n");
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
/* Halt if there was a built in self test failure. */
report_bist_failure(bist);
setup_default_resource_map();
setup_coherent_ht_domain();
wait_all_core0_started();
printk(BIOS_INFO, "now booting... All core 0 started\n");
#if CONFIG_LOGICAL_CPUS
/* It is said that we should start core1 after all core0 launched. */
start_other_cores();
wait_all_other_cores_started(bsp_apicid);
#endif
init_timer();
ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
needs_reset = optimize_link_coherent_ht();
print_debug_hex8(needs_reset);
needs_reset |= optimize_link_incoherent_ht(sysinfo);
print_debug_hex8(needs_reset);
needs_reset |= k8t890_early_setup_ht();
print_debug_hex8(needs_reset);
vt8237_early_network_init(NULL);
vt8237_early_spi_init();
if (needs_reset) {
printk(BIOS_DEBUG, "ht reset -\n");
soft_reset();
printk(BIOS_DEBUG, "FAILED!\n");
}
/* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */
/* allow LDT STOP asserts */
vt8237_sb_enable_fid_vid();
enable_fid_change();
print_debug("after enable_fid_change\n");
init_fidvid_bsp(bsp_apicid);
/* Stop the APs so we can start them later in init. */
allow_all_aps_stop(bsp_apicid);
/* It's the time to set ctrl now. */
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
enable_smbus();
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
post_cache_as_ram();
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
if (!cpu_init_detectedx && boot_cpu()) {
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
/*
* SR5650/5670/5690 RD890 chipset, read pci config space hang at POR,
* Disable all Pcie Bridges to work around It.
*/
sr56x0_rd890_disable_pcie_bridge();
}
post_code(0x32);
val = agesawrapper_amdinitmmio();
if (val) {
printk(BIOS_DEBUG, "agesawrapper_amdinitmmio failed: %x \n", val);
} else {
printk(BIOS_DEBUG, "agesawrapper_amdinitmmio passed\n");
}
/* Halt if there was a built in self test failure */
post_code(0x33);
report_bist_failure(bist);
// Load MPB
val = cpuid_eax(1);
printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
if(boot_cpu()) {
post_code(0x34);
sb_Poweron_Init();
}
post_code(0x35);
val = agesawrapper_amdinitreset();
if (val) {
printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val);
} else {
printk(BIOS_DEBUG, "agesawrapper_amdinitreset passed\n");
}
post_code(0x36);
val = agesawrapper_amdinitearly ();
if (val) {
printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val);
} else {
printk(BIOS_DEBUG, "agesawrapper_amdinitearly passed\n");
}
post_code(0x37);
nb_Poweron_Init();
post_code(0x38);
nb_Ht_Init();
post_code(0x39);
val = agesawrapper_amdinitpost ();
if (val) {
printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val);
} else {
printk(BIOS_DEBUG, "agesawrapper_amdinitpost passed\n");
}
post_code(0x40);
val = agesawrapper_amdinitenv ();
if (val) {
printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val);
} else {
printk(BIOS_DEBUG, "agesawrapper_amdinitenv passed\n");
}
post_code(0x43);
print_debug("Disabling cache as ram ");
disable_cache_as_ram();
print_debug("done\n");
post_code(0x44);
copy_and_run();
post_code(0x45); // Should never see this post code.
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
// Node 0
DIMM0, DIMM2, 0, 0,
DIMM1, DIMM3, 0, 0,
// Node 1
DIMM4, DIMM6, 0, 0,
DIMM5, DIMM7, 0, 0,
};
struct sys_info *sysinfo = &sysinfo_car;
int needs_reset = 0;
unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
sio_setup();
}
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48);
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
setup_mb_resource_map();
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
setup_coherent_ht_domain(); // routing table and start other core0
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
// It is said that we should start core1 after all core0 launched
/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
* So here need to make sure last core0 is started, esp for two way system,
* (there may be apic id conflicts in that case)
*/
start_other_cores();
wait_all_other_cores_started(bsp_apicid);
#endif
/* it will set up chains and store link pair for optimization later */
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if CONFIG_SET_FIDVID
{
msr_t msr;
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
}
enable_fid_change();
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
init_fidvid_bsp(bsp_apicid);
// show final fid and vid
{
msr_t msr;
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo);
}
#endif
needs_reset |= optimize_link_coherent_ht();
needs_reset |= optimize_link_incoherent_ht(sysinfo);
// fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) {
printk(BIOS_INFO, "ht reset -\n");
soft_reset();
}
allow_all_aps_stop(bsp_apicid);
//It's the time to set ctrl in sysinfo now;
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
sis_init_stage1();
enable_smbus();
//do we need apci timer, tsc...., only debug need it for better output
/* all ap stopped? */
// init_timer(); // Need to use TMICT to synchronize FID/VID
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
sis_init_stage2();
post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const u16 spd_addr[] = {
DIMM0, DIMM2, 0, 0, /* Channel A (DIMM_A1, DIMM_A2) */
DIMM1, DIMM3, 0, 0, /* Channel B (DIMM_B1, DIMM_B2) */
};
struct sys_info *sysinfo = &sysinfo_car;
int needs_reset = 0;
unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) {
/* Allow the HT devices to be found. */
enumerate_ht_chain();
sio_setup();
}
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24);
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
setup_mb_resource_map();
report_bist_failure(bist);
console_init();
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo, sysinfo + 1);
printk(BIOS_DEBUG, "bsp_apicid=0x%02x\n", bsp_apicid);
/* In BSP so could hold all AP until sysinfo is in RAM. */
set_sysinfo_in_ram(0);
setup_coherent_ht_domain(); /* Routing table and start other core0. */
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
/*
* It is said that we should start core1 after all core0 launched
* becase optimize_link_coherent_ht is moved out from
* setup_coherent_ht_domain, so here need to make sure last core0 is
* started, esp for two way system (there may be APIC ID conflicts in
* that case).
*/
start_other_cores();
wait_all_other_cores_started(bsp_apicid);
#endif
/* Set up chains and store link pair for optimization later. */
ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
/* TODO: FIDVID */
init_timer(); /* Need to use TMICT to synchronize FID/VID. */
needs_reset |= optimize_link_coherent_ht();
needs_reset |= optimize_link_incoherent_ht(sysinfo);
needs_reset |= mcp55_early_setup_x();
/*
* FIDVID change will issue one LDTSTOP and the HT change will be
* effective too.
*/
if (needs_reset) {
printk(BIOS_INFO, "ht reset -\n");
soft_reset();
}
allow_all_aps_stop(bsp_apicid);
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
enable_smbus();
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
/* BSP switch stack to RAM and copy sysinfo RAM now. */
post_cache_as_ram();
}
void mainboard_romstage_entry(unsigned long bist)
{
struct pei_data pei_data = {
.pei_version = PEI_VERSION,
.mchbar = (uintptr_t)DEFAULT_MCHBAR,
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = DEFAULT_PCIEXBAR,
.smbusbar = SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = HPET_ADDR,
.rcba = (uintptr_t)DEFAULT_RCBA,
.pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE,
.temp_mmio_base = 0xfed08000,
.system_type = 5, /* ULT */
.tseg_size = CONFIG_SMM_TSEG_SIZE,
.spd_addresses = { 0xa0, 0x00, 0xa4, 0x00 },
.ec_present = 0,
// 0 = leave channel enabled
// 1 = disable dimm 0 on channel
// 2 = disable dimm 1 on channel
// 3 = disable dimm 0+1 on channel
.dimm_channel0_disabled = 2,
.dimm_channel1_disabled = 2,
// Enable 2x refresh mode
.ddr_refresh_2x = 1,
.dq_pins_interleaved = 1,
.max_ddr3_freq = 1600,
.usb_xhci_on_resume = 1,
.usb2_ports = {
/* Length, Enable, OCn#, Location */
{ 0x0064, 1, 0, /* P0: VP8 */
USB_PORT_MINI_PCIE },
{ 0x0040, 1, 0, /* P1: Port A, CN22 */
USB_PORT_INTERNAL },
{ 0x0040, 1, 1, /* P2: Port B, CN23 */
USB_PORT_INTERNAL },
{ 0x0040, 1, USB_OC_PIN_SKIP, /* P3: WLAN */
USB_PORT_INTERNAL },
{ 0x0040, 1, 2, /* P4: Port C, CN25 */
USB_PORT_INTERNAL },
{ 0x0040, 1, 2, /* P5: Port D, CN25 */
USB_PORT_INTERNAL },
{ 0x0040, 1, USB_OC_PIN_SKIP, /* P6: Card Reader */
USB_PORT_INTERNAL },
{ 0x0000, 0, 0, /* P7: N/C */
USB_PORT_SKIP },
},
.usb3_ports = {
/* Enable, OCn# */
{ 1, 0 }, /* P1; CN22 */
{ 1, 1 }, /* P2; CN23 */
{ 1, 2 }, /* P3; CN25 */
{ 1, 2 }, /* P4; CN25 */
},
};
struct romstage_params romstage_params = {
.pei_data = &pei_data,
.gpio_map = &mainboard_gpio_map,
.rcba_config = &rcba_config[0],
.bist = bist,
};
/* Early SuperIO setup */
ite_kill_watchdog(IT8772F_GPIO_DEV);
it8772f_ac_resume_southbridge(IT8772F_DUMMY_DEV);
pch_enable_lpc();
ite_enable_serial(IT8772F_SERIAL_DEV, CONFIG_TTYS0_BASE);
/* Turn on Power LED GP22 for Tricky */
it8772f_gpio_led(IT8772F_GPIO_DEV, 2 /* set */, 0xF7 /* select */,
0x04 /* polarity: inverting */, 0x00 /* 0=pulldown */,
0x04 /* output */, 0x04 /* 1=Simple IO function */,
SIO_GPIO_BLINK_GPIO22, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ);
/* Call into the real romstage main with this board's attributes. */
romstage_common(&romstage_params);
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
u8 byte;
device_t dev;
#if IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE)
hudson_pci_port80();
#endif
#if IS_ENABLED(CONFIG_POST_DEVICE_LPC)
hudson_lpc_port80();
#endif
val = agesawrapper_amdinitmmio();
if (!cpu_init_detectedx && boot_cpu()) {
/* enable SIO LPC decode */
dev = PCI_DEV(0, 0x14, 3);
byte = pci_read_config8(dev, 0x48);
byte |= 3; /* 2e, 2f */
pci_write_config8(dev, 0x48, byte);
/* enable serial decode */
byte = pci_read_config8(dev, 0x44);
byte |= (1 << 6); /* 0x3f8 */
pci_write_config8(dev, 0x44, byte);
post_code(0x30);
/* enable SB MMIO space */
outb(0x24, 0xcd6);
outb(0x1, 0xcd7);
/* enable SIO clock */
sbxxx_enable_48mhzout();
ite_kill_watchdog(GPIO_DEV);
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
ite_enable_3vsbsw(GPIO_DEV);
console_init();
/* turn on secondary smbus at b20 */
outb(0x28, 0xcd6);
byte = inb(0xcd7);
byte |= 1;
outb(byte, 0xcd7);
/* set DDR3 voltage */
byte = CONFIG_BOARD_ASUS_F2A85_M_DDR3_VOLT_VAL;
/* default is byte = 0x0, so no need to set it in this case */
if (byte)
do_smbus_write_byte(0xb20, 0x15, 0x3, byte);
}
/* Halt if there was a built in self test failure */
post_code(0x34);
report_bist_failure(bist);
/* Load MPB */
val = cpuid_eax(1);
printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
post_code(0x37);
printk(BIOS_DEBUG, "agesawrapper_amdinitreset ");
val = agesawrapper_amdinitreset();
if(val) {
printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val);
}
post_code(0x39);
val = agesawrapper_amdinitearly ();
if(val) {
printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val);
}
printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n");
int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed();
if (!s3resume) {
post_code(0x40);
val = agesawrapper_amdinitpost ();
if(val) {
printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val);
}
printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n");
post_code(0x41);
val = agesawrapper_amdinitenv ();
if(val) {
printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val);
}
printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n");
disable_cache_as_ram();
} else { /* S3 detect */
printk(BIOS_INFO, "S3 detected\n");
post_code(0x60);
printk(BIOS_DEBUG, "agesawrapper_amdinitresume ");
val = agesawrapper_amdinitresume();
if (val)
printk(BIOS_DEBUG, "error level: %x \n", val);
else
printk(BIOS_DEBUG, "passed.\n");
printk(BIOS_DEBUG, "agesawrapper_amds3laterestore ");
val = agesawrapper_amds3laterestore ();
if (val)
printk(BIOS_DEBUG, "error level: %x \n", val);
else
printk(BIOS_DEBUG, "passed.\n");
post_code(0x61);
prepare_for_resume();
}
post_code(0x50);
copy_and_run();
post_code(0x54); /* Should never see this post code. */
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
struct sys_info *sysinfo = &sysinfo_car;
static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
u32 bsp_apicid = 0, val;
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
/* mov bsp to bus 0xff when > 8 nodes */
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
sb7xx_51xx_pci_port80();
}
post_code(0x30);
if (bist == 0) {
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */
/* All cores run this but the BSP(node0,core0) is the only core that returns. */
}
post_code(0x32);
enable_rs780_dev8();
sb7xx_51xx_lpc_init();
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
ite_kill_watchdog(GPIO_DEV);
console_init();
// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
// Load MPB
val = cpuid_eax(1);
printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid);
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
update_microcode(val);
post_code(0x33);
cpuSetAMDMSR();
post_code(0x34);
amd_ht_init(sysinfo);
post_code(0x35);
/* Setup nodes PCI space and start core 0 AP init. */
finalize_node_setup(sysinfo);
/* Setup any mainboard PCI settings etc. */
setup_mb_resource_map();
post_code(0x36);
/* wait for all the APs core0 started by finalize_node_setup. */
/* FIXME: A bunch of cores are going to start output to serial at once.
It would be nice to fixup prink spinlocks for ROM XIP mode.
I think it could be done by putting the spinlock flag in the cache
of the BSP located right after sysinfo.
*/
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores();
post_code(0x37);
wait_all_other_cores_started(bsp_apicid);
#endif
post_code(0x38);
/* run _early_setup before soft-reset. */
rs780_early_setup();
sb7xx_51xx_early_setup();
#if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
/* FIXME: The sb fid change may survive the warm reset and only
need to be done once.*/
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
post_code(0x39);
if (!warm_reset_detect(0)) { // BSP is node 0
init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
} else {
init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
}
post_code(0x3A);
/* show final fid and vid */
msr=rdmsr(0xc0010071);
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
#endif
rs780_htinit();
/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
if (!warm_reset_detect(0)) {
print_info("...WARM RESET...\n\n\n");
soft_reset();
die("After soft_reset_x - shouldn't see this message!!!\n");
}
post_code(0x3B);
/* It's the time to set ctrl in sysinfo now; */
printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
post_code(0x40);
// die("Die Before MCT init.");
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
post_code(0x41);
/*
dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200);
dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
*/
// die("After MCT init before CAR disabled.");
rs780_before_pci_init();
sb7xx_51xx_before_pci_init();
post_code(0x42);
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
u8 byte;
device_t dev;
#if IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE)
hudson_pci_port80();
#endif
#if IS_ENABLED(CONFIG_POST_DEVICE_LPC)
hudson_lpc_port80();
#endif
#if CONFIG_HAVE_ACPI_RESUME
void *resume_backup_memory;
#endif
val = agesawrapper_amdinitmmio();
if (!cpu_init_detectedx && boot_cpu()) {
/* enable SIO LPC decode */
dev = PCI_DEV(0, 0x14, 3);
byte = pci_read_config8(dev, 0x48);
byte |= 3; /* 2e, 2f */
pci_write_config8(dev, 0x48, byte);
/* enable serial decode */
byte = pci_read_config8(dev, 0x44);
byte |= (1 << 6); /* 0x3f8 */
pci_write_config8(dev, 0x44, byte);
post_code(0x30);
/* enable SB MMIO space */
outb(0x24, 0xcd6);
outb(0x1, 0xcd7);
/* enable SIO clock */
sbxxx_enable_48mhzout();
ite_kill_watchdog(GPIO_DEV);
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
ite_enable_3vsbsw(GPIO_DEV);
console_init();
/* turn on secondary smbus at b20 */
outb(0x28, 0xcd6);
byte = inb(0xcd7);
byte |= 1;
outb(byte, 0xcd7);
/* set DDR3 voltage */
byte = CONFIG_BOARD_ASUS_F2A85_M_DDR3_VOLT_VAL;
/* default is byte = 0x0, so no need to set it in this case */
if (byte)
do_smbus_write_byte(0xb20, 0x15, 0x3, byte);
}
/* Halt if there was a built in self test failure */
post_code(0x34);
report_bist_failure(bist);
/* Load MPB */
val = cpuid_eax(1);
printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
post_code(0x37);
printk(BIOS_DEBUG, "agesawrapper_amdinitreset ");
val = agesawrapper_amdinitreset();
if(val) {
printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val);
}
post_code(0x39);
val = agesawrapper_amdinitearly ();
if(val) {
printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val);
}
printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n");
#if CONFIG_HAVE_ACPI_RESUME
if (!acpi_is_wakeup_early()) { /* Check for S3 resume */
#endif
post_code(0x40);
val = agesawrapper_amdinitpost ();
if(val) {
printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val);
}
printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n");
post_code(0x41);
val = agesawrapper_amdinitenv ();
if(val) {
printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val);
}
printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n");
disable_cache_as_ram();
#if CONFIG_HAVE_ACPI_RESUME
} else { /* S3 detect */
printk(BIOS_INFO, "S3 detected\n");
post_code(0x60);
printk(BIOS_DEBUG, "agesawrapper_amdinitresume ");
val = agesawrapper_amdinitresume();
if (val)
printk(BIOS_DEBUG, "error level: %x \n", val);
else
printk(BIOS_DEBUG, "passed.\n");
printk(BIOS_DEBUG, "agesawrapper_amds3laterestore ");
val = agesawrapper_amds3laterestore ();
if (val)
printk(BIOS_DEBUG, "error level: %x \n", val);
else
printk(BIOS_DEBUG, "passed.\n");
post_code(0x61);
printk(BIOS_DEBUG, "Find resume memory location\n");
resume_backup_memory = (void *)backup_resume();
post_code(0x62);
printk(BIOS_DEBUG, "Move CAR stack.\n");
move_stack_high_mem();
printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE));
post_code(0x63);
disable_cache_as_ram();
printk(BIOS_DEBUG, "CAR disabled.\n");
set_resume_cache();
/*
* Copy the system memory that is in the ramstage area to the
* reserved area.
*/
if (resume_backup_memory)
memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE);
printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n");
}
#endif
post_code(0x50);
copy_and_run();
post_code(0x54); /* Should never see this post code. */
}
