/** * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB * @adapter: board private structure to initialize * * Cache the descriptor ring offsets for DCB to the assigned rings. * **/ static bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter) { struct net_device *dev = adapter->netdev; unsigned int tx_idx, rx_idx; int tc, offset, rss_i, i; u8 num_tcs = netdev_get_num_tc(dev); /* verify we have DCB queueing enabled before proceeding */ if (num_tcs <= 1) return false; rss_i = adapter->ring_feature[RING_F_RSS].indices; for (tc = 0, offset = 0; tc < num_tcs; tc++, offset += rss_i) { ixgbe_get_first_reg_idx(adapter, tc, &tx_idx, &rx_idx); for (i = 0; i < rss_i; i++, tx_idx++, rx_idx++) { adapter->tx_ring[offset + i]->reg_idx = tx_idx; adapter->rx_ring[offset + i]->reg_idx = rx_idx; adapter->tx_ring[offset + i]->dcb_tc = tc; adapter->rx_ring[offset + i]->dcb_tc = tc; } } return true; }
/** * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB * @adapter: board private structure to initialize * * Cache the descriptor ring offsets for DCB to the assigned rings. * **/ static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter) { struct net_device *dev = adapter->netdev; int i, j, k; u8 num_tcs = netdev_get_num_tc(dev); if (!num_tcs) return false; for (i = 0, k = 0; i < num_tcs; i++) { unsigned int tx_s, rx_s; u16 count = dev->tc_to_txq[i].count; ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s); for (j = 0; j < count; j++, k++) { adapter->tx_ring[k]->reg_idx = tx_s + j; adapter->rx_ring[k]->reg_idx = rx_s + j; adapter->tx_ring[k]->dcb_tc = i; adapter->rx_ring[k]->dcb_tc = i; } } return true; }