HISAX_INITFUNC(void initjade(struct IsdnCardState *cs)) { cs->bcs[0].BC_SetStack = setstack_jade; cs->bcs[1].BC_SetStack = setstack_jade; cs->bcs[0].BC_Close = close_jadestate; cs->bcs[1].BC_Close = close_jadestate; cs->bcs[0].hw.hscx.hscx = 0; cs->bcs[1].hw.hscx.hscx = 1; /* Stop DSP audio tx/rx */ jade_write_indirect(cs, 0x11, 0x0f); jade_write_indirect(cs, 0x17, 0x2f); /* Transparent Mode, RxTx inactive, No Test, No RFS/TFS */ cs->BC_Write_Reg(cs, 0, jade_HDLC_MODE, jadeMODE_TMO); cs->BC_Write_Reg(cs, 1, jade_HDLC_MODE, jadeMODE_TMO); /* Power down, 1-Idle, RxTx least significant bit first */ cs->BC_Write_Reg(cs, 0, jade_HDLC_CCR0, 0x00); cs->BC_Write_Reg(cs, 1, jade_HDLC_CCR0, 0x00); /* Mask all interrupts */ cs->BC_Write_Reg(cs, 0, jade_HDLC_IMR, 0x00); cs->BC_Write_Reg(cs, 1, jade_HDLC_IMR, 0x00); /* Setup host access to hdlc controller */ jade_write_indirect(cs, jade_HDLCCNTRACCESS, (jadeINDIRECT_HAH1|jadeINDIRECT_HAH2)); /* Unmask HDLC int (don´t forget DSP int later on)*/ cs->BC_Write_Reg(cs, -1,jade_INT, (jadeINT_HDLC1|jadeINT_HDLC2)); /* once again TRANSPARENT */ modejade(cs->bcs, 0, 0); modejade(cs->bcs + 1, 0, 0); }
void initjade(struct IsdnCardState *cs) { cs->bcs[0].BC_SetStack = setstack_jade; cs->bcs[1].BC_SetStack = setstack_jade; cs->bcs[0].BC_Close = close_jadestate; cs->bcs[1].BC_Close = close_jadestate; cs->bcs[0].hw.hscx.hscx = 0; cs->bcs[1].hw.hscx.hscx = 1; jade_write_indirect(cs, 0x11, 0x0f); jade_write_indirect(cs, 0x17, 0x2f); cs->BC_Write_Reg(cs, 0, jade_HDLC_MODE, jadeMODE_TMO); cs->BC_Write_Reg(cs, 1, jade_HDLC_MODE, jadeMODE_TMO); cs->BC_Write_Reg(cs, 0, jade_HDLC_CCR0, 0x00); cs->BC_Write_Reg(cs, 1, jade_HDLC_CCR0, 0x00); cs->BC_Write_Reg(cs, 0, jade_HDLC_IMR, 0x00); cs->BC_Write_Reg(cs, 1, jade_HDLC_IMR, 0x00); jade_write_indirect(cs, jade_HDLCCNTRACCESS, (jadeINDIRECT_HAH1|jadeINDIRECT_HAH2)); cs->BC_Write_Reg(cs, -1,jade_INT, (jadeINT_HDLC1|jadeINT_HDLC2)); modejade(cs->bcs, 0, 0); modejade(cs->bcs + 1, 0, 0); }
void modejade(struct BCState *bcs, int mode, int bc) { struct IsdnCardState *cs = bcs->cs; int jade = bcs->hw.hscx.hscx; if (cs->debug & L1_DEB_HSCX) { char tmp[40]; sprintf(tmp, "jade %c mode %d ichan %d", 'A' + jade, mode, bc); debugl1(cs, tmp); } bcs->mode = mode; bcs->channel = bc; cs->BC_Write_Reg(cs, jade, jade_HDLC_MODE, (mode == L1_MODE_TRANS ? jadeMODE_TMO:0x00)); cs->BC_Write_Reg(cs, jade, jade_HDLC_CCR0, (jadeCCR0_PU|jadeCCR0_ITF)); cs->BC_Write_Reg(cs, jade, jade_HDLC_CCR1, 0x00); jade_write_indirect(cs, jade_HDLC1SERRXPATH, 0x08); jade_write_indirect(cs, jade_HDLC2SERRXPATH, 0x08); jade_write_indirect(cs, jade_HDLC1SERTXPATH, 0x00); jade_write_indirect(cs, jade_HDLC2SERTXPATH, 0x00); cs->BC_Write_Reg(cs, jade, jade_HDLC_XCCR, 0x07); cs->BC_Write_Reg(cs, jade, jade_HDLC_RCCR, 0x07); if (bc == 0) { cs->BC_Write_Reg(cs, jade, jade_HDLC_TSAX, 0x00); cs->BC_Write_Reg(cs, jade, jade_HDLC_TSAR, 0x00); } else { cs->BC_Write_Reg(cs, jade, jade_HDLC_TSAX, 0x04); cs->BC_Write_Reg(cs, jade, jade_HDLC_TSAR, 0x04); } switch (mode) { case (L1_MODE_NULL): cs->BC_Write_Reg(cs, jade, jade_HDLC_MODE, jadeMODE_TMO); break; case (L1_MODE_TRANS): cs->BC_Write_Reg(cs, jade, jade_HDLC_MODE, (jadeMODE_TMO|jadeMODE_RAC|jadeMODE_XAC)); break; case (L1_MODE_HDLC): cs->BC_Write_Reg(cs, jade, jade_HDLC_MODE, (jadeMODE_RAC|jadeMODE_XAC)); break; } if (mode) { cs->BC_Write_Reg(cs, jade, jade_HDLC_RCMD, (jadeRCMD_RRES|jadeRCMD_RMC)); cs->BC_Write_Reg(cs, jade, jade_HDLC_XCMD, jadeXCMD_XRES); /* Unmask ints */ cs->BC_Write_Reg(cs, jade, jade_HDLC_IMR, 0xF8); } else /* Mask ints */ cs->BC_Write_Reg(cs, jade, jade_HDLC_IMR, 0x00); }