/* * Main initialization routine */ void board_nand_init(struct nand_chip *nand) { jz_device_setup(); if (CFG_NAND_BCH_BIT == 8) { par_size = 26; nand->eccmode = NAND_ECC_HW13_512; } else { par_size = 13; nand->eccmode = NAND_ECC_HW7_512; } nand->hwcontrol = jz_hwcontrol; nand->dev_ready = jz_device_ready; nand->correct_data = jzsoc_nand_bch_correct_data; nand->enable_hwecc = jzsoc_nand_enable_bch_hwecc; nand->calculate_ecc = jzsoc_nand_calculate_bch_ecc; /* Set address of NAND IO lines */ nand->IO_ADDR_R = (void __iomem *) CFG_NAND_BASE; nand->IO_ADDR_W = (void __iomem *) CFG_NAND_BASE; /* 20 us command delay time */ nand->chip_delay = 20; // nand->autooob = &nand_oob_bch; // init in nand_base.c nand->options &= ~NAND_BUSWIDTH_16; #if CFG_NAND_BW8 == 0 nand->options |= NAND_BUSWIDTH_16; #endif }
/* * Main initialization routine */ void board_nand_init(struct nand_chip *nand) { if ((REG_NEMC_BCR & NEMC_BCR_BSR_MASK) == NEMC_BCR_BSR_SHARE) share_mode = 1; else share_mode = 0; jz_device_setup(); if (CFG_NAND_BCH_BIT == 8) { par_size = 13; nand->eccmode = NAND_ECC_HW13_512; } else { par_size = 7; nand->eccmode = NAND_ECC_HW7_512; } nand->hwcontrol = jz_hwcontrol; nand->dev_ready = jz_device_ready; nand->correct_data = jzsoc_nand_bch_correct_data; nand->enable_hwecc = jzsoc_nand_enable_bch_hwecc; nand->calculate_ecc = jzsoc_nand_calculate_bch_ecc; /* Set address of NAND IO lines */ nand->IO_ADDR_R = (void __iomem *) CFG_NAND_BASE; nand->IO_ADDR_W = (void __iomem *) CFG_NAND_BASE; /* 20 us command delay time */ nand->chip_delay = 20; // nand->autooob = &nand_oob_bch; // init in nand_base.c }
/* * Main initialization routine */ void board_nand_init(struct nand_chip *nand) { jz_device_setup(); nand->eccmode = NAND_ECC_SOFT; nand->hwcontrol = jz_hwcontrol; nand->dev_ready = jz_device_ready; /* Set address of NAND IO lines */ nand->IO_ADDR_R = (void __iomem *) CFG_NAND_BASE; nand->IO_ADDR_W = (void __iomem *) CFG_NAND_BASE; /* 20 us command delay time */ nand->chip_delay = 20; }
/* * Main initialization routine */ void board_nand_init(struct nand_chip *nand) { jz_device_setup(); nand->ecc.mode = NAND_ECC_NONE; /* FIXME: should use NAND_ECC_SOFT */ nand->cmd_ctrl = jz_hwcontrol; nand->dev_ready = jz_device_ready; /* Set address of NAND IO lines */ nand->IO_ADDR_R = (void __iomem *) CONFIG_SYS_NAND_BASE; nand->IO_ADDR_W = (void __iomem *) CONFIG_SYS_NAND_BASE; /* 20 us command delay time */ nand->chip_delay = 20; }