static void set_scancode(uint8_t s) { keyboard_host_write(I8042_CMD_SSCANSET, 0); msleep(30); keyboard_host_write(s, 0); msleep(30); }
static void write_cmd_byte(uint8_t val) { keyboard_host_write(I8042_WRITE_CMD_BYTE, 1); msleep(30); keyboard_host_write(val, 0); msleep(30); }
static void set_typematic(uint8_t val) { keyboard_host_write(I8042_CMD_SETREP, 0); msleep(30); keyboard_host_write(val, 0); msleep(30); }
void kb_ibf_interrupt(void) { if (lpc_keyboard_input_pending()) keyboard_host_write(MEC1322_8042_H2E, MEC1322_8042_STS & (1 << 3)); task_wake(TASK_ID_KEYPROTO); }
static uint8_t read_cmd_byte(void) { lpc_char_cnt = 0; keyboard_host_write(I8042_READ_CMD_BYTE, 1); msleep(30); return lpc_char_buf[0]; }
void lpc_kbc_ibf_interrupt(void) { #ifdef CONFIG_KEYBOARD_PROTOCOL_8042 /* If "command" input 0, else 1*/ keyboard_host_write(NPCX_HIKMDI, (NPCX_HIKMST & 0x08) ? 1 : 0); #endif }
/* KB controller input buffer full ISR */ void lpc_kbc_ibf_interrupt(void) { /* If "command" input 0, else 1*/ if (lpc_keyboard_input_pending()) keyboard_host_write(NPCX_HIKMDI, (NPCX_HIKMST & 0x08) ? 1 : 0); CPRINTS("ibf isr %02x", NPCX_HIKMDI); task_wake(TASK_ID_KEYPROTO); }
/* KBC and PMC control modules */ void lpc_kbc_ibf_interrupt(void) { if (lpc_keyboard_input_pending()) { keyboard_host_write(IT83XX_KBC_KBHIDIR, (IT83XX_KBC_KBHISR & 0x08) ? 1 : 0); } task_clear_pending_irq(IT83XX_IRQ_KBC_IN); #ifdef HAS_TASK_KEYPROTO task_wake(TASK_ID_KEYPROTO); #endif }
static void reset_8042(void) { keyboard_host_write(I8042_CMD_RESET_DEF, 0); msleep(30); }
static void enable_keystroke(int enabled) { uint8_t data = enabled ? I8042_CMD_ENABLE : I8042_CMD_RESET_DIS; keyboard_host_write(data, 0); msleep(30); }
/** * LPC interrupt handler */ void lpc_interrupt(void) { uint32_t mis = LM4_LPC_LPCMIS; uint32_t st; /* Clear the interrupt bits we're handling */ LM4_LPC_LPCIC = mis; #ifdef HAS_TASK_HOSTCMD /* Handle ACPI command and data writes */ st = LM4_LPC_ST(LPC_CH_ACPI); if (st & LM4_LPC_ST_FRMH) handle_acpi_write(st & LM4_LPC_ST_CMD); /* Handle user command writes */ st = LM4_LPC_ST(LPC_CH_CMD); if (st & LM4_LPC_ST_FRMH) handle_host_write(st & LM4_LPC_ST_CMD); #endif /* * Handle port 80 writes (CH0MIS1). Due to crosbug.com/p/12349 the * interrupt status (mis & LM4_LPC_INT_MASK(LPC_CH_PORT80, 2)) * apparently gets lost on back-to-back writes to port 80, so check the * FRMH bit in the channel status register to see if a write is * pending. Loop to handle bursts of back-to-back writes. */ while (LM4_LPC_ST(LPC_CH_PORT80) & LM4_LPC_ST_FRMH) port_80_write(LPC_POOL_PORT80[0]); #ifdef HAS_TASK_KEYPROTO /* Handle keyboard interface writes */ st = LM4_LPC_ST(LPC_CH_KEYBOARD); if (st & LM4_LPC_ST_FRMH) keyboard_host_write(LPC_POOL_KEYBOARD[0], st & LM4_LPC_ST_CMD); if (mis & LM4_LPC_INT_MASK(LPC_CH_KEYBOARD, 1)) { /* Host read data; wake up task to send remaining bytes */ task_wake(TASK_ID_KEYPROTO); } #endif #ifdef CONFIG_UART_HOST /* Handle COMx */ if (lpc_comx_has_char()) { /* Copy a character to the UART if there's space */ if (uart_comx_putc_ok()) uart_comx_putc(lpc_comx_get_char()); } #endif /* Debugging: print changes to LPC0RESET */ if (mis & (1 << 31)) { if (LM4_LPC_LPCSTS & (1 << 10)) { int i; /* Store port 80 reset event */ port_80_write(PORT_80_EVENT_RESET); /* * Workaround for crosbug.com/p/12349; clear all FRMH * bits so host writes will trigger interrupts. */ for (i = 0; i < 8; i++) LM4_LPC_ST(i) &= ~LM4_LPC_ST_FRMH; } CPRINTS("LPC RESET# %sasserted", lpc_get_pltrst_asserted() ? "" : "de"); } }