/** * keystone_timer_config: configures timer to work in oneshot/periodic modes. * @ mask: mask of the mode to configure * @ period: cycles number to configure for */ static int keystone_timer_config(u64 period, int mask) { u32 tcr; u32 off; tcr = keystone_timer_readl(TCR); off = tcr & ~(TCR_ENAMODE_MASK); /* set enable mode */ tcr |= mask; /* disable timer */ keystone_timer_writel(off, TCR); /* here we have to be sure the timer has been disabled */ keystone_timer_barrier(); /* reset counter to zero, set new period */ keystone_timer_writel(0, TIM12); keystone_timer_writel(0, TIM34); keystone_timer_writel(period & 0xffffffff, PRD12); keystone_timer_writel(period >> 32, PRD34); /* * enable timer * here we have to be sure that CNTLO, CNTHI, PRDLO, PRDHI registers * have been written. */ keystone_timer_barrier(); keystone_timer_writel(tcr, TCR); return 0; }
static void keystone_timer_disable(void) { u32 tcr; tcr = keystone_timer_readl(TCR); /* disable timer */ tcr &= ~(TCR_ENAMODE_MASK); keystone_timer_writel(tcr, TCR); }
/** * keystone_timer_config: configures timer to work in oneshot/periodic modes. * @ mode: mode to configure * @ period: cycles number to configure for */ static int keystone_timer_config(u64 period, enum clock_event_mode mode) { u32 tcr; u32 off; tcr = keystone_timer_readl(TCR); off = tcr & ~(TCR_ENAMODE_MASK); /* set enable mode */ switch (mode) { case CLOCK_EVT_MODE_ONESHOT: tcr |= TCR_ENAMODE_ONESHOT_MASK; break; case CLOCK_EVT_MODE_PERIODIC: tcr |= TCR_ENAMODE_PERIODIC_MASK; break; default: return -1; } /* disable timer */ keystone_timer_writel(off, TCR); /* here we have to be sure the timer has been disabled */ keystone_timer_barrier(); /* reset counter to zero, set new period */ keystone_timer_writel(0, TIM12); keystone_timer_writel(0, TIM34); keystone_timer_writel(period & 0xffffffff, PRD12); keystone_timer_writel(period >> 32, PRD34); /* * enable timer * here we have to be sure that CNTLO, CNTHI, PRDLO, PRDHI registers * have been written. */ keystone_timer_barrier(); keystone_timer_writel(tcr, TCR); return 0; }
static void __init keystone_timer_init(struct device_node *np) { struct clock_event_device *event_dev = &timer.event_dev; unsigned long rate; struct clk *clk; int irq, error; irq = irq_of_parse_and_map(np, 0); if (irq == NO_IRQ) { pr_err("%s: failed to map interrupts\n", __func__); return; } timer.base = of_iomap(np, 0); if (!timer.base) { pr_err("%s: failed to map registers\n", __func__); return; } clk = of_clk_get(np, 0); if (IS_ERR(clk)) { pr_err("%s: failed to get clock\n", __func__); iounmap(timer.base); return; } error = clk_prepare_enable(clk); if (error) { pr_err("%s: failed to enable clock\n", __func__); goto err; } rate = clk_get_rate(clk); /* disable, use internal clock source */ keystone_timer_writel(0, TCR); /* here we have to be sure the timer has been disabled */ keystone_timer_barrier(); /* reset timer as 64-bit, no pre-scaler, plus features are disabled */ keystone_timer_writel(0, TGCR); /* unreset timer */ keystone_timer_writel(TGCR_TIM_UNRESET_MASK, TGCR); /* init counter to zero */ keystone_timer_writel(0, TIM12); keystone_timer_writel(0, TIM34); timer.hz_period = DIV_ROUND_UP(rate, HZ); /* enable timer interrupts */ keystone_timer_writel(INTCTLSTAT_ENINT_MASK, INTCTLSTAT); error = request_irq(irq, keystone_timer_interrupt, IRQF_TIMER, TIMER_NAME, event_dev); if (error) { pr_err("%s: failed to setup irq\n", __func__); goto err; } /* setup clockevent */ event_dev->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; event_dev->set_next_event = keystone_set_next_event; event_dev->set_mode = keystone_set_mode; event_dev->cpumask = cpu_all_mask; event_dev->owner = THIS_MODULE; event_dev->name = TIMER_NAME; event_dev->irq = irq; clockevents_config_and_register(event_dev, rate, 1, ULONG_MAX); pr_info("keystone timer clock @%lu Hz\n", rate); return; err: clk_put(clk); iounmap(timer.base); }