void kw2xrf_reset_phy(kw2xrf_t *dev) { netdev_ieee802154_reset(&dev->netdev); dev->tx_power = KW2XRF_DEFAULT_TX_POWER; kw2xrf_set_tx_power(dev, dev->tx_power); kw2xrf_set_channel(dev, KW2XRF_DEFAULT_CHANNEL); kw2xrf_set_pan(dev, KW2XRF_DEFAULT_PANID); kw2xrf_set_address(dev); kw2xrf_set_cca_mode(dev, 1); kw2xrf_set_rx_watermark(dev, 1); kw2xrf_set_option(dev, KW2XRF_OPT_AUTOACK, true); kw2xrf_set_option(dev, KW2XRF_OPT_ACK_REQ, true); kw2xrf_set_option(dev, KW2XRF_OPT_AUTOCCA, true); kw2xrf_set_power_mode(dev, KW2XRF_AUTODOZE); kw2xrf_set_sequence(dev, dev->idle_state); kw2xrf_clear_dreg_bit(dev, MKW2XDM_PHY_CTRL2, MKW2XDM_PHY_CTRL2_SEQMSK); kw2xrf_enable_irq_b(dev); DEBUG("[kw2xrf] init phy and (re)set to channel %d and pan %d.\n", KW2XRF_DEFAULT_CHANNEL, KW2XRF_DEFAULT_PANID); }
void kw2xrf_seq_timeout_on(kw2xrf_t *dev, uint32_t timeout) { kw2xrf_mask_irq_b(dev); kw2xrf_timer_set(dev, MKW2XDM_T4CMP_LSB, timeout); /* enable and clear irq for timer 3 */ uint8_t irqsts3 = kw2xrf_read_dreg(dev, MKW2XDM_IRQSTS3) & 0xf0; irqsts3 &= ~MKW2XDM_IRQSTS3_TMR4MSK; irqsts3 |= MKW2XDM_IRQSTS3_TMR4IRQ; kw2xrf_write_dreg(dev, MKW2XDM_IRQSTS3, irqsts3); kw2xrf_set_dreg_bit(dev, MKW2XDM_PHY_CTRL3, MKW2XDM_PHY_CTRL3_TMR4CMP_EN); kw2xrf_enable_irq_b(dev); }
static void _isr(netdev_t *netdev) { uint8_t dregs[MKW2XDM_PHY_CTRL4 + 1]; kw2xrf_t *dev = (kw2xrf_t *)netdev; kw2xrf_read_dregs(dev, MKW2XDM_IRQSTS1, dregs, MKW2XDM_PHY_CTRL4 + 1); kw2xrf_mask_irq_b(dev); DEBUG("[kw2xrf] CTRL1 %0x, IRQSTS1 %0x, IRQSTS2 %0x\n", dregs[MKW2XDM_PHY_CTRL1], dregs[MKW2XDM_IRQSTS1], dregs[MKW2XDM_IRQSTS2]); switch (dregs[MKW2XDM_PHY_CTRL1] & MKW2XDM_PHY_CTRL1_XCVSEQ_MASK) { case XCVSEQ_RECEIVE: _isr_event_seq_r(netdev, dregs); break; case XCVSEQ_TRANSMIT: _isr_event_seq_t(netdev, dregs); break; case XCVSEQ_CCA: _isr_event_seq_cca(netdev, dregs); break; case XCVSEQ_TX_RX: _isr_event_seq_tr(netdev, dregs); break; case XCVSEQ_CONTINUOUS_CCA: _isr_event_seq_ccca(netdev, dregs); break; case XCVSEQ_IDLE: default: DEBUG("[kw2xrf] undefined seq state in isr\n"); break; } uint8_t irqsts2 = 0; if (dregs[MKW2XDM_IRQSTS2] & MKW2XDM_IRQSTS2_PB_ERR_IRQ) { DEBUG("[kw2xrf] untreated PB_ERR_IRQ\n"); irqsts2 |= MKW2XDM_IRQSTS2_PB_ERR_IRQ; } if (dregs[MKW2XDM_IRQSTS2] & MKW2XDM_IRQSTS2_WAKE_IRQ) { DEBUG("[kw2xrf] untreated WAKE_IRQ\n"); irqsts2 |= MKW2XDM_IRQSTS2_WAKE_IRQ; } kw2xrf_write_dreg(dev, MKW2XDM_IRQSTS2, irqsts2); if (ENABLE_DEBUG) { /* for debugging only */ kw2xrf_read_dregs(dev, MKW2XDM_IRQSTS1, dregs, MKW2XDM_IRQSTS1 + 3); if (dregs[MKW2XDM_IRQSTS1] & 0x7f) { DEBUG("[kw2xrf] IRQSTS1 contains untreated IRQs: 0x%02x\n", dregs[MKW2XDM_IRQSTS1]); } if (dregs[MKW2XDM_IRQSTS2] & 0x02) { DEBUG("[kw2xrf] IRQSTS2 contains untreated IRQs: 0x%02x\n", dregs[MKW2XDM_IRQSTS2]); } if (dregs[MKW2XDM_IRQSTS3] & 0x0f) { DEBUG("[kw2xrf] IRQSTS3 contains untreated IRQs: 0x%02x\n", dregs[MKW2XDM_IRQSTS3]); } } kw2xrf_enable_irq_b(dev); }