static int baytrail_init_cpus(void)
{
struct mp_params mp_params;
lapic_setup();
mp_params.num_cpus = detect_num_cpus();
mp_params.parallel_microcode_load = 0,
mp_params.flight_plan = &mp_steps[0];
mp_params.num_records = ARRAY_SIZE(mp_steps);
mp_params.microcode_pointer = 0;
if (mp_init(&mp_params)) {
printf("Warning: MP init failure\n");
return -EIO;
}
return 0;
}
static int init_bsp(struct udevice **devp)
{
char processor_name[CPU_MAX_NAME_LEN];
int apic_id;
int ret;
cpu_get_name(processor_name);
debug("CPU: %s.\n", processor_name);
lapic_setup();
apic_id = lapicid();
ret = find_cpu_by_apid_id(apic_id, devp);
if (ret) {
printf("Cannot find boot CPU, APIC ID %d\n", apic_id);
return ret;
}
return 0;
}
void main_ap(void)
{
// Load the IDT
idt_load((uintptr_t) &idt_data, IDT_LENGTH);
// Enable LAPIC and calibrate the timer
lapic_setup();
lapic_timer_calibrate();
// Setup stack mapping
kernel_map_stack();
// Setup fast syscall support
syscall_init();
// Signal complete AP startup
++smp_ready_count;
// Wait for main entry barrier, then enter the kernel (or halt)
while (main_entry_barrier == 1);
kernel_enter_ap();
}
/*
* AP CPU's call this to initialize themselves.
*/
void
init_secondary(void)
{
vm_offset_t addr;
u_int cpuid;
int gsel_tss;
/* bootAP is set in start_ap() to our ID. */
PCPU_SET(currentldt, _default_ldt);
gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
#if 0
gdt[bootAP * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
#endif
PCPU_SET(common_tss.tss_esp0, 0); /* not used until after switch */
PCPU_SET(common_tss.tss_ss0, GSEL(GDATA_SEL, SEL_KPL));
PCPU_SET(common_tss.tss_ioopt, (sizeof (struct i386tss)) << 16);
#if 0
PCPU_SET(tss_gdt, &gdt[bootAP * NGDT + GPROC0_SEL].sd);
PCPU_SET(common_tssd, *PCPU_GET(tss_gdt));
#endif
PCPU_SET(fsgs_gdt, &gdt[GUFS_SEL].sd);
/*
* Set to a known state:
* Set by mpboot.s: CR0_PG, CR0_PE
* Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
*/
/*
* signal our startup to the BSP.
*/
mp_naps++;
/* Spin until the BSP releases the AP's. */
while (!aps_ready)
ia32_pause();
/* BSP may have changed PTD while we were waiting */
invltlb();
for (addr = 0; addr < NKPT * NBPDR - 1; addr += PAGE_SIZE)
invlpg(addr);
/* set up FPU state on the AP */
npxinit();
#if 0
/* set up SSE registers */
enable_sse();
#endif
#if 0 && defined(PAE)
/* Enable the PTE no-execute bit. */
if ((amd_feature & AMDID_NX) != 0) {
uint64_t msr;
msr = rdmsr(MSR_EFER) | EFER_NXE;
wrmsr(MSR_EFER, msr);
}
#endif
#if 0
/* A quick check from sanity claus */
if (PCPU_GET(apic_id) != lapic_id()) {
printf("SMP: cpuid = %d\n", PCPU_GET(cpuid));
printf("SMP: actual apic_id = %d\n", lapic_id());
printf("SMP: correct apic_id = %d\n", PCPU_GET(apic_id));
panic("cpuid mismatch! boom!!");
}
#endif
/* Initialize curthread. */
KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread"));
PCPU_SET(curthread, PCPU_GET(idlethread));
mtx_lock_spin(&ap_boot_mtx);
#if 0
/* Init local apic for irq's */
lapic_setup(1);
#endif
smp_cpus++;
cpuid = PCPU_GET(cpuid);
CTR1(KTR_SMP, "SMP: AP CPU #%d Launched", cpuid);
printf("SMP: AP CPU #%d Launched!\n", cpuid);
/* Determine if we are a logical CPU. */
if (logical_cpus > 1 && PCPU_GET(apic_id) % logical_cpus != 0)
CPU_SET(cpuid, &logical_cpus_mask);
/* Determine if we are a hyperthread. */
if (hyperthreading_cpus > 1 &&
PCPU_GET(apic_id) % hyperthreading_cpus != 0)
CPU_SET(cpuid, &hyperthreading_cpus_mask);
#if 0
if (bootverbose)
lapic_dump("AP");
#endif
if (smp_cpus == mp_ncpus) {
/* enable IPI's, tlb shootdown, freezes etc */
atomic_store_rel_int(&smp_started, 1);
smp_active = 1; /* historic */
}
mtx_unlock_spin(&ap_boot_mtx);
/* wait until all the AP's are up */
while (smp_started == 0)
ia32_pause();
PCPU_SET(curthread, PCPU_GET(idlethread));
/* Start per-CPU event timers. */
cpu_initclocks_ap();
/* enter the scheduler */
sched_throw(NULL);
panic("scheduler returned us to %s", __func__);
/* NOTREACHED */
}
void main_bsp(void)
{
// Print header
screen_write("Hydrogen v0.2b - http://github.com/farok/H2", 0, 0);
screen_write("Copyright (c) 2012 by Lukas Heidemann", 0, 1);
screen_write("-------------------------------------------------", 0, 2);
// Load the IDT
idt_load(idt_address, IDT_LENGTH);
idt_setup_loader();
// Initialize Hydrogen info tables and parse the multiboot tables
info_init();
multiboot_parse();
// Setup the heap
heap_init();
// Now parse the ACPI tables and analyze the IO APICs
acpi_parse();
ioapic_analyze();
// Find, check and load the kernel binary
kernel_find();
kernel_check();
elf64_load(kernel_binary);
kernel_analyze();
// Initialize interrupt controllers
lapic_detect();
lapic_setup();
ioapic_setup_loader();
pic_setup();
// Calibrate the LAPIC timer
lapic_timer_calibrate();
// Boot APs
info_cpu[lapic_id()].flags |= HY_INFO_CPU_FLAG_BSP;
smp_setup();
// Setup IDT and IOAPIC according to kernel header
idt_setup_kernel();
ioapic_setup_kernel();
// Setup fast syscall support
syscall_init();
// Setup mapping
kernel_map_info();
kernel_map_stack();
kernel_map_idt();
kernel_map_gdt();
// Set free address
info_root->free_paddr = (heap_top + 0xFFF) & ~0xFFF;
// Lower main entry barrier and jump to the kernel entry point
main_entry_barrier = 0;
kernel_enter_bsp();
}
