static int rk3188_lcdc_early_resume(struct rk_lcdc_device_driver *dev_drv)
{
struct rk3188_lcdc_device *lcdc_dev =
container_of(dev_drv,struct rk3188_lcdc_device,driver);
int i=0;
int __iomem *c;
int v;
#ifndef CONFIG_FB_CONSOLE_GALLAND_FIX //Galland to fix FRAMEBUFFER_CONSOLE on rk30 and rk31
if(dev_drv->screen_ctr_info->io_enable) //power on
dev_drv->screen_ctr_info->io_enable();
#endif
if(!lcdc_dev->clk_on)
{
rk3188_lcdc_clk_enable(lcdc_dev);
}
rk3188_lcdc_reg_resume(lcdc_dev); //resume reg
spin_lock(&lcdc_dev->reg_lock);
if(dev_drv->cur_screen->dsp_lut) //resume dsp lut
{
lcdc_msk_reg(lcdc_dev,SYS_CTRL,m_DSP_LUT_EN,v_DSP_LUT_EN(0));
lcdc_cfg_done(lcdc_dev);
mdelay(25);
for(i=0;i<256;i++)
{
v = dev_drv->cur_screen->dsp_lut[i];
c = lcdc_dev->dsp_lut_addr_base+i;
writel_relaxed(v,c);
}
lcdc_msk_reg(lcdc_dev,SYS_CTRL,m_DSP_LUT_EN,v_DSP_LUT_EN(1));
}
if(lcdc_dev->atv_layer_cnt)
{
lcdc_msk_reg(lcdc_dev, SYS_CTRL,m_LCDC_STANDBY,v_LCDC_STANDBY(0));
lcdc_cfg_done(lcdc_dev);
}
spin_unlock(&lcdc_dev->reg_lock);
if(!lcdc_dev->atv_layer_cnt)
rk3188_lcdc_clk_disable(lcdc_dev);
#ifndef CONFIG_FB_CONSOLE_GALLAND_FIX //Galland to fix FRAMEBUFFER_CONSOLE on rk30 and rk31
if(dev_drv->screen0->standby)
dev_drv->screen0->standby(0); //screen wake up
#endif
return 0;
}
int rk_lcdc_init(int lcdc_id)
{
struct lcdc_device *lcdc_dev = &rk32_lcdc;
u32 msk, val;
lcdc_dev->soc_type = gd->arch.chiptype;
lcdc_dev->id = lcdc_id;
#ifdef CONFIG_OF_LIBFDT
if (!lcdc_dev->node)
rk32_lcdc_parse_dt(lcdc_dev, gd->fdt_blob);
#endif
if (lcdc_dev->node <= 0) {
if (lcdc_dev->id == 0)
lcdc_dev->regs = RKIO_VOP_BIG_PHYS;
else
lcdc_dev->regs = RKIO_VOP_LIT_PHYS;
}
grf_writel(1<<16, GRF_IO_VSEL); /*LCDCIOdomain 3.3 Vvoltageselectio*/
msk = m_AUTO_GATING_EN | m_STANDBY_EN |
m_DMA_STOP | m_MMU_EN;
val = v_AUTO_GATING_EN(1) | v_STANDBY_EN(0) |
v_DMA_STOP(0) | v_MMU_EN(0);
lcdc_msk_reg(lcdc_dev, SYS_CTRL, msk, val);
msk = m_DSP_LAYER3_SEL | m_DSP_LAYER2_SEL|
m_DSP_LAYER1_SEL | m_DSP_LAYER0_SEL;
val = v_DSP_LAYER3_SEL(3) | v_DSP_LAYER2_SEL(2) |
v_DSP_LAYER1_SEL(1) | v_DSP_LAYER0_SEL(0);
lcdc_msk_reg(lcdc_dev, DSP_CTRL1, msk, val);
lcdc_cfg_done(lcdc_dev);
return 0;
}
static int win1_open(struct rk30_lcdc_device *lcdc_dev,bool open)
{
spin_lock(&lcdc_dev->reg_lock);
if(likely(lcdc_dev->clk_on))
{
if(open)
{
if(!lcdc_dev->atv_layer_cnt)
{
printk(KERN_INFO "lcdc%d wakeup from standby!\n",lcdc_dev->id);
lcdc_msk_reg(lcdc_dev, SYS_CTRL0,m_LCDC_STANDBY,v_LCDC_STANDBY(0));
}
lcdc_dev->atv_layer_cnt++;
}
else if((lcdc_dev->atv_layer_cnt > 0) && (!open))
{
lcdc_dev->atv_layer_cnt--;
}
lcdc_dev->driver.layer_par[1]->state = open;
lcdc_msk_reg(lcdc_dev, SYS_CTRL1, m_W1_EN, v_W1_EN(open));
if(!lcdc_dev->atv_layer_cnt) //if no layer used,disable lcdc
{
printk(KERN_INFO "no layer of lcdc%d is used,go to standby!\n",lcdc_dev->id);
lcdc_msk_reg(lcdc_dev, SYS_CTRL0,m_LCDC_STANDBY,v_LCDC_STANDBY(1));
}
lcdc_cfg_done(lcdc_dev);
}
spin_unlock(&lcdc_dev->reg_lock);
return 0;
}
static int rk3188_lcdc_early_suspend(struct rk_lcdc_device_driver *dev_drv)
{
struct rk3188_lcdc_device *lcdc_dev =
container_of(dev_drv,struct rk3188_lcdc_device,driver);
#ifndef CONFIG_FB_CONSOLE_GALLAND_FIX //Galland to fix FRAMEBUFFER_CONSOLE on rk30 and rk31
if(dev_drv->screen0->standby)
dev_drv->screen0->standby(1);
if(dev_drv->screen_ctr_info->io_disable)
dev_drv->screen_ctr_info->io_disable();
#endif
spin_lock(&lcdc_dev->reg_lock);
if(likely(lcdc_dev->clk_on))
{
lcdc_msk_reg(lcdc_dev,INT_STATUS,m_FS_INT_CLEAR,v_FS_INT_CLEAR(1));
lcdc_msk_reg(lcdc_dev,SYS_CTRL,m_LCDC_STANDBY,v_LCDC_STANDBY(1));
lcdc_cfg_done(lcdc_dev);
spin_unlock(&lcdc_dev->reg_lock);
}
else //clk already disabled
{
spin_unlock(&lcdc_dev->reg_lock);
return 0;
}
mdelay(25);
rk3188_lcdc_clk_disable(lcdc_dev);
return 0;
}
static int win1_display(struct rk3188_lcdc_device *lcdc_dev,struct layer_par *par )
{
u32 y_addr;
u32 uv_addr;
y_addr = par->smem_start + par->y_offset;
uv_addr = par->cbr_start + par->c_offset;
DBG(2,"lcdc%d>>%s>>y_addr:0x%x>>uv_addr:0x%x\n",lcdc_dev->id,__func__,y_addr,uv_addr);
spin_lock(&lcdc_dev->reg_lock);
if(likely(lcdc_dev->clk_on))
{
lcdc_writel(lcdc_dev,WIN1_MST,y_addr);
// #if defined(CONFIG_RK_HDMI)
// #if defined(CONFIG_DUAL_LCDC_DUAL_DISP_IN_KERNEL)
// if(lcdc_dev->driver.screen_ctr_info->prop == EXTEND)
// {
// if(hdmi_get_hotplug() == HDMI_HPD_ACTIVED)
// {
lcdc_cfg_done(lcdc_dev);
// }
// }
// #endif
// #endif
}
spin_unlock(&lcdc_dev->reg_lock);
return 0;
}
static int rk3188_lcdc_blank(struct rk_lcdc_device_driver *dev_drv,
int layer_id,int blank_mode)
{
struct rk3188_lcdc_device * lcdc_dev =
container_of(dev_drv,struct rk3188_lcdc_device,driver);
spin_lock(&lcdc_dev->reg_lock);
if(likely(lcdc_dev->clk_on))
{
switch(blank_mode)
{
case FB_BLANK_UNBLANK:
lcdc_msk_reg(lcdc_dev,DSP_CTRL1,m_BLANK_EN ,v_BLANK_EN(0));
break;
case FB_BLANK_NORMAL:
lcdc_msk_reg(lcdc_dev,DSP_CTRL1,m_BLANK_EN ,v_BLANK_EN(1));
break;
default:
lcdc_msk_reg(lcdc_dev,DSP_CTRL1,m_BLANK_EN ,v_BLANK_EN(1));
break;
}
lcdc_cfg_done(lcdc_dev);
dev_info(dev_drv->dev,"blank mode:%d\n",blank_mode);
}
spin_unlock(&lcdc_dev->reg_lock);
return 0;
}
static int rk30_lcdc_blank(struct rk_lcdc_device_driver*lcdc_drv,int layer_id,int blank_mode)
{
struct rk30_lcdc_device * lcdc_dev = container_of(lcdc_drv,struct rk30_lcdc_device ,driver);
printk(KERN_INFO "%s>>>>>%d\n",__func__, blank_mode);
spin_lock(&lcdc_dev->reg_lock);
if(likely(lcdc_dev->clk_on))
{
switch(blank_mode)
{
case FB_BLANK_UNBLANK:
lcdc_msk_reg(lcdc_dev,DSP_CTRL1,m_BLANK_MODE ,v_BLANK_MODE(0));
break;
case FB_BLANK_NORMAL:
lcdc_msk_reg(lcdc_dev,DSP_CTRL1,m_BLANK_MODE ,v_BLANK_MODE(1));
break;
default:
lcdc_msk_reg(lcdc_dev,DSP_CTRL1,m_BLANK_MODE ,v_BLANK_MODE(1));
break;
}
lcdc_cfg_done(lcdc_dev);
}
spin_unlock(&lcdc_dev->reg_lock);
return 0;
}
/***********************************
overlay manager
swap:1 win0 on the top of win1
0 win1 on the top of win0
set : 1 set overlay
0 get overlay state
************************************/
static int rk30_lcdc_ovl_mgr(struct rk_lcdc_device_driver *dev_drv,int swap,bool set)
{
struct rk30_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk30_lcdc_device,driver);
int ovl;
spin_lock(&lcdc_dev->reg_lock);
if(lcdc_dev->clk_on)
{
if(set) //set overlay
{
lcdc_msk_reg(lcdc_dev,DSP_CTRL0,m_W0W1_POSITION_SWAP,v_W0W1_POSITION_SWAP(swap));
lcdc_writel(lcdc_dev, REG_CFG_DONE, 0x01);
lcdc_cfg_done(lcdc_dev);
ovl = swap;
}
else //get overlay
{
ovl = lcdc_read_bit(lcdc_dev,DSP_CTRL0,m_W0W1_POSITION_SWAP);
}
}
else
{
ovl = -EPERM;
}
spin_unlock(&lcdc_dev->reg_lock);
return ovl;
}
static int rk3188_lcdc_open(struct rk_lcdc_device_driver *dev_drv,int layer_id,bool open)
{
int i=0;
int __iomem *c;
int v;
struct rk3188_lcdc_device *lcdc_dev =
container_of(dev_drv,struct rk3188_lcdc_device,driver);
if((open) && (!lcdc_dev->atv_layer_cnt)) //enable clk,when first layer open
{
rk3188_lcdc_clk_enable(lcdc_dev);
#ifndef CONFIG_FB_CONSOLE_GALLAND_FIX //Galland to fix FRAMEBUFFER_CONSOLE on rk30 and rk31
rk3188_lcdc_reg_resume(lcdc_dev); //resume reg
rk3188_load_screen(dev_drv,1);
spin_lock(&lcdc_dev->reg_lock);
if(dev_drv->cur_screen->dsp_lut) //resume dsp lut
{
lcdc_msk_reg(lcdc_dev,SYS_CTRL,m_DSP_LUT_EN,v_DSP_LUT_EN(0));
lcdc_cfg_done(lcdc_dev);
mdelay(25); //wait for dsp lut disabled
for(i=0;i<256;i++)
{
v = dev_drv->cur_screen->dsp_lut[i];
c = lcdc_dev->dsp_lut_addr_base+i;
writel_relaxed(v,c);
}
lcdc_msk_reg(lcdc_dev,SYS_CTRL,m_DSP_LUT_EN,v_DSP_LUT_EN(1)); //enable dsp lut
}
spin_unlock(&lcdc_dev->reg_lock);
#endif
}
if(layer_id == 0)
{
win0_open(lcdc_dev,open);
}
else if(layer_id == 1)
{
win1_open(lcdc_dev,open);
}
else
{
printk("invalid win number:%d\n",layer_id);
}
if((!open) && (!lcdc_dev->atv_layer_cnt)) //when all layer closed,disable clk
{
rk3188_lcdc_clk_disable(lcdc_dev);
}
printk(KERN_INFO "lcdc%d win%d %s,atv layer:%d\n",
lcdc_dev->id,layer_id,open?"open":"closed",
lcdc_dev->atv_layer_cnt);
return 0;
}
static int rk30_lcdc_open(struct rk_lcdc_device_driver *dev_drv,int layer_id,bool open)
{
int i=0;
int __iomem *c;
int v;
struct rk30_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk30_lcdc_device,driver);
//printk("%s>>open:%d>>cnt:%d\n",__func__,open,lcdc_dev->atv_layer_cnt);
if((open) && (!lcdc_dev->atv_layer_cnt)) //enable clk,when first layer open
{
rk30_lcdc_clk_enable(lcdc_dev);
memcpy((u8*)lcdc_dev->regs, (u8*)lcdc_dev->regsbak, 0xc4); //resume reg
rk30_load_screen(dev_drv,1);
spin_lock(&lcdc_dev->reg_lock);
if(dev_drv->cur_screen->dsp_lut) //resume dsp lut
{
lcdc_msk_reg(lcdc_dev,SYS_CTRL1,m_DSP_LUT_RAM_EN,v_DSP_LUT_RAM_EN(0));
lcdc_cfg_done(lcdc_dev);
mdelay(25);
for(i=0;i<256;i++)
{
v = dev_drv->cur_screen->dsp_lut[i];
c = lcdc_dev->dsp_lut_addr_base+i;
writel_relaxed(v,c);
}
lcdc_msk_reg(lcdc_dev,SYS_CTRL1,m_DSP_LUT_RAM_EN,v_DSP_LUT_RAM_EN(1));
}
spin_unlock(&lcdc_dev->reg_lock);
}
if(layer_id == 0)
{
win0_open(lcdc_dev,open);
}
else if(layer_id == 1)
{
win1_open(lcdc_dev,open);
}
else if(layer_id == 2)
{
win2_open(lcdc_dev,open);
}
if((!open) && (!lcdc_dev->atv_layer_cnt)) //when all layer closed,disable clk
{
rk30_lcdc_clk_disable(lcdc_dev);
}
printk(KERN_INFO "lcdc%d win%d %s,atv layer:%d\n",
lcdc_dev->id,layer_id,open?"open":"closed",
lcdc_dev->atv_layer_cnt);
return 0;
}
int rk30_lcdc_pan_display(struct rk_lcdc_device_driver * dev_drv,int layer_id)
{
struct rk30_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk30_lcdc_device,driver);
struct layer_par *par = NULL;
rk_screen *screen = dev_drv->cur_screen;
unsigned long flags;
int timeout;
if(!screen)
{
printk(KERN_ERR "screen is null!\n");
return -ENOENT;
}
if(layer_id==0)
{
par = dev_drv->layer_par[0];
win0_display(lcdc_dev,par);
}
else if(layer_id==1)
{
par = dev_drv->layer_par[1];
win1_display(lcdc_dev,par);
}
else if(layer_id == 2)
{
par = dev_drv->layer_par[2];
win2_display(lcdc_dev,par);
}
if((dev_drv->first_frame)) //this is the first frame of the system ,enable frame start interrupt
{
dev_drv->first_frame = 0;
lcdc_msk_reg(lcdc_dev,INT_STATUS,m_FRM_START_INT_CLEAR |m_FRM_START_INT_EN ,
v_FRM_START_INT_CLEAR(1) | v_FRM_START_INT_EN(1));
lcdc_cfg_done(lcdc_dev); // write any value to REG_CFG_DONE let config become effective
}
if(dev_drv->num_buf < 3) //3buffer ,no need to wait for sysn
{
spin_lock_irqsave(&dev_drv->cpl_lock,flags);
init_completion(&dev_drv->frame_done);
spin_unlock_irqrestore(&dev_drv->cpl_lock,flags);
timeout = wait_for_completion_timeout(&dev_drv->frame_done,msecs_to_jiffies(dev_drv->cur_screen->ft+5));
if(!timeout&&(!dev_drv->frame_done.done))
{
printk(KERN_ERR "wait for new frame start time out!\n");
return -ETIMEDOUT;
}
}
return 0;
}
/* Enable LCD and DIGITAL OUT in DSS */
void rk_lcdc_standby(int enable)
{
struct lcdc_device *lcdc_dev = &rk32_lcdc;
#if defined(CONFIG_RK32_DSI)
if (((panel_info.screen_type == SCREEN_MIPI) ||
(panel_info.screen_type == SCREEN_DUAL_MIPI))) {
if (enable == 0) {
rk32_dsi_enable();
rk32_dsi_sync();
} else if (enable == 1) {
rk32_dsi_disable();
}
}
#endif
lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
v_STANDBY_EN(enable ? 1 : 0));
lcdc_cfg_done(lcdc_dev);
}
static int win1_display(struct rk30_lcdc_device *lcdc_dev,struct layer_par *par )
{
u32 y_addr;
u32 uv_addr;
y_addr = par->smem_start + par->y_offset;
uv_addr = par->cbr_start + par->c_offset;
DBG(2,KERN_INFO "lcdc%d>>%s>>y_addr:0x%x>>uv_addr:0x%x\n",lcdc_dev->id,__func__,y_addr,uv_addr);
spin_lock(&lcdc_dev->reg_lock);
if(likely(lcdc_dev->clk_on))
{
lcdc_writel(lcdc_dev, WIN1_YRGB_MST, y_addr);
lcdc_writel(lcdc_dev, WIN1_CBR_MST, uv_addr);
lcdc_cfg_done(lcdc_dev);
}
spin_unlock(&lcdc_dev->reg_lock);
return 0;
}
void rk_lcdc_set_par(struct fb_dsp_info *fb_info, vidinfo_t *vid)
{
struct lcdc_device *lcdc_dev = &rk32_lcdc;
fb_info->layer_id = lcdc_dev->dft_win;
switch (fb_info->layer_id) {
case WIN0:
win0_set_par(lcdc_dev, fb_info, vid);
break;
case WIN1:
printf("%s --->WIN1 not support\n", __func__);
break;
default:
printf("%s --->unknow lay_id \n", __func__);
break;
}
lcdc_writel(lcdc_dev, BCSH_BCS, 0xd0010000);
lcdc_writel(lcdc_dev, BCSH_H, 0x01000000);
lcdc_writel(lcdc_dev, BCSH_COLOR_BAR, 1);
lcdc_cfg_done(lcdc_dev);
}
static int rk3188_lcdc_ioctl(struct rk_lcdc_device_driver *dev_drv, unsigned int cmd,unsigned long arg,int layer_id)
{
struct rk3188_lcdc_device *lcdc_dev =
container_of(dev_drv,struct rk3188_lcdc_device,driver);
u32 panel_size[2];
void __user *argp = (void __user *)arg;
int enable;
unsigned long flags;
int timeout;
switch(cmd)
{
case RK_FBIOGET_PANEL_SIZE: //get panel size
panel_size[0] = lcdc_dev->screen->x_res;
panel_size[1] = lcdc_dev->screen->y_res;
if(copy_to_user(argp, panel_size, 8))
return -EFAULT;
break;
case RK_FBIOSET_CONFIG_DONE:
if (copy_from_user(&(dev_drv->wait_fs),argp,sizeof(dev_drv->wait_fs)))
return -EFAULT;
rk3188_lcdc_alpha_cfg(lcdc_dev);
lcdc_cfg_done(lcdc_dev);
if(dev_drv->wait_fs)
{
spin_lock_irqsave(&dev_drv->cpl_lock,flags);
init_completion(&dev_drv->frame_done);
spin_unlock_irqrestore(&dev_drv->cpl_lock,flags);
timeout = wait_for_completion_timeout(&dev_drv->frame_done,msecs_to_jiffies(dev_drv->cur_screen->ft+5));
if(!timeout&&(!dev_drv->frame_done.done))
{
printk(KERN_ERR "wait for new frame start time out!\n");
return -ETIMEDOUT;
}
}
break;
default:
break;
}
return 0;
}
static void rk3188_lcdc_deint(struct rk3188_lcdc_device * lcdc_dev)
{
spin_lock(&lcdc_dev->reg_lock);
if(likely(lcdc_dev->clk_on))
{
lcdc_dev->clk_on = 0;
lcdc_msk_reg(lcdc_dev, INT_STATUS, m_FS_INT_CLEAR, v_FS_INT_CLEAR(1));
lcdc_msk_reg(lcdc_dev, INT_STATUS, m_HS_INT_EN | m_FS_INT_EN |
m_LF_INT_EN | m_BUS_ERR_INT_EN,v_HS_INT_EN(0) | v_FS_INT_EN(0) |
v_LF_INT_EN(0) | v_BUS_ERR_INT_EN(0)); //disable all lcdc interrupt
lcdc_set_bit(lcdc_dev,SYS_CTRL,m_LCDC_STANDBY);
lcdc_cfg_done(lcdc_dev);
spin_unlock(&lcdc_dev->reg_lock);
}
else //clk already disabled
{
spin_unlock(&lcdc_dev->reg_lock);
return 0;
}
mdelay(1);
}
//enable layer,open:1,enable;0 disable
static int win0_open(struct rk3188_lcdc_device *lcdc_dev,bool open)
{
spin_lock(&lcdc_dev->reg_lock);
if(likely(lcdc_dev->clk_on))
{
if(open)
{
if(!lcdc_dev->atv_layer_cnt)
{
printk(KERN_INFO "lcdc%d wakeup from standby!\n",lcdc_dev->id);
lcdc_msk_reg(lcdc_dev, SYS_CTRL,m_LCDC_STANDBY,v_LCDC_STANDBY(0));
}
lcdc_dev->atv_layer_cnt++;
}
else if((lcdc_dev->atv_layer_cnt > 0) && (!open))
{
lcdc_dev->atv_layer_cnt--;
}
lcdc_dev->driver.layer_par[0]->state = open;
lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_WIN0_EN, v_WIN0_EN(open));
#ifdef CONFIG_LCDC_OVERLAY_ENABLE
lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_ALPHA_MODE_SEL0 | m_WIN1_ALPHA_MODE, v_ALPHA_MODE_SEL0(1) | v_WIN1_ALPHA_MODE(1));
lcdc_msk_reg(lcdc_dev, ALPHA_CTRL, m_WIN1_ALPHA_EN, v_WIN1_ALPHA_EN(open));
#endif
if(!lcdc_dev->atv_layer_cnt) //if no layer used,disable lcdc
{
printk(KERN_INFO "no layer of lcdc%d is used,go to standby!\n",lcdc_dev->id);
lcdc_msk_reg(lcdc_dev, SYS_CTRL,m_LCDC_STANDBY,v_LCDC_STANDBY(1));
}
lcdc_cfg_done(lcdc_dev);
}
spin_unlock(&lcdc_dev->reg_lock);
return 0;
}
static int rk30_load_screen(struct rk_lcdc_device_driver *dev_drv, bool initscreen)
{
int ret = -EINVAL;
struct rk30_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk30_lcdc_device,driver);
rk_screen *screen = dev_drv->cur_screen;
u64 ft;
int fps;
u16 face;
u16 mcu_total, mcu_rwstart, mcu_csstart, mcu_rwend, mcu_csend;
u16 right_margin = screen->right_margin;
u16 lower_margin = screen->lower_margin;
u16 x_res = screen->x_res, y_res = screen->y_res;
// set the rgb or mcu
spin_lock(&lcdc_dev->reg_lock);
if(likely(lcdc_dev->clk_on))
{
if(screen->type==SCREEN_MCU)
{
lcdc_msk_reg(lcdc_dev, MCU_CTRL, m_MCU_OUTPUT_SELECT,v_MCU_OUTPUT_SELECT(1));
// set out format and mcu timing
mcu_total = (screen->mcu_wrperiod*150*1000)/1000000;
if(mcu_total>31)
mcu_total = 31;
if(mcu_total<3)
mcu_total = 3;
mcu_rwstart = (mcu_total+1)/4 - 1;
mcu_rwend = ((mcu_total+1)*3)/4 - 1;
mcu_csstart = (mcu_rwstart>2) ? (mcu_rwstart-3) : (0);
mcu_csend = (mcu_rwend>15) ? (mcu_rwend-1) : (mcu_rwend);
//DBG(1,">> mcu_total=%d, mcu_rwstart=%d, mcu_csstart=%d, mcu_rwend=%d, mcu_csend=%d \n",
// mcu_total, mcu_rwstart, mcu_csstart, mcu_rwend, mcu_csend);
// set horizontal & vertical out timing
right_margin = x_res/6;
screen->pixclock = 150000000; //mcu fix to 150 MHz
lcdc_msk_reg(lcdc_dev, MCU_CTRL,m_MCU_CS_ST | m_MCU_CS_END| m_MCU_RW_ST | m_MCU_RW_END |
m_MCU_WRITE_PERIOD | m_MCU_HOLDMODE_SELECT | m_MCU_HOLDMODE_FRAME_ST,
v_MCU_CS_ST(mcu_csstart) | v_MCU_CS_END(mcu_csend) | v_MCU_RW_ST(mcu_rwstart) |
v_MCU_RW_END(mcu_rwend) | v_MCU_WRITE_PERIOD(mcu_total) |
v_MCU_HOLDMODE_SELECT((SCREEN_MCU==screen->type)?(1):(0)) | v_MCU_HOLDMODE_FRAME_ST(0));
}
switch (screen->face)
{
case OUT_P565:
face = OUT_P565;
lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0));
break;
case OUT_P666:
face = OUT_P666;
lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1));
break;
case OUT_D888_P565:
face = OUT_P888;
lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0));
break;
case OUT_D888_P666:
face = OUT_P888;
lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1));
break;
case OUT_P888:
face = OUT_P888;
lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DITHER_UP_EN, v_DITHER_UP_EN(1));
lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(0) | v_DITHER_DOWN_MODE(0));
break;
default:
lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DITHER_UP_EN, v_DITHER_UP_EN(0));
lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(0) | v_DITHER_DOWN_MODE(0));
face = screen->face;
break;
}
//use default overlay,set vsyn hsync den dclk polarity
lcdc_msk_reg(lcdc_dev, DSP_CTRL0,m_DISPLAY_FORMAT | m_HSYNC_POLARITY | m_VSYNC_POLARITY |
m_DEN_POLARITY |m_DCLK_POLARITY,v_DISPLAY_FORMAT(face) |
v_HSYNC_POLARITY(screen->pin_hsync) | v_VSYNC_POLARITY(screen->pin_vsync) |
v_DEN_POLARITY(screen->pin_den) | v_DCLK_POLARITY(screen->pin_dclk));
//set background color to black,set swap according to the screen panel,disable blank mode
lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_BG_COLOR | m_OUTPUT_RB_SWAP | m_OUTPUT_RG_SWAP | m_DELTA_SWAP |
m_DUMMY_SWAP | m_BLANK_MODE,v_BG_COLOR(0x000000) | v_OUTPUT_RB_SWAP(screen->swap_rb) |
v_OUTPUT_RG_SWAP(screen->swap_rg) | v_DELTA_SWAP(screen->swap_delta) | v_DUMMY_SWAP(screen->swap_dumy) |
v_BLACK_MODE(0));
lcdc_writel(lcdc_dev, DSP_HTOTAL_HS_END,v_HSYNC(screen->hsync_len) |
v_HORPRD(screen->hsync_len + screen->left_margin + x_res + right_margin));
lcdc_writel(lcdc_dev, DSP_HACT_ST_END, v_HAEP(screen->hsync_len + screen->left_margin + x_res) |
v_HASP(screen->hsync_len + screen->left_margin));
lcdc_writel(lcdc_dev, DSP_VTOTAL_VS_END, v_VSYNC(screen->vsync_len) |
v_VERPRD(screen->vsync_len + screen->upper_margin + y_res + lower_margin));
lcdc_writel(lcdc_dev, DSP_VACT_ST_END, v_VAEP(screen->vsync_len + screen->upper_margin+y_res)|
v_VASP(screen->vsync_len + screen->upper_margin));
// let above to take effect
lcdc_cfg_done(lcdc_dev);
}
spin_unlock(&lcdc_dev->reg_lock);
ret = clk_set_rate(lcdc_dev->dclk, screen->pixclock);
if(ret)
{
printk(KERN_ERR ">>>>>> set lcdc%d dclk failed\n",lcdc_dev->id);
}
lcdc_dev->driver.pixclock = lcdc_dev->pixclock = div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
ft = (u64)(screen->upper_margin + screen->lower_margin + screen->y_res +screen->vsync_len)*
(screen->left_margin + screen->right_margin + screen->x_res + screen->hsync_len)*
(dev_drv->pixclock); // one frame time ,(pico seconds)
fps = div64_u64(1000000000000llu,ft);
screen->ft = 1000/fps;
printk("%s: dclk:%lu>>fps:%d ",lcdc_dev->driver.name,clk_get_rate(lcdc_dev->dclk),fps);
if(screen->init)
{
screen->init();
}
printk("%s for lcdc%d ok!\n",__func__,lcdc_dev->id);
return 0;
}
static int win0_set_par(struct rk30_lcdc_device *lcdc_dev,rk_screen *screen,
struct layer_par *par )
{
u32 xact, yact, xvir, yvir, xpos, ypos;
u32 ScaleYrgbX = 0x1000;
u32 ScaleYrgbY = 0x1000;
u32 ScaleCbrX = 0x1000;
u32 ScaleCbrY = 0x1000;
u8 fmt_cfg = 0;
char fmt[9] = "NULL";
xact = par->xact; //active (origin) picture window width/height
yact = par->yact;
xvir = par->xvir; // virtual resolution
yvir = par->yvir;
xpos = par->xpos+screen->left_margin + screen->hsync_len;
ypos = par->ypos+screen->upper_margin + screen->vsync_len;
DBG(1,"%s for lcdc%d>>format:%s>>>xact:%d>>yact:%d>>xsize:%d>>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n",
__func__,lcdc_dev->id,get_format_string(par->format,fmt),xact,yact,par->xsize,par->ysize,xvir,yvir,xpos,ypos);
ScaleYrgbX = CalScale(xact, par->xsize); //both RGB and yuv need this two factor
ScaleYrgbY = CalScale(yact, par->ysize);
switch (par->format)
{
case ARGB888:
case XBGR888:
case ABGR888:
fmt_cfg = 0;
break;
case RGB888:
fmt_cfg = 1;
break;
case RGB565:
fmt_cfg = 2;
break;
case YUV422:// yuv422
fmt_cfg = 5;
ScaleCbrX = CalScale((xact/2), par->xsize);
ScaleCbrY = CalScale(yact, par->ysize);
break;
case YUV420: // yuv420
fmt_cfg = 4;
ScaleCbrX = CalScale(xact/2, par->xsize);
ScaleCbrY = CalScale(yact/2, par->ysize);
break;
case YUV444:// yuv444
fmt_cfg = 6;
ScaleCbrX = CalScale(xact, par->xsize);
ScaleCbrY = CalScale(yact, par->ysize);
break;
default:
printk("%s un supported format\n",__func__);
break;
}
spin_lock(&lcdc_dev->reg_lock);
if(likely(lcdc_dev->clk_on))
{
lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_YRGB,v_X_SCL_FACTOR(ScaleYrgbX) | v_Y_SCL_FACTOR(ScaleYrgbY));
lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_CBR,v_X_SCL_FACTOR(ScaleCbrX)| v_Y_SCL_FACTOR(ScaleCbrY));
lcdc_msk_reg(lcdc_dev, SYS_CTRL1, m_W0_FORMAT, v_W0_FORMAT(fmt_cfg)); //(inf->video_mode==0)
lcdc_writel(lcdc_dev, WIN0_ACT_INFO,v_ACT_WIDTH(xact) | v_ACT_HEIGHT(yact));
lcdc_writel(lcdc_dev, WIN0_DSP_ST, v_DSP_STX(xpos) | v_DSP_STY(ypos));
lcdc_writel(lcdc_dev, WIN0_DSP_INFO, v_DSP_WIDTH(par->xsize)| v_DSP_HEIGHT(par->ysize));
//lcdc_msk_reg(lcdc_dev, WIN0_COLOR_KEY_CTRL, m_COLORKEY_EN | m_KEYCOLOR,
// v_COLORKEY_EN(1) | v_KEYCOLOR(0));
switch(par->format)
{
case XBGR888:
lcdc_writel(lcdc_dev, WIN0_VIR,v_ARGB888_VIRWIDTH(xvir));
lcdc_msk_reg(lcdc_dev,SYS_CTRL1,m_W0_RGB_RB_SWAP,v_W0_RGB_RB_SWAP(1));
break;
case ARGB888:
lcdc_writel(lcdc_dev, WIN0_VIR,v_ARGB888_VIRWIDTH(xvir));
lcdc_msk_reg(lcdc_dev,SYS_CTRL1,m_W0_RGB_RB_SWAP,v_W0_RGB_RB_SWAP(0));
break;
case ABGR888:
lcdc_writel(lcdc_dev, WIN0_VIR,v_ARGB888_VIRWIDTH(xvir));
lcdc_msk_reg(lcdc_dev,SYS_CTRL1,m_W0_RGB_RB_SWAP,v_W0_RGB_RB_SWAP(1));
break;
case RGB888: //rgb888
lcdc_writel(lcdc_dev, WIN0_VIR,v_RGB888_VIRWIDTH(xvir));
lcdc_msk_reg(lcdc_dev,SYS_CTRL1,m_W0_RGB_RB_SWAP,v_W0_RGB_RB_SWAP(0));
break;
case RGB565: //rgb565
lcdc_writel(lcdc_dev, WIN0_VIR,v_RGB565_VIRWIDTH(xvir));
lcdc_msk_reg(lcdc_dev,SYS_CTRL1,m_W0_RGB_RB_SWAP,v_W0_RGB_RB_SWAP(0));
break;
case YUV422:
case YUV420:
lcdc_writel(lcdc_dev, WIN0_VIR,v_YUV_VIRWIDTH(xvir));
lcdc_msk_reg(lcdc_dev,SYS_CTRL1,m_W0_RGB_RB_SWAP,v_W0_RGB_RB_SWAP(0));
break;
default:
printk("%s:un supported format\n",__func__);
break;
}
lcdc_cfg_done(lcdc_dev);
}
spin_unlock(&lcdc_dev->reg_lock);
return 0;
}
static int win0_set_par(struct rk3188_lcdc_device *lcdc_dev,rk_screen *screen,
struct layer_par *par )
{
u32 xact, yact, xvir, yvir, xpos, ypos;
u32 ScaleYrgbX = 0x1000;
u32 ScaleYrgbY = 0x1000;
u32 ScaleCbrX = 0x1000;
u32 ScaleCbrY = 0x1000;
u8 fmt_cfg =0 ; //data format register config value
xact = par->xact; //active (origin) picture window width/height
yact = par->yact;
xvir = par->xvir; // virtual resolution
yvir = par->yvir;
xpos = par->xpos+screen->left_margin + screen->hsync_len;
ypos = par->ypos+screen->upper_margin + screen->vsync_len;
ScaleYrgbX = CalScale(xact, par->xsize); //both RGB and yuv need this two factor
ScaleYrgbY = CalScale(yact, par->ysize);
switch (par->format)
{
case ARGB888:
case XBGR888:
case ABGR888:
fmt_cfg = 0;
break;
case RGB888:
fmt_cfg = 1;
break;
case RGB565:
fmt_cfg = 2;
break;
case YUV422:// yuv422
fmt_cfg = 5;
ScaleCbrX = CalScale((xact/2), par->xsize);
ScaleCbrY = CalScale(yact, par->ysize);
break;
case YUV420: // yuv420
fmt_cfg = 4;
ScaleCbrX = CalScale(xact/2, par->xsize);
ScaleCbrY = CalScale(yact/2, par->ysize);
break;
case YUV444:// yuv444
fmt_cfg = 6;
ScaleCbrX = CalScale(xact, par->xsize);
ScaleCbrY = CalScale(yact, par->ysize);
break;
default:
dev_err(lcdc_dev->driver.dev,"%s:un supported format!\n",__func__);
break;
}
DBG(1,"lcdc%d>>%s>>format:%d>>>xact:%d>>yact:%d>>xsize:%d>>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n",
lcdc_dev->id,__func__,par->format,xact,yact,par->xsize,par->ysize,xvir,yvir,xpos,ypos);
spin_lock(&lcdc_dev->reg_lock);
if(likely(lcdc_dev->clk_on))
{
lcdc_writel(lcdc_dev,WIN0_SCL_FACTOR_YRGB,v_X_SCL_FACTOR(ScaleYrgbX) | v_Y_SCL_FACTOR(ScaleYrgbY));
lcdc_writel(lcdc_dev,WIN0_SCL_FACTOR_CBR,v_X_SCL_FACTOR(ScaleCbrX) | v_Y_SCL_FACTOR(ScaleCbrY));
lcdc_msk_reg(lcdc_dev,SYS_CTRL,m_WIN0_FORMAT,v_WIN0_FORMAT(fmt_cfg)); //(inf->video_mode==0)
lcdc_writel(lcdc_dev,WIN0_ACT_INFO,v_ACT_WIDTH(xact) | v_ACT_HEIGHT(yact));
lcdc_writel(lcdc_dev,WIN0_DSP_ST,v_DSP_STX(xpos) | v_DSP_STY(ypos));
lcdc_writel(lcdc_dev,WIN0_DSP_INFO,v_DSP_WIDTH(par->xsize) | v_DSP_HEIGHT(par->ysize));
lcdc_msk_reg(lcdc_dev,WIN0_COLOR_KEY,m_COLOR_KEY_EN,v_COLOR_KEY_EN(0));
switch(par->format)
{
case XBGR888:
lcdc_msk_reg(lcdc_dev, WIN_VIR,m_WIN0_VIR,v_ARGB888_VIRWIDTH(xvir));
//lcdc_msk_reg(lcdc_dev,ALPHA_CTRL,m_WIN0_ALPHA_EN,v_WIN0_ALPHA_EN(0));
lcdc_msk_reg(lcdc_dev,SYS_CTRL,m_WIN0_RB_SWAP,v_WIN0_RB_SWAP(1));
break;
case ABGR888:
lcdc_msk_reg(lcdc_dev,WIN_VIR,m_WIN0_VIR,v_ARGB888_VIRWIDTH(xvir));
//lcdc_msk_reg(lcdc_dev,ALPHA_CTRL,m_WIN0_ALPHA_EN,v_WIN0_ALPHA_EN(1));
//lcdc_msk_reg(lcdc_dev,DSP_CTRL0,m_WIN0_ALPHA_MODE | m_ALPHA_MODE_SEL0 |
// m_ALPHA_MODE_SEL1,v_WIN0_ALPHA_MODE(1) | v_ALPHA_MODE_SEL0(1) |
// v_ALPHA_MODE_SEL1(0));//default set to per-pixel alpha
lcdc_msk_reg(lcdc_dev,SYS_CTRL,m_WIN0_RB_SWAP,v_WIN0_RB_SWAP(1));
break;
case ARGB888:
lcdc_msk_reg(lcdc_dev,WIN_VIR,m_WIN0_VIR,v_ARGB888_VIRWIDTH(xvir));
//lcdc_msk_reg(lcdc_dev,ALPHA_CTRL,m_WIN0_ALPHA_EN,v_WIN0_ALPHA_EN(1));
//lcdc_msk_reg(lcdc_dev,DSP_CTRL0,m_WIN0_ALPHA_MODE | m_ALPHA_MODE_SEL0,
// v_WIN0_ALPHA_MODE(1) | v_ALPHA_MODE_SEL0(1));//default set to per-pixel alpha
lcdc_msk_reg(lcdc_dev,SYS_CTRL,m_WIN0_RB_SWAP,v_WIN0_RB_SWAP(0));
break;
case RGB888: //rgb888
lcdc_msk_reg(lcdc_dev, WIN_VIR,m_WIN0_VIR,v_RGB888_VIRWIDTH(xvir));
//lcdc_msk_reg(lcdc_dev,ALPHA_CTRL,m_WIN0_ALPHA_EN,v_WIN0_ALPHA_EN(0));
lcdc_msk_reg(lcdc_dev,SYS_CTRL,m_WIN0_RB_SWAP,v_WIN0_RB_SWAP(0));
break;
case RGB565: //rgb565
lcdc_msk_reg(lcdc_dev, WIN_VIR,m_WIN0_VIR,v_RGB565_VIRWIDTH(xvir));
//lcdc_msk_reg(lcdc_dev,ALPHA_CTRL,m_WIN0_ALPHA_EN,v_WIN0_ALPHA_EN(0));
lcdc_msk_reg(lcdc_dev,SYS_CTRL,m_WIN0_RB_SWAP,v_WIN0_RB_SWAP(0));
break;
case YUV422:
case YUV420:
case YUV444:
lcdc_msk_reg(lcdc_dev, WIN_VIR,m_WIN0_VIR,v_YUV_VIRWIDTH(xvir));
//lcdc_msk_reg(lcdc_dev,ALPHA_CTRL,m_WIN0_ALPHA_EN,v_WIN0_ALPHA_EN(0));
lcdc_msk_reg(lcdc_dev,SYS_CTRL,m_WIN0_RB_SWAP,v_WIN0_RB_SWAP(0));
break;
default:
dev_err(lcdc_dev->driver.dev,"%s:un supported format!\n",__func__);
break;
}
lcdc_cfg_done(lcdc_dev);
}
spin_unlock(&lcdc_dev->reg_lock);
return 0;
}
static int rk3188_lcdc_init(struct rk_lcdc_device_driver *dev_drv)
{
int i = 0;
int __iomem *c;
int v;
struct rk3188_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk3188_lcdc_device,driver);
if(lcdc_dev->id == 0) //lcdc0
{
lcdc_dev->pd = clk_get(NULL,"pd_lcdc0");
lcdc_dev->hclk = clk_get(NULL,"hclk_lcdc0");
lcdc_dev->aclk = clk_get(NULL,"aclk_lcdc0");
lcdc_dev->dclk = clk_get(NULL,"dclk_lcdc0");
}
else if(lcdc_dev->id == 1)
{
lcdc_dev->pd = clk_get(NULL,"pd_lcdc1");
lcdc_dev->hclk = clk_get(NULL,"hclk_lcdc1");
lcdc_dev->aclk = clk_get(NULL,"aclk_lcdc1");
lcdc_dev->dclk = clk_get(NULL,"dclk_lcdc1");
}
else
{
printk(KERN_ERR "invalid lcdc device!\n");
return -EINVAL;
}
if (IS_ERR(lcdc_dev->pd) || (IS_ERR(lcdc_dev->aclk)) ||(IS_ERR(lcdc_dev->dclk)) || (IS_ERR(lcdc_dev->hclk)))
{
printk(KERN_ERR "failed to get lcdc%d clk source\n",lcdc_dev->id);
}
rk3188_lcdc_clk_enable(lcdc_dev);
if(lcdc_dev->id == 0)
{
#if defined(CONFIG_LCDC0_IO_18V)
v = 0x40004000; //bit14: 1,1.8v;0,3.3v
writel_relaxed(v,RK30_GRF_BASE + GRF_IO_CON4);
#else
v = 0x40000000;
writel_relaxed(v,RK30_GRF_BASE + GRF_IO_CON4);
#endif
}
if(lcdc_dev->id == 1) //iomux for lcdc1
{
#if defined(CONFIG_LCDC1_IO_18V)
v = 0x80008000; //bit14: 1,1.8v;0,3.3v
writel_relaxed(v,RK30_GRF_BASE + GRF_IO_CON4);
#else
v = 0x80000000;
writel_relaxed(v,RK30_GRF_BASE + GRF_IO_CON4);
#endif
iomux_set(LCDC1_DCLK);
iomux_set(LCDC1_DEN);
iomux_set(LCDC1_HSYNC);
iomux_set(LCDC1_VSYNC);
iomux_set(LCDC1_D0);
iomux_set(LCDC1_D1);
iomux_set(LCDC1_D2);
iomux_set(LCDC1_D3);
iomux_set(LCDC1_D4);
iomux_set(LCDC1_D5);
iomux_set(LCDC1_D6);
iomux_set(LCDC1_D7);
iomux_set(LCDC1_D8);
iomux_set(LCDC1_D9);
iomux_set(LCDC1_D10);
iomux_set(LCDC1_D11);
iomux_set(LCDC1_D12);
iomux_set(LCDC1_D13);
iomux_set(LCDC1_D14);
iomux_set(LCDC1_D15);
iomux_set(LCDC1_D16);
iomux_set(LCDC1_D17);
iomux_set(LCDC1_D18);
iomux_set(LCDC1_D19);
iomux_set(LCDC1_D20);
iomux_set(LCDC1_D21);
iomux_set(LCDC1_D22);
iomux_set(LCDC1_D23);
}
lcdc_set_bit(lcdc_dev,SYS_CTRL,m_AUTO_GATING_EN);//eanble axi-clk auto gating for low power
//lcdc_set_bit(lcdc_dev,DSP_CTRL0,m_WIN0_TOP);
if(dev_drv->cur_screen->dsp_lut)
{
lcdc_msk_reg(lcdc_dev,SYS_CTRL,m_DSP_LUT_EN,v_DSP_LUT_EN(0));
lcdc_cfg_done(lcdc_dev);
msleep(25);
for(i=0;i<256;i++)
{
v = dev_drv->cur_screen->dsp_lut[i];
c = lcdc_dev->dsp_lut_addr_base+i;
writel_relaxed(v,c);
}
lcdc_msk_reg(lcdc_dev,SYS_CTRL,m_DSP_LUT_EN,v_DSP_LUT_EN(1));
}
lcdc_cfg_done(lcdc_dev); // write any value to REG_CFG_DONE let config become effective
rk3188_lcdc_clk_disable(lcdc_dev);
return 0;
}
static int win1_set_par(struct rk30_lcdc_device *lcdc_dev,rk_screen *screen,
struct layer_par *par )
{
u32 xact, yact, xvir, yvir, xpos, ypos;
u32 ScaleYrgbX = 0x1000;
u32 ScaleYrgbY = 0x1000;
u32 ScaleCbrX = 0x1000;
u32 ScaleCbrY = 0x1000;
u8 fmt_cfg = 0;
char fmt[9];
xact = par->xact;
yact = par->yact;
xvir = par->xvir;
yvir = par->yvir;
xpos = par->xpos+screen->left_margin + screen->hsync_len;
ypos = par->ypos+screen->upper_margin + screen->vsync_len;
ScaleYrgbX = CalScale(xact, par->xsize);
ScaleYrgbY = CalScale(yact, par->ysize);
DBG(1,"%s for lcdc%d>>format:%s>>>xact:%d>>yact:%d>>xsize:%d>>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n",
__func__,lcdc_dev->id,get_format_string(par->format,fmt),xact,yact,par->xsize,par->ysize,xvir,yvir,xpos,ypos);
spin_lock(&lcdc_dev->reg_lock);
if(likely(lcdc_dev->clk_on))
{
switch (par->format)
{
case ARGB888:
case XBGR888:
case ABGR888:
fmt_cfg = 0;
break;
case RGB888:
fmt_cfg = 1;
break;
case RGB565:
fmt_cfg = 2;
break;
case YUV422:// yuv422
fmt_cfg = 5;
ScaleCbrX = CalScale((xact/2), par->xsize);
ScaleCbrY = CalScale(yact, par->ysize);
break;
case YUV420: // yuv420
fmt_cfg = 4;
ScaleCbrX = CalScale(xact/2, par->xsize);
ScaleCbrY = CalScale(yact/2, par->ysize);
break;
case YUV444:// yuv444
fmt_cfg = 6;
ScaleCbrX = CalScale(xact, par->xsize);
ScaleCbrY = CalScale(yact, par->ysize);
break;
default:
printk("%s:un supported format\n",__func__);
break;
}
lcdc_writel(lcdc_dev, WIN1_SCL_FACTOR_YRGB, v_X_SCL_FACTOR(ScaleYrgbX) | v_Y_SCL_FACTOR(ScaleYrgbY));
lcdc_writel(lcdc_dev, WIN1_SCL_FACTOR_CBR, v_X_SCL_FACTOR(ScaleCbrX) | v_Y_SCL_FACTOR(ScaleCbrY));
lcdc_msk_reg(lcdc_dev,SYS_CTRL1, m_W1_FORMAT, v_W1_FORMAT(fmt_cfg));
lcdc_writel(lcdc_dev, WIN1_ACT_INFO,v_ACT_WIDTH(xact) | v_ACT_HEIGHT(yact));
lcdc_writel(lcdc_dev, WIN1_DSP_ST,v_DSP_STX(xpos) | v_DSP_STY(ypos));
lcdc_writel(lcdc_dev, WIN1_DSP_INFO,v_DSP_WIDTH(par->xsize) | v_DSP_HEIGHT(par->ysize));
// enable win1 color key and set the color to black(rgb=0)
//lcdc_msk_reg(lcdc_dev, WIN1_COLOR_KEY_CTRL, m_COLORKEY_EN | m_KEYCOLOR,v_COLORKEY_EN(1) | v_KEYCOLOR(0));
switch(par->format)
{
case XBGR888:
case ABGR888:
lcdc_writel(lcdc_dev, WIN1_VIR,v_ARGB888_VIRWIDTH(xvir));
lcdc_msk_reg(lcdc_dev,SYS_CTRL1,m_W1_RGB_RB_SWAP,v_W1_RGB_RB_SWAP(1));
break;
case ARGB888:
lcdc_writel(lcdc_dev, WIN1_VIR,v_ARGB888_VIRWIDTH(xvir));
lcdc_msk_reg(lcdc_dev,SYS_CTRL1,m_W1_RGB_RB_SWAP,v_W1_RGB_RB_SWAP(0));
break;
case RGB888: //rgb888
lcdc_writel(lcdc_dev, WIN1_VIR,v_RGB888_VIRWIDTH(xvir));
lcdc_msk_reg(lcdc_dev,SYS_CTRL1,m_W1_RGB_RB_SWAP,v_W1_RGB_RB_SWAP(0));
break;
case RGB565: //rgb565
lcdc_writel(lcdc_dev, WIN1_VIR,v_RGB565_VIRWIDTH(xvir));
lcdc_msk_reg(lcdc_dev,SYS_CTRL1,m_W1_RGB_RB_SWAP,v_W1_RGB_RB_SWAP(0));
break;
case YUV422:
case YUV420:
lcdc_writel(lcdc_dev, WIN1_VIR,v_YUV_VIRWIDTH(xvir));
lcdc_msk_reg(lcdc_dev,SYS_CTRL1,m_W1_RGB_RB_SWAP,v_W1_RGB_RB_SWAP(0));
break;
default:
printk("%s:un supported format\n",__func__);
break;
}
lcdc_cfg_done(lcdc_dev);
}
spin_unlock(&lcdc_dev->reg_lock);
return 0;
}
static int rk30_lcdc_init(struct rk_lcdc_device_driver *dev_drv)
{
int i = 0;
int __iomem *c;
int v;
struct rk30_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk30_lcdc_device,driver);
if(lcdc_dev->id == 0) //lcdc0
{
lcdc_dev->pd = clk_get(NULL,"pd_lcdc0");
lcdc_dev->hclk = clk_get(NULL,"hclk_lcdc0");
lcdc_dev->aclk = clk_get(NULL,"aclk_lcdc0");
lcdc_dev->dclk = clk_get(NULL,"dclk_lcdc0");
}
else if(lcdc_dev->id == 1)
{
lcdc_dev->pd = clk_get(NULL,"pd_lcdc1");
lcdc_dev->hclk = clk_get(NULL,"hclk_lcdc1");
lcdc_dev->aclk = clk_get(NULL,"aclk_lcdc1");
lcdc_dev->dclk = clk_get(NULL,"dclk_lcdc1");
}
else
{
printk(KERN_ERR "invalid lcdc device!\n");
return -EINVAL;
}
if (IS_ERR(lcdc_dev->pd) || (IS_ERR(lcdc_dev->aclk)) ||(IS_ERR(lcdc_dev->dclk)) || (IS_ERR(lcdc_dev->hclk)))
{
printk(KERN_ERR "failed to get lcdc%d clk source\n",lcdc_dev->id);
}
rk30_lcdc_clk_enable(lcdc_dev);
rk30_lcdc_read_reg_defalut_cfg(lcdc_dev);
lcdc_msk_reg(lcdc_dev,SYS_CTRL0,m_HWC_CHANNEL_ID | m_WIN2_CHANNEL_ID | m_WIN1_CBR_CHANNEL_ID |
m_WIN1_YRGB_CHANNEL_ID | m_WIN0_CBR_CHANNEL1_ID | m_WIN0_YRGB_CHANNEL1_ID |
m_WIN0_CBR_CHANNEL0_ID | m_WIN0_YRGB_CHANNEL0_ID,v_HWC_CHANNEL_ID(7) |
v_WIN2_CHANNEL_ID(6) | v_WIN1_CBR_CHANNEL_ID(5) | v_WIN1_YRGB_CHANNEL_ID(4) |
v_WIN0_CBR_CHANNEL1_ID(3) | v_WIN0_YRGB_CHANNEL1_ID(2) | v_WIN0_CBR_CHANNEL0_ID(1) |
v_WIN0_YRGB_CHANNEL0_ID(0)); //channel id ,just use default value
lcdc_writel(lcdc_dev,WIN0_SCL_FACTOR_YRGB,0x10001000);
lcdc_writel(lcdc_dev,WIN1_SCL_FACTOR_YRGB,0x10001000);
lcdc_set_bit(lcdc_dev,DSP_CTRL0, m_LCDC_AXICLK_AUTO_ENABLE);//eanble axi-clk auto gating for low power
lcdc_msk_reg(lcdc_dev,INT_STATUS,m_FRM_START_INT_CLEAR | m_BUS_ERR_INT_CLEAR | m_LINE_FLAG_INT_EN |
m_FRM_START_INT_EN | m_HOR_START_INT_EN,v_FRM_START_INT_CLEAR(1) | v_BUS_ERR_INT_CLEAR(0) |
v_LINE_FLAG_INT_EN(0) | v_FRM_START_INT_EN(0) | v_HOR_START_INT_EN(0)); //enable frame start interrupt for sync
if(dev_drv->cur_screen->dsp_lut)
{
lcdc_msk_reg(lcdc_dev,SYS_CTRL1,m_DSP_LUT_RAM_EN,v_DSP_LUT_RAM_EN(0));
lcdc_cfg_done(lcdc_dev);
msleep(25);
for(i=0;i<256;i++)
{
v = dev_drv->cur_screen->dsp_lut[i];
c = lcdc_dev->dsp_lut_addr_base+i;
writel_relaxed(v,c);
}
lcdc_msk_reg(lcdc_dev,SYS_CTRL1,m_DSP_LUT_RAM_EN,v_DSP_LUT_RAM_EN(1));
}
lcdc_cfg_done(lcdc_dev); // write any value to REG_CFG_DONE let config become effective
rk30_lcdc_clk_disable(lcdc_dev);
return 0;
}
int rk_lcdc_load_screen(vidinfo_t *vid)
{
struct lcdc_device *lcdc_dev = &rk32_lcdc;
struct rk_screen *screen = lcdc_dev->screen;
int face = 0;
u32 msk, val;
rk_fb_vidinfo_to_screen(vid, screen);
if (vid->screen_type == SCREEN_MIPI ||
vid->screen_type == SCREEN_DUAL_MIPI) {
rk32_mipi_enable(vid);
if (vid->screen_type == SCREEN_MIPI) {
msk = m_MIPI_OUT_EN | m_EDP_OUT_EN |
m_HDMI_OUT_EN | m_RGB_OUT_EN;
val = v_MIPI_OUT_EN(1);
} else {
msk = m_MIPI_OUT_EN | m_EDP_OUT_EN |
m_HDMI_OUT_EN | m_RGB_OUT_EN |
m_DOUB_CHANNEL_EN;
val = v_MIPI_OUT_EN(1) | v_DOUB_CHANNEL_EN(1);
}
} else if (vid->screen_type == SCREEN_EDP) {
msk = m_MIPI_OUT_EN | m_EDP_OUT_EN |
m_HDMI_OUT_EN | m_RGB_OUT_EN;
val = v_EDP_OUT_EN(1);
} else if (vid->screen_type == SCREEN_HDMI) {
msk = m_MIPI_OUT_EN | m_EDP_OUT_EN |
m_HDMI_OUT_EN | m_RGB_OUT_EN;
val = v_HDMI_OUT_EN(1);
} else if (vid->screen_type == SCREEN_RGB ||
vid->screen_type == SCREEN_LVDS ||
vid->screen_type == SCREEN_DUAL_LVDS) {
msk = m_MIPI_OUT_EN | m_EDP_OUT_EN |
m_HDMI_OUT_EN | m_RGB_OUT_EN;
val = v_RGB_OUT_EN(1);
} else {
msk = m_MIPI_OUT_EN | m_EDP_OUT_EN |
m_HDMI_OUT_EN | m_RGB_OUT_EN;
val = v_HDMI_OUT_EN(1);
}
lcdc_msk_reg(lcdc_dev, SYS_CTRL, msk, val);
msk = m_DSP_BLACK_EN | m_DSP_BLANK_EN | m_DSP_OUT_ZERO |
m_DSP_DCLK_POL | m_DSP_DEN_POL | m_DSP_VSYNC_POL |
m_DSP_HSYNC_POL;
val = v_DSP_BLACK_EN(0) | v_DSP_BLANK_EN(0) | v_DSP_OUT_ZERO(0) |
v_DSP_DCLK_POL(vid->vl_clkp) | v_DSP_DEN_POL(vid->vl_oep) |
v_DSP_VSYNC_POL(vid->vl_vsp) | v_DSP_HSYNC_POL(vid->vl_hsp);
lcdc_msk_reg(lcdc_dev, DSP_CTRL0, msk, val);
switch (vid->lcd_face) {
case OUT_P565:
face = OUT_P565;
msk = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE;
val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0);
break;
case OUT_P666:
face = OUT_P666;
msk = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
m_DITHER_DOWN_SEL;
val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1) |
v_DITHER_DOWN_SEL(1);
break;
case OUT_D888_P565:
face = OUT_P888;
msk = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE;
val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0);
break;
case OUT_D888_P666:
face = OUT_P888;
msk = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
m_DITHER_DOWN_SEL;
val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1) |
v_DITHER_DOWN_SEL(1);
break;
case OUT_P888:
face = OUT_P888;
msk = m_DITHER_DOWN_EN | m_DITHER_UP_EN |
m_PRE_DITHER_DOWN_EN;
val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(1) |
v_PRE_DITHER_DOWN_EN(1);
break;
case OUT_P101010:
face = OUT_P101010;
msk = m_DITHER_DOWN_EN | m_DITHER_UP_EN |
m_PRE_DITHER_DOWN_EN;
val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(1) |
v_PRE_DITHER_DOWN_EN(0);
break;
default:
face = vid->lcd_face;
msk = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
m_DITHER_UP_EN;
val = v_DITHER_DOWN_EN(0) | v_DITHER_DOWN_MODE(0) |
v_DITHER_UP_EN(1);
break;
}
lcdc_msk_reg(lcdc_dev, DSP_CTRL1, msk, val);
if (vid->screen_type == SCREEN_EDP || vid->screen_type == SCREEN_HDMI)
face = OUT_P101010;
msk = m_DSP_RG_SWAP | m_DSP_RB_SWAP | m_DSP_DELTA_SWAP |
m_DSP_FIELD_POL | m_DSP_DUMMY_SWAP | m_DSP_BG_SWAP |
m_DSP_OUT_MODE;
val = v_DSP_RG_SWAP(0) | v_DSP_RB_SWAP(vid->vl_swap_rb) |
v_DSP_DELTA_SWAP(0) | v_DSP_DUMMY_SWAP(0) |
v_DSP_FIELD_POL(0) | v_DSP_BG_SWAP(0) |
v_DSP_OUT_MODE(face);
lcdc_msk_reg(lcdc_dev, DSP_CTRL0, msk, val);
lcdc_writel(lcdc_dev, DSP_BG, 0);
val = v_DSP_HS_PW(vid->vl_hspw) | v_DSP_HTOTAL(vid->vl_hspw +
vid->vl_hbpd + vid->vl_col + vid->vl_hfpd);
lcdc_writel(lcdc_dev, DSP_HTOTAL_HS_END, val);
val = v_DSP_HACT_END(vid->vl_hspw + vid->vl_hbpd + vid->vl_col) |
v_DSP_HACT_ST(vid->vl_hspw + vid->vl_hbpd);
lcdc_writel(lcdc_dev, DSP_HACT_ST_END, val);
val = v_DSP_VTOTAL(vid->vl_vspw + vid->vl_vbpd +
vid->vl_row + vid->vl_vfpd) | v_DSP_VS_PW(vid->vl_vspw);
lcdc_writel(lcdc_dev, DSP_VTOTAL_VS_END, val);
val = v_DSP_VACT_END(vid->vl_vspw + vid->vl_vbpd + vid->vl_row)|
v_DSP_VACT_ST(vid->vl_vspw + vid->vl_vbpd);
lcdc_writel(lcdc_dev, DSP_VACT_ST_END, val);
val = v_DSP_HACT_END_POST(vid->vl_hspw + vid->vl_hbpd + vid->vl_col) |
v_DSP_HACT_ST_POST(vid->vl_hspw + vid->vl_hbpd);
lcdc_writel(lcdc_dev, POST_DSP_HACT_INFO, val);
val = v_DSP_HACT_END_POST(vid->vl_vspw + vid->vl_vbpd + vid->vl_row)|
v_DSP_HACT_ST_POST(vid->vl_vspw + vid->vl_vbpd);
lcdc_writel(lcdc_dev, POST_DSP_VACT_INFO, val);
lcdc_writel(lcdc_dev, POST_DSP_VACT_INFO_F1, 0);
lcdc_writel(lcdc_dev, POST_RESERVED, 0x10001000);
lcdc_writel(lcdc_dev, MCU_CTRL, 0);
msk = m_DSP_LINE_FLAG_NUM | m_LINE_FLAG_INTR_EN;
val = v_DSP_LINE_FLAG_NUM(vid->vl_vspw + vid->vl_vbpd + vid->vl_row) |
v_LINE_FLAG_INTR_EN(0);
lcdc_msk_reg(lcdc_dev, INTR_CTRL0, msk, val);
lcdc_cfg_done(lcdc_dev);
if ((vid->screen_type == SCREEN_LVDS) ||
(vid->screen_type == SCREEN_DUAL_LVDS) ||
(vid->screen_type == SCREEN_RGB)) {
rk32_lvds_en(vid);
} else if (vid->screen_type == SCREEN_EDP) {
rk32_edp_enable(vid);
} else if ((vid->screen_type == SCREEN_MIPI) ||
(vid->screen_type == SCREEN_DUAL_MIPI)) {
rk32_dsi_sync();
}
return 0;
}
