static void lio_cn68xx_set_dpi_regs(struct octeon_device *oct)
{
u32 i;
u32 fifo_sizes[6] = { 3, 3, 1, 1, 1, 8 };
lio_pci_writeq(oct, CN6XXX_DPI_DMA_CTL_MASK, CN6XXX_DPI_DMA_CONTROL);
dev_dbg(&oct->pci_dev->dev, "DPI_DMA_CONTROL: 0x%016llx\n",
lio_pci_readq(oct, CN6XXX_DPI_DMA_CONTROL));
for (i = 0; i < 6; i++) {
/* Prevent service of instruction queue for all DMA engines
* Engine 5 will remain 0. Engines 0 - 4 will be setup by
* core.
*/
lio_pci_writeq(oct, 0, CN6XXX_DPI_DMA_ENG_ENB(i));
lio_pci_writeq(oct, fifo_sizes[i], CN6XXX_DPI_DMA_ENG_BUF(i));
dev_dbg(&oct->pci_dev->dev, "DPI_ENG_BUF%d: 0x%016llx\n", i,
lio_pci_readq(oct, CN6XXX_DPI_DMA_ENG_BUF(i)));
}
/* DPI_SLI_PRT_CFG has MPS and MRRS settings that will be set
* separately.
*/
lio_pci_writeq(oct, 1, CN6XXX_DPI_CTL);
dev_dbg(&oct->pci_dev->dev, "DPI_CTL: 0x%016llx\n",
lio_pci_readq(oct, CN6XXX_DPI_CTL));
}
int lio_cn6xxx_soft_reset(struct octeon_device *oct)
{
octeon_write_csr64(oct, CN6XXX_WIN_WR_MASK_REG, 0xFF);
dev_dbg(&oct->pci_dev->dev, "BIST enabled for soft reset\n");
lio_pci_writeq(oct, 1, CN6XXX_CIU_SOFT_BIST);
octeon_write_csr64(oct, CN6XXX_SLI_SCRATCH1, 0x1234ULL);
lio_pci_readq(oct, CN6XXX_CIU_SOFT_RST);
lio_pci_writeq(oct, 1, CN6XXX_CIU_SOFT_RST);
/* make sure that the reset is written before starting timer */
mmiowb();
/* Wait for 10ms as Octeon resets. */
mdelay(100);
if (octeon_read_csr64(oct, CN6XXX_SLI_SCRATCH1) == 0x1234ULL) {
dev_err(&oct->pci_dev->dev, "Soft reset failed\n");
return 1;
}
dev_dbg(&oct->pci_dev->dev, "Reset completed\n");
octeon_write_csr64(oct, CN6XXX_WIN_WR_MASK_REG, 0xFF);
return 0;
}
static void
lio_cn23xx_pf_bar1_idx_setup(struct octeon_device *oct, uint64_t core_addr,
uint32_t idx, int valid)
{
volatile uint64_t bar1;
uint64_t reg_adr;
if (!valid) {
reg_adr = lio_pci_readq(oct,
LIO_CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port,
idx));
bar1 = reg_adr;
lio_pci_writeq(oct, (bar1 & 0xFFFFFFFEULL),
LIO_CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port,
idx));
reg_adr = lio_pci_readq(oct,
LIO_CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port,
idx));
bar1 = reg_adr;
return;
}
/*
* The PEM(0..3)_BAR1_INDEX(0..15)[ADDR_IDX]<23:4> stores
* bits <41:22> of the Core Addr
*/
lio_pci_writeq(oct, (((core_addr >> 22) << 4) | LIO_PCI_BAR1_MASK),
LIO_CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, idx));
bar1 = lio_pci_readq(oct, LIO_CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port,
idx));
}
static int
lio_cn23xx_pf_soft_reset(struct octeon_device *oct)
{
lio_write_csr64(oct, LIO_CN23XX_SLI_WIN_WR_MASK_REG, 0xFF);
lio_dev_dbg(oct, "BIST enabled for CN23XX soft reset\n");
lio_write_csr64(oct, LIO_CN23XX_SLI_SCRATCH1, 0x1234ULL);
/* Initiate chip-wide soft reset */
lio_pci_readq(oct, LIO_CN23XX_RST_SOFT_RST);
lio_pci_writeq(oct, 1, LIO_CN23XX_RST_SOFT_RST);
/* Wait for 100ms as Octeon resets. */
lio_mdelay(100);
if (lio_read_csr64(oct, LIO_CN23XX_SLI_SCRATCH1)) {
lio_dev_err(oct, "Soft reset failed\n");
return (1);
}
lio_dev_dbg(oct, "Reset completed\n");
/* restore the reset value */
lio_write_csr64(oct, LIO_CN23XX_SLI_WIN_WR_MASK_REG, 0xFF);
return (0);
}
static void
lio_cn23xx_pf_bar1_idx_write(struct octeon_device *oct, uint32_t idx,
uint32_t mask)
{
lio_pci_writeq(oct, mask,
LIO_CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, idx));
}
