/*---------------------------------------------------------------------------*/
void
crypto_init(void)
{
volatile int i;
lpm_register_peripheral(permit_pm1);
crypto_enable();
/* Reset the AES/SHA cryptoprocessor */
REG(SYS_CTRL_SRSEC) |= SYS_CTRL_SRSEC_AES;
for(i = 0; i < 16; i++);
REG(SYS_CTRL_SRSEC) &= ~SYS_CTRL_SRSEC_AES;
}
/*---------------------------------------------------------------------------*/
void
pka_init(void)
{
volatile int i;
lpm_register_peripheral(permit_pm1);
pka_enable();
/* Reset the PKA engine */
REG(SYS_CTRL_SRSEC) |= SYS_CTRL_SRSEC_PKA;
for(i = 0; i < 16; i++) {
REG(SYS_CTRL_SRSEC) &= ~SYS_CTRL_SRSEC_PKA;
}
}
/*---------------------------------------------------------------------------*/
void
uart_init(uint8_t uart)
{
const uart_regs_t *regs;
if(uart >= UART_INSTANCE_COUNT) {
return;
}
regs = &uart_regs[uart];
if(regs->rx.port < 0 || regs->tx.port < 0) {
return;
}
lpm_register_peripheral(permit_pm1);
/* Enable clock for the UART while Running, in Sleep and Deep Sleep */
REG(SYS_CTRL_RCGCUART) |= regs->sys_ctrl_rcgcuart_uart;
REG(SYS_CTRL_SCGCUART) |= regs->sys_ctrl_scgcuart_uart;
REG(SYS_CTRL_DCGCUART) |= regs->sys_ctrl_dcgcuart_uart;
/* Run on SYS_DIV */
REG(regs->base | UART_CC) = 0;
/*
* Select the UARTx RX pin by writing to the IOC_UARTRXD_UARTn register
*
* The value to be written will be on of the IOC_INPUT_SEL_Pxn defines from
* ioc.h. The value can also be calculated as:
*
* (port << 3) + pin
*/
REG(regs->ioc_uartrxd_uart) = (regs->rx.port << 3) + regs->rx.pin;
/*
* Pad Control for the TX pin:
* - Set function to UARTn TX
* - Output Enable
*/
ioc_set_sel(regs->tx.port, regs->tx.pin, regs->ioc_pxx_sel_uart_txd);
ioc_set_over(regs->tx.port, regs->tx.pin, IOC_OVERRIDE_OE);
/* Set RX and TX pins to peripheral mode */
GPIO_PERIPHERAL_CONTROL(GPIO_PORT_TO_BASE(regs->tx.port),
GPIO_PIN_MASK(regs->tx.pin));
GPIO_PERIPHERAL_CONTROL(GPIO_PORT_TO_BASE(regs->rx.port),
GPIO_PIN_MASK(regs->rx.pin));
/*
* UART Interrupt Masks:
* Acknowledge RX and RX Timeout
* Acknowledge Framing, Overrun and Break Errors
*/
REG(regs->base | UART_IM) = UART_IM_RXIM | UART_IM_RTIM;
REG(regs->base | UART_IM) |= UART_IM_OEIM | UART_IM_BEIM | UART_IM_FEIM;
REG(regs->base | UART_IFLS) =
UART_IFLS_RXIFLSEL_1_8 | UART_IFLS_TXIFLSEL_1_2;
/* Make sure the UART is disabled before trying to configure it */
REG(regs->base | UART_CTL) = UART_CTL_VALUE;
/* Baud Rate Generation */
REG(regs->base | UART_IBRD) = regs->ibrd;
REG(regs->base | UART_FBRD) = regs->fbrd;
/* UART Control: 8N1 with FIFOs */
REG(regs->base | UART_LCRH) = UART_LCRH_WLEN_8 | UART_LCRH_FEN;
/*
* Enable hardware flow control (RTS/CTS) if requested.
* Note that hardware flow control is available only on UART1.
*/
if(regs->cts.port >= 0) {
REG(IOC_UARTCTS_UART1) = ioc_input_sel(regs->cts.port, regs->cts.pin);
GPIO_PERIPHERAL_CONTROL(GPIO_PORT_TO_BASE(regs->cts.port), GPIO_PIN_MASK(regs->cts.pin));
ioc_set_over(regs->cts.port, regs->cts.pin, IOC_OVERRIDE_DIS);
REG(UART_1_BASE | UART_CTL) |= UART_CTL_CTSEN;
}
if(regs->rts.port >= 0) {
ioc_set_sel(regs->rts.port, regs->rts.pin, IOC_PXX_SEL_UART1_RTS);
GPIO_PERIPHERAL_CONTROL(GPIO_PORT_TO_BASE(regs->rts.port), GPIO_PIN_MASK(regs->rts.pin));
ioc_set_over(regs->rts.port, regs->rts.pin, IOC_OVERRIDE_OE);
REG(UART_1_BASE | UART_CTL) |= UART_CTL_RTSEN;
}
/* UART Enable */
REG(regs->base | UART_CTL) |= UART_CTL_UARTEN;
/* Enable UART0 Interrupts */
nvic_interrupt_enable(regs->nvic_int);
}
/*---------------------------------------------------------------------------*/
void
uart_init(void)
{
lpm_register_peripheral(permit_pm1);
/* Enable clock for the UART while Running, in Sleep and Deep Sleep */
REG(SYS_CTRL_RCGCUART) |= SYS_CTRL_RCGCUART_UART;
REG(SYS_CTRL_SCGCUART) |= SYS_CTRL_SCGCUART_UART;
REG(SYS_CTRL_DCGCUART) |= SYS_CTRL_DCGCUART_UART;
/* Run on SYS_DIV */
REG(UART_BASE | UART_CC) = 0;
/*
* Select the UARTx RX pin by writing to the IOC_UARTRXD_UARTn register
*
* The value to be written will be on of the IOC_INPUT_SEL_Pxn defines from
* ioc.h. The value can also be calculated as:
*
* (port << 3) + pin
*/
REG(IOC_UARTRXD_UART) = (UART_RX_PORT << 3) + UART_RX_PIN;
/*
* Pad Control for the TX pin:
* - Set function to UART0 TX
* - Output Enable
*/
ioc_set_sel(UART_TX_PORT, UART_TX_PIN, IOC_PXX_SEL_UART_TXD);
ioc_set_over(UART_TX_PORT, UART_TX_PIN, IOC_OVERRIDE_OE);
/* Set RX and TX pins to peripheral mode */
GPIO_PERIPHERAL_CONTROL(UART_TX_PORT_BASE, UART_TX_PIN_MASK);
GPIO_PERIPHERAL_CONTROL(UART_RX_PORT_BASE, UART_RX_PIN_MASK);
/*
* UART Interrupt Masks:
* Acknowledge RX and RX Timeout
* Acknowledge Framing, Overrun and Break Errors
*/
REG(UART_BASE | UART_IM) = UART_IM_RXIM | UART_IM_RTIM;
REG(UART_BASE | UART_IM) |= UART_IM_OEIM | UART_IM_BEIM | UART_IM_FEIM;
REG(UART_BASE | UART_IFLS) =
UART_IFLS_RXIFLSEL_1_8 | UART_IFLS_TXIFLSEL_1_2;
/* Make sure the UART is disabled before trying to configure it */
REG(UART_BASE | UART_CTL) = UART_CTL_TXE | UART_CTL_RXE;
/* Baud Rate Generation */
REG(UART_BASE | UART_IBRD) = UART_CONF_IBRD;
REG(UART_BASE | UART_FBRD) = UART_CONF_FBRD;
/* UART Control: 8N1 with FIFOs */
REG(UART_BASE | UART_LCRH) = UART_LCRH_WLEN_8 | UART_LCRH_FEN;
/* UART Enable */
REG(UART_BASE | UART_CTL) |= UART_CTL_UARTEN;
/* Enable UART0 Interrupts */
nvic_interrupt_enable(NVIC_INT_UART);
}
