int xway_nand_probe(struct platform_device *pdev)
{
// ltq_gpio_request(PIN_CS1, 1, 0, 1, "NAND_CS1");
ltq_gpio_request(PIN_CLE, 1, 0, 1, "NAND_CLE");
ltq_gpio_request(PIN_ALE, 1, 0, 1, "NAND_ALE");
if (ltq_is_ar9() || ltq_is_vr9()) {
ltq_gpio_request(PIN_RDY, 1, 0, 0, "NAND_BSY");
ltq_gpio_request(PIN_RD, 1, 0, 1, "NAND_RD");
}
ltq_ebu_w32((NAND_BASE_ADDRESS & 0x1fffff00)
| ADDSEL1_MASK(3) | ADDSEL1_REGEN, LTQ_EBU_ADDSEL1);
ltq_ebu_w32(BUSCON1_SETUP | BUSCON1_BCGEN_RES | BUSCON1_WAITWRC2
| BUSCON1_WAITRDC2 | BUSCON1_HOLDC1 | BUSCON1_RECOVC1
| BUSCON1_CMULT4, LTQ_EBU_BUSCON1);
ltq_ebu_w32(NAND_CON_NANDM | NAND_CON_CSMUX | NAND_CON_CS_P
| NAND_CON_SE_P | NAND_CON_WP_P | NAND_CON_PRE_P
| NAND_CON_IN_CS0 | NAND_CON_OUT_CS0, LTQ_EBU_NAND_CON);
ltq_w32(NAND_WRITE_CMD_RESET, ((u32*)(NAND_BASE_ADDRESS | NAND_WRITE_CMD)));
while((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0);
return 0;
}
void __init
ltq_register_etop(struct ltq_eth_data *eth)
{
/* only register the gphy on socs that have one */
if (ltq_is_ar9() | ltq_is_vr9())
ltq_etop.num_resources = 2;
if (eth) {
ltq_etop.dev.platform_data = eth;
platform_device_register(<q_etop);
}
}
void __init ltq_register_gpio(void)
{
platform_device_register_simple("ltq_gpio", 0,
<q_gpio_resource[0], 1);
platform_device_register_simple("ltq_gpio", 1,
<q_gpio_resource[1], 1);
/* AR9 and VR9 have an extra gpio block */
if (ltq_is_ar9() || ltq_is_vr9()) {
platform_device_register_simple("ltq_gpio", 2,
<q_gpio_resource[2], 1);
}
}
/*!
\brief This function is called by module management in 2.6 kernel or by ifxusb_driver_init with 2.4 kernel
It is to probe and setup IFXUSB core(s).
*/
static int ifxusb_driver_probe(struct platform_device *_dev)
{
int retval = 0;
int *pins = _dev->dev.platform_data;
if (ltq_is_vr9()) {
gpio_request(6, "id1");
gpio_request(9, "id2");
gpio_direction_input(6);
gpio_direction_input(9);
}
if (pins) {
if (pins[0]) {
gpio_request(pins[0], "vbus1");
gpio_direction_output(pins[0], 1);
}
if (pins[1] && ltq_is_vr9()) {
gpio_request(pins[1], "vbus2");
gpio_direction_output(pins[1], 1);
}
}
// Parsing and store the parameters
IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ );
parse_parms();
#ifdef __IS_HOST__
#if defined(__IS_DUAL__)
memset(&ifxusb_hcd_1, 0, sizeof(ifxhcd_hcd_t));
memset(&ifxusb_hcd_2, 0, sizeof(ifxhcd_hcd_t));
ifxusb_hcd_1.core_if.core_no=0;
ifxusb_hcd_2.core_if.core_no=1;
ifxusb_hcd_1.core_if.core_name=(char *)ifxusb_hcd_name_1;
ifxusb_hcd_2.core_if.core_name=(char *)ifxusb_hcd_name_2;
ifxusb_hcd_1.dev=&_dev->dev;
ifxusb_hcd_2.dev=&_dev->dev;
retval = ifxusb_driver_probe_h(&ifxusb_hcd_1,
IFX_USB0_IR,
IFXUSB1_IOMEM_BASE,
IFXUSB1_FIFOMEM_BASE,
IFXUSB1_FIFODBG_BASE
);
if(retval)
goto ifxusb_driver_probe_fail;
retval = ifxusb_driver_probe_h(&ifxusb_hcd_2,
IFX_USB1_IR,
IFXUSB2_IOMEM_BASE,
IFXUSB2_FIFOMEM_BASE,
IFXUSB2_FIFODBG_BASE
);
if(retval)
goto ifxusb_driver_probe_fail;
#elif defined(__IS_FIRST__)
memset(&ifxusb_hcd, 0, sizeof(ifxhcd_hcd_t));
ifxusb_hcd.core_if.core_no=0;
ifxusb_hcd.core_if.core_name=(char *)ifxusb_hcd_name;
ifxusb_hcd.dev=&_dev->dev;
retval = ifxusb_driver_probe_h(&ifxusb_hcd,
IFX_USB0_IR,
IFXUSB1_IOMEM_BASE,
IFXUSB1_FIFOMEM_BASE,
IFXUSB1_FIFODBG_BASE
);
if(retval)
goto ifxusb_driver_probe_fail;
#elif defined(__IS_SECOND__)
memset(&ifxusb_hcd, 0, sizeof(ifxhcd_hcd_t));
ifxusb_hcd.core_if.core_no=1;
ifxusb_hcd.core_if.core_name=(char *)ifxusb_hcd_name;
ifxusb_hcd.dev=&_dev->dev;
retval = ifxusb_driver_probe_h(&ifxusb_hcd,
IFX_USB1_IR,
IFXUSB2_IOMEM_BASE,
IFXUSB2_FIFOMEM_BASE,
IFXUSB2_FIFODBG_BASE
);
if(retval)
goto ifxusb_driver_probe_fail;
#else
memset(&ifxusb_hcd, 0, sizeof(ifxhcd_hcd_t));
ifxusb_hcd.core_if.core_no=0;
ifxusb_hcd.core_if.core_name=(char *)ifxusb_hcd_name;
ifxusb_hcd.dev=&_dev->dev;
retval = ifxusb_driver_probe_h(&ifxusb_hcd,
IFXUSB_IRQ,
IFXUSB_IOMEM_BASE,
IFXUSB_FIFOMEM_BASE,
IFXUSB_FIFODBG_BASE
);
if(retval)
goto ifxusb_driver_probe_fail;
#endif
#if defined(__DO_OC_INT__)
IFXUSB_DEBUGPL( DBG_CIL, "registering (overcurrent) handler for irq%d\n", IFXUSB_OC_IRQ);
#if defined(__IS_DUAL__)
request_irq((unsigned int)IFXUSB_OC_IRQ, &ifx_hcd_oc_irq,
// SA_INTERRUPT|SA_SHIRQ, "ifxusb_oc", (void *)&ifxusb_hcd_1);
IRQF_DISABLED | IRQF_SHARED, "ifxusb_oc", (void *)&ifxusb_hcd_1);
oc_int_id=&ifxusb_hcd_1;
#else
request_irq((unsigned int)IFXUSB_OC_IRQ, &ifx_hcd_oc_irq,
// SA_INTERRUPT|SA_SHIRQ, "ifxusb_oc", (void *)&ifxusb_hcd);
IRQF_DISABLED | IRQF_SHARED, "ifxusb_oc", (void *)&ifxusb_hcd);
oc_int_id=&ifxusb_hcd;
#endif
oc_int_installed=1;
#if defined(__DO_OC_INT_ENABLE__)
ifxusb_oc_int_on();
#endif
#endif
#endif
#ifdef __IS_DEVICE__
memset(&ifxusb_pcd, 0, sizeof(ifxpcd_pcd_t));
ifxusb_pcd.core_if.core_name=(char *)&ifxusb_pcd_name[0];
ifxusb_pcd.dev=&_dev->dev;
#if defined(__IS_FIRST__)
ifxusb_pcd.core_if.core_no=0;
retval = ifxusb_driver_probe_d(&ifxusb_pcd,
IFXUSB1_IRQ,
IFXUSB1_IOMEM_BASE,
IFXUSB1_FIFOMEM_BASE,
IFXUSB1_FIFODBG_BASE
);
#elif defined(__IS_SECOND__)
ifxusb_pcd.core_if.core_no=1;
retval = ifxusb_driver_probe_d(&ifxusb_pcd,
IFXUSB2_IRQ,
IFXUSB2_IOMEM_BASE,
IFXUSB2_FIFOMEM_BASE,
IFXUSB2_FIFODBG_BASE
);
#else
ifxusb_pcd.core_if.core_no=0;
retval = ifxusb_driver_probe_d(&ifxusb_pcd,
IFXUSB_IRQ,
IFXUSB_IOMEM_BASE,
IFXUSB_FIFOMEM_BASE,
IFXUSB_FIFODBG_BASE
);
#endif
if(retval)
goto ifxusb_driver_probe_fail;
#endif
ifxusb_attr_create(&_dev->dev);
return 0;
ifxusb_driver_probe_fail:
ifxusb_driver_remove(_dev);
return retval;
}
void __init arch_init_irq(void)
{
int i;
if (insert_resource(&iomem_resource, <q_icu_resource) < 0)
panic("Failed to insert icu memory");
if (request_mem_region(ltq_icu_resource.start,
resource_size(<q_icu_resource), "icu") < 0)
panic("Failed to request icu memory");
ltq_icu_membase = ioremap_nocache(ltq_icu_resource.start,
resource_size(<q_icu_resource));
if (!ltq_icu_membase)
panic("Failed to remap icu memory");
if (insert_resource(&iomem_resource, <q_eiu_resource) < 0)
panic("Failed to insert eiu memory");
if (request_mem_region(ltq_eiu_resource.start,
resource_size(<q_eiu_resource), "eiu") < 0)
panic("Failed to request eiu memory");
ltq_eiu_membase = ioremap_nocache(ltq_eiu_resource.start,
resource_size(<q_eiu_resource));
if (!ltq_eiu_membase)
panic("Failed to remap eiu memory");
for (i = 0; i < 5; i++)
ltq_icu_w32(0, LTQ_ICU_IM0_IER + (i * LTQ_ICU_OFFSET));
ltq_icu_w32(~0, LTQ_ICU_IM0_ISR + (i * LTQ_ICU_OFFSET));
mips_cpu_irq_init();
for (i = 2; i <= 6; i++)
setup_irq(i, &cascade);
if (cpu_has_vint) {
pr_info("Setting up vectored interrupts\n");
set_vi_handler(2, ltq_hw0_irqdispatch);
set_vi_handler(3, ltq_hw1_irqdispatch);
set_vi_handler(4, ltq_hw2_irqdispatch);
set_vi_handler(5, ltq_hw3_irqdispatch);
set_vi_handler(6, ltq_hw4_irqdispatch);
set_vi_handler(7, ltq_hw5_irqdispatch);
}
for (i = INT_NUM_IRQ0;
i <= (INT_NUM_IRQ0 + (5 * INT_NUM_IM_OFFSET)); i++)
if ((i == LTQ_EIU_IR0) || (i == LTQ_EIU_IR1) ||
(i == LTQ_EIU_IR2))
irq_set_chip_and_handler(i, <q_eiu_type,
handle_level_irq);
else if (((i == LTQ_EIU_IR3) || (i == LTQ_EIU_IR4) ||
(i == LTQ_EIU_IR5)) && (ltq_is_ar9() || ltq_is_vr9()))
irq_set_chip_and_handler(i, <q_eiu_type,
handle_level_irq);
else
irq_set_chip_and_handler(i, <q_irq_type,
handle_level_irq);
#if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 |
IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
#else
set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ0 | IE_IRQ1 |
IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
#endif
}
