/* execute instructions on this CPU until icount expires */ static CPU_EXECUTE( m6805 ) { UINT8 ireg; m6805_Regs *cpustate = get_safe_token(device); S = SP_ADJUST( S ); /* Taken from CPU_SET_CONTEXT when pointer'afying */ do { if (cpustate->pending_interrupts != 0) { if (SUBTYPE==SUBTYPE_M68705) { m68705_Interrupt(cpustate); } else { Interrupt(cpustate); } } debugger_instruction_hook(device, PC); ireg=M_RDOP(PC++); switch( ireg ) { case 0x00: brset(cpustate, 0x01); break; case 0x01: brclr(cpustate, 0x01); break; case 0x02: brset(cpustate, 0x02); break; case 0x03: brclr(cpustate, 0x02); break; case 0x04: brset(cpustate, 0x04); break; case 0x05: brclr(cpustate, 0x04); break; case 0x06: brset(cpustate, 0x08); break; case 0x07: brclr(cpustate, 0x08); break; case 0x08: brset(cpustate, 0x10); break; case 0x09: brclr(cpustate, 0x10); break; case 0x0A: brset(cpustate, 0x20); break; case 0x0B: brclr(cpustate, 0x20); break; case 0x0C: brset(cpustate, 0x40); break; case 0x0D: brclr(cpustate, 0x40); break; case 0x0E: brset(cpustate, 0x80); break; case 0x0F: brclr(cpustate, 0x80); break; case 0x10: bset(cpustate, 0x01); break; case 0x11: bclr(cpustate, 0x01); break; case 0x12: bset(cpustate, 0x02); break; case 0x13: bclr(cpustate, 0x02); break; case 0x14: bset(cpustate, 0x04); break; case 0x15: bclr(cpustate, 0x04); break; case 0x16: bset(cpustate, 0x08); break; case 0x17: bclr(cpustate, 0x08); break; case 0x18: bset(cpustate, 0x10); break; case 0x19: bclr(cpustate, 0x10); break; case 0x1a: bset(cpustate, 0x20); break; case 0x1b: bclr(cpustate, 0x20); break; case 0x1c: bset(cpustate, 0x40); break; case 0x1d: bclr(cpustate, 0x40); break; case 0x1e: bset(cpustate, 0x80); break; case 0x1f: bclr(cpustate, 0x80); break; case 0x20: bra(cpustate); break; case 0x21: brn(cpustate); break; case 0x22: bhi(cpustate); break; case 0x23: bls(cpustate); break; case 0x24: bcc(cpustate); break; case 0x25: bcs(cpustate); break; case 0x26: bne(cpustate); break; case 0x27: beq(cpustate); break; case 0x28: bhcc(cpustate); break; case 0x29: bhcs(cpustate); break; case 0x2a: bpl(cpustate); break; case 0x2b: bmi(cpustate); break; case 0x2c: bmc(cpustate); break; case 0x2d: bms(cpustate); break; case 0x2e: bil(cpustate); break; case 0x2f: bih(cpustate); break; case 0x30: neg_di(cpustate); break; case 0x31: illegal(cpustate); break; case 0x32: illegal(cpustate); break; case 0x33: com_di(cpustate); break; case 0x34: lsr_di(cpustate); break; case 0x35: illegal(cpustate); break; case 0x36: ror_di(cpustate); break; case 0x37: asr_di(cpustate); break; case 0x38: lsl_di(cpustate); break; case 0x39: rol_di(cpustate); break; case 0x3a: dec_di(cpustate); break; case 0x3b: illegal(cpustate); break; case 0x3c: inc_di(cpustate); break; case 0x3d: tst_di(cpustate); break; case 0x3e: illegal(cpustate); break; case 0x3f: clr_di(cpustate); break; case 0x40: nega(cpustate); break; case 0x41: illegal(cpustate); break; case 0x42: illegal(cpustate); break; case 0x43: coma(cpustate); break; case 0x44: lsra(cpustate); break; case 0x45: illegal(cpustate); break; case 0x46: rora(cpustate); break; case 0x47: asra(cpustate); break; case 0x48: lsla(cpustate); break; case 0x49: rola(cpustate); break; case 0x4a: deca(cpustate); break; case 0x4b: illegal(cpustate); break; case 0x4c: inca(cpustate); break; case 0x4d: tsta(cpustate); break; case 0x4e: illegal(cpustate); break; case 0x4f: clra(cpustate); break; case 0x50: negx(cpustate); break; case 0x51: illegal(cpustate); break; case 0x52: illegal(cpustate); break; case 0x53: comx(cpustate); break; case 0x54: lsrx(cpustate); break; case 0x55: illegal(cpustate); break; case 0x56: rorx(cpustate); break; case 0x57: asrx(cpustate); break; case 0x58: aslx(cpustate); break; case 0x59: rolx(cpustate); break; case 0x5a: decx(cpustate); break; case 0x5b: illegal(cpustate); break; case 0x5c: incx(cpustate); break; case 0x5d: tstx(cpustate); break; case 0x5e: illegal(cpustate); break; case 0x5f: clrx(cpustate); break; case 0x60: neg_ix1(cpustate); break; case 0x61: illegal(cpustate); break; case 0x62: illegal(cpustate); break; case 0x63: com_ix1(cpustate); break; case 0x64: lsr_ix1(cpustate); break; case 0x65: illegal(cpustate); break; case 0x66: ror_ix1(cpustate); break; case 0x67: asr_ix1(cpustate); break; case 0x68: lsl_ix1(cpustate); break; case 0x69: rol_ix1(cpustate); break; case 0x6a: dec_ix1(cpustate); break; case 0x6b: illegal(cpustate); break; case 0x6c: inc_ix1(cpustate); break; case 0x6d: tst_ix1(cpustate); break; case 0x6e: illegal(cpustate); break; case 0x6f: clr_ix1(cpustate); break; case 0x70: neg_ix(cpustate); break; case 0x71: illegal(cpustate); break; case 0x72: illegal(cpustate); break; case 0x73: com_ix(cpustate); break; case 0x74: lsr_ix(cpustate); break; case 0x75: illegal(cpustate); break; case 0x76: ror_ix(cpustate); break; case 0x77: asr_ix(cpustate); break; case 0x78: lsl_ix(cpustate); break; case 0x79: rol_ix(cpustate); break; case 0x7a: dec_ix(cpustate); break; case 0x7b: illegal(cpustate); break; case 0x7c: inc_ix(cpustate); break; case 0x7d: tst_ix(cpustate); break; case 0x7e: illegal(cpustate); break; case 0x7f: clr_ix(cpustate); break; case 0x80: rti(cpustate); break; case 0x81: rts(cpustate); break; case 0x82: illegal(cpustate); break; case 0x83: swi(cpustate); break; case 0x84: illegal(cpustate); break; case 0x85: illegal(cpustate); break; case 0x86: illegal(cpustate); break; case 0x87: illegal(cpustate); break; case 0x88: illegal(cpustate); break; case 0x89: illegal(cpustate); break; case 0x8a: illegal(cpustate); break; case 0x8b: illegal(cpustate); break; case 0x8c: illegal(cpustate); break; case 0x8d: illegal(cpustate); break; case 0x8e: illegal(cpustate); break; case 0x8f: illegal(cpustate); break; case 0x90: illegal(cpustate); break; case 0x91: illegal(cpustate); break; case 0x92: illegal(cpustate); break; case 0x93: illegal(cpustate); break; case 0x94: illegal(cpustate); break; case 0x95: illegal(cpustate); break; case 0x96: illegal(cpustate); break; case 0x97: tax(cpustate); break; case 0x98: CLC; break; case 0x99: SEC; break; #if IRQ_LEVEL_DETECT case 0x9a: CLI; if (m6805.irq_state != CLEAR_LINE) m6805.pending_interrupts |= 1<<M6805_IRQ_LINE; break; #else case 0x9a: CLI; break; #endif case 0x9b: SEI; break; case 0x9c: rsp(cpustate); break; case 0x9d: nop(cpustate); break; case 0x9e: illegal(cpustate); break; case 0x9f: txa(cpustate); break; case 0xa0: suba_im(cpustate); break; case 0xa1: cmpa_im(cpustate); break; case 0xa2: sbca_im(cpustate); break; case 0xa3: cpx_im(cpustate); break; case 0xa4: anda_im(cpustate); break; case 0xa5: bita_im(cpustate); break; case 0xa6: lda_im(cpustate); break; case 0xa7: illegal(cpustate); break; case 0xa8: eora_im(cpustate); break; case 0xa9: adca_im(cpustate); break; case 0xaa: ora_im(cpustate); break; case 0xab: adda_im(cpustate); break; case 0xac: illegal(cpustate); break; case 0xad: bsr(cpustate); break; case 0xae: ldx_im(cpustate); break; case 0xaf: illegal(cpustate); break; case 0xb0: suba_di(cpustate); break; case 0xb1: cmpa_di(cpustate); break; case 0xb2: sbca_di(cpustate); break; case 0xb3: cpx_di(cpustate); break; case 0xb4: anda_di(cpustate); break; case 0xb5: bita_di(cpustate); break; case 0xb6: lda_di(cpustate); break; case 0xb7: sta_di(cpustate); break; case 0xb8: eora_di(cpustate); break; case 0xb9: adca_di(cpustate); break; case 0xba: ora_di(cpustate); break; case 0xbb: adda_di(cpustate); break; case 0xbc: jmp_di(cpustate); break; case 0xbd: jsr_di(cpustate); break; case 0xbe: ldx_di(cpustate); break; case 0xbf: stx_di(cpustate); break; case 0xc0: suba_ex(cpustate); break; case 0xc1: cmpa_ex(cpustate); break; case 0xc2: sbca_ex(cpustate); break; case 0xc3: cpx_ex(cpustate); break; case 0xc4: anda_ex(cpustate); break; case 0xc5: bita_ex(cpustate); break; case 0xc6: lda_ex(cpustate); break; case 0xc7: sta_ex(cpustate); break; case 0xc8: eora_ex(cpustate); break; case 0xc9: adca_ex(cpustate); break; case 0xca: ora_ex(cpustate); break; case 0xcb: adda_ex(cpustate); break; case 0xcc: jmp_ex(cpustate); break; case 0xcd: jsr_ex(cpustate); break; case 0xce: ldx_ex(cpustate); break; case 0xcf: stx_ex(cpustate); break; case 0xd0: suba_ix2(cpustate); break; case 0xd1: cmpa_ix2(cpustate); break; case 0xd2: sbca_ix2(cpustate); break; case 0xd3: cpx_ix2(cpustate); break; case 0xd4: anda_ix2(cpustate); break; case 0xd5: bita_ix2(cpustate); break; case 0xd6: lda_ix2(cpustate); break; case 0xd7: sta_ix2(cpustate); break; case 0xd8: eora_ix2(cpustate); break; case 0xd9: adca_ix2(cpustate); break; case 0xda: ora_ix2(cpustate); break; case 0xdb: adda_ix2(cpustate); break; case 0xdc: jmp_ix2(cpustate); break; case 0xdd: jsr_ix2(cpustate); break; case 0xde: ldx_ix2(cpustate); break; case 0xdf: stx_ix2(cpustate); break; case 0xe0: suba_ix1(cpustate); break; case 0xe1: cmpa_ix1(cpustate); break; case 0xe2: sbca_ix1(cpustate); break; case 0xe3: cpx_ix1(cpustate); break; case 0xe4: anda_ix1(cpustate); break; case 0xe5: bita_ix1(cpustate); break; case 0xe6: lda_ix1(cpustate); break; case 0xe7: sta_ix1(cpustate); break; case 0xe8: eora_ix1(cpustate); break; case 0xe9: adca_ix1(cpustate); break; case 0xea: ora_ix1(cpustate); break; case 0xeb: adda_ix1(cpustate); break; case 0xec: jmp_ix1(cpustate); break; case 0xed: jsr_ix1(cpustate); break; case 0xee: ldx_ix1(cpustate); break; case 0xef: stx_ix1(cpustate); break; case 0xf0: suba_ix(cpustate); break; case 0xf1: cmpa_ix(cpustate); break; case 0xf2: sbca_ix(cpustate); break; case 0xf3: cpx_ix(cpustate); break; case 0xf4: anda_ix(cpustate); break; case 0xf5: bita_ix(cpustate); break; case 0xf6: lda_ix(cpustate); break; case 0xf7: sta_ix(cpustate); break; case 0xf8: eora_ix(cpustate); break; case 0xf9: adca_ix(cpustate); break; case 0xfa: ora_ix(cpustate); break; case 0xfb: adda_ix(cpustate); break; case 0xfc: jmp_ix(cpustate); break; case 0xfd: jsr_ix(cpustate); break; case 0xfe: ldx_ix(cpustate); break; case 0xff: stx_ix(cpustate); break; } cpustate->iCount -= cycles1[ireg]; } while( cpustate->iCount > 0 ); }
/* Generate interrupts */ static void Interrupt(void) { /* the 6805 latches interrupt requests internally, so we don't clear */ /* pending_interrupts until the interrupt is taken, no matter what the */ /* external IRQ pin does. */ #if (1) //HAS_HD63705) if( (m6805.pending_interrupts & (1<<HD63705_INT_NMI)) != 0) { PUSHWORD(m6805.pc); PUSHBYTE(m6805.x); PUSHBYTE(m6805.a); PUSHBYTE(m6805.cc); SEI; /* no vectors supported, just do the callback to clear irq_state if needed */ if (m6805.irq_callback) (*m6805.irq_callback)(0); RM16( 0x1ffc, &pPC); change_pc(PC); m6805.pending_interrupts &= ~(1<<HD63705_INT_NMI); m6805_ICount -= 11; } else if( (m6805.pending_interrupts & ((1<<M6805_IRQ_LINE)|HD63705_INT_MASK)) != 0 ) { if ( (CC & IFLAG) == 0 ) { #else if( (m6805.pending_interrupts & (1<<M6805_IRQ_LINE)) != 0 ) { if ( (CC & IFLAG) == 0 ) { #endif { /* standard IRQ */ //#if (HAS_HD63705) // if(SUBTYPE!=SUBTYPE_HD63705) //#endif // PC |= ~AMASK; PUSHWORD(m6805.pc); PUSHBYTE(m6805.x); PUSHBYTE(m6805.a); PUSHBYTE(m6805.cc); SEI; /* no vectors supported, just do the callback to clear irq_state if needed */ if (m6805.irq_callback) (*m6805.irq_callback)(0); //#if (HAS_HD63705) if(SUBTYPE==SUBTYPE_HD63705) { /* Need to add emulation of other interrupt sources here KW-2/4/99 */ /* This is just a quick patch for Namco System 2 operation */ if((m6805.pending_interrupts&(1<<HD63705_INT_IRQ1))!=0) { m6805.pending_interrupts &= ~(1<<HD63705_INT_IRQ1); RM16( 0x1ff8, &pPC); change_pc(PC); } else if((m6805.pending_interrupts&(1<<HD63705_INT_IRQ2))!=0) { m6805.pending_interrupts &= ~(1<<HD63705_INT_IRQ2); RM16( 0x1fec, &pPC); change_pc(PC); } else if((m6805.pending_interrupts&(1<<HD63705_INT_ADCONV))!=0) { m6805.pending_interrupts &= ~(1<<HD63705_INT_ADCONV); RM16( 0x1fea, &pPC); change_pc(PC); } else if((m6805.pending_interrupts&(1<<HD63705_INT_TIMER1))!=0) { m6805.pending_interrupts &= ~(1<<HD63705_INT_TIMER1); RM16( 0x1ff6, &pPC); change_pc(PC); } else if((m6805.pending_interrupts&(1<<HD63705_INT_TIMER2))!=0) { m6805.pending_interrupts &= ~(1<<HD63705_INT_TIMER2); RM16( 0x1ff4, &pPC); change_pc(PC); } else if((m6805.pending_interrupts&(1<<HD63705_INT_TIMER3))!=0) { m6805.pending_interrupts &= ~(1<<HD63705_INT_TIMER3); RM16( 0x1ff2, &pPC); change_pc(PC); } else if((m6805.pending_interrupts&(1<<HD63705_INT_PCI))!=0) { m6805.pending_interrupts &= ~(1<<HD63705_INT_PCI); RM16( 0x1ff0, &pPC); change_pc(PC); } else if((m6805.pending_interrupts&(1<<HD63705_INT_SCI))!=0) { m6805.pending_interrupts &= ~(1<<HD63705_INT_SCI); RM16( 0x1fee, &pPC); change_pc(PC); } } else //#endif { RM16( 0xffff - 5, &pPC ); change_pc(PC); } } // CC & IFLAG m6805.pending_interrupts &= ~(1<<M6805_IRQ_LINE); } m6805_ICount -= 11; } } static void m6805_reset() { int (*save_irqcallback)(int) = m6805.irq_callback; memset(&m6805, 0, sizeof(m6805)); m6805.irq_callback = save_irqcallback; /* Force CPU sub-type and relevant masks */ m6805.subtype = SUBTYPE_M6805; SP_MASK = 0x07f; SP_LOW = 0x060; /* Initial stack pointer */ S = SP_MASK; /* IRQ disabled */ SEI; RM16( 0xfffe , &pPC ); change_pc(PC); } void m6805Reset() { m6805_reset(); } //static void m6805_init(int ) //int (*irqcallback)(int)) //{ // m6805.irq_callback = irqcallback; //} //static void m6805_exit(void) //{ // /* nothing to do */ //} void m6805SetIrqLine(int , int state) { /* Basic 6805 only has one IRQ line */ /* See HD63705 specific version */ if (m6805.irq_state[0] == state) return; m6805.irq_state[0] = state; if (state != CLEAR_LINE) m6805.pending_interrupts |= 1<<M6805_IRQ_LINE; } #include "6805ops.c" /* execute instructions on this CPU until icount expires */ int m6805Run(int cycles) { UINT8 ireg; m6805_ICount = cycles; do { if (m6805.pending_interrupts != 0) { if (SUBTYPE==SUBTYPE_M68705) { m68705_Interrupt(); } else { Interrupt(); } } ireg=M_RDOP(PC++); switch( ireg ) { case 0x00: brset(0x01); break; case 0x01: brclr(0x01); break; case 0x02: brset(0x02); break; case 0x03: brclr(0x02); break; case 0x04: brset(0x04); break; case 0x05: brclr(0x04); break; case 0x06: brset(0x08); break; case 0x07: brclr(0x08); break; case 0x08: brset(0x10); break; case 0x09: brclr(0x10); break; case 0x0A: brset(0x20); break; case 0x0B: brclr(0x20); break; case 0x0C: brset(0x40); break; case 0x0D: brclr(0x40); break; case 0x0E: brset(0x80); break; case 0x0F: brclr(0x80); break; case 0x10: bset(0x01); break; case 0x11: bclr(0x01); break; case 0x12: bset(0x02); break; case 0x13: bclr(0x02); break; case 0x14: bset(0x04); break; case 0x15: bclr(0x04); break; case 0x16: bset(0x08); break; case 0x17: bclr(0x08); break; case 0x18: bset(0x10); break; case 0x19: bclr(0x10); break; case 0x1a: bset(0x20); break; case 0x1b: bclr(0x20); break; case 0x1c: bset(0x40); break; case 0x1d: bclr(0x40); break; case 0x1e: bset(0x80); break; case 0x1f: bclr(0x80); break; case 0x20: bra(); break; case 0x21: brn(); break; case 0x22: bhi(); break; case 0x23: bls(); break; case 0x24: bcc(); break; case 0x25: bcs(); break; case 0x26: bne(); break; case 0x27: beq(); break; case 0x28: bhcc(); break; case 0x29: bhcs(); break; case 0x2a: bpl(); break; case 0x2b: bmi(); break; case 0x2c: bmc(); break; case 0x2d: bms(); break; case 0x2e: bil(); break; case 0x2f: bih(); break; case 0x30: neg_di(); break; case 0x31: illegal(); break; case 0x32: illegal(); break; case 0x33: com_di(); break; case 0x34: lsr_di(); break; case 0x35: illegal(); break; case 0x36: ror_di(); break; case 0x37: asr_di(); break; case 0x38: lsl_di(); break; case 0x39: rol_di(); break; case 0x3a: dec_di(); break; case 0x3b: illegal(); break; case 0x3c: inc_di(); break; case 0x3d: tst_di(); break; case 0x3e: illegal(); break; case 0x3f: clr_di(); break; case 0x40: nega(); break; case 0x41: illegal(); break; case 0x42: illegal(); break; case 0x43: coma(); break; case 0x44: lsra(); break; case 0x45: illegal(); break; case 0x46: rora(); break; case 0x47: asra(); break; case 0x48: lsla(); break; case 0x49: rola(); break; case 0x4a: deca(); break; case 0x4b: illegal(); break; case 0x4c: inca(); break; case 0x4d: tsta(); break; case 0x4e: illegal(); break; case 0x4f: clra(); break; case 0x50: negx(); break; case 0x51: illegal(); break; case 0x52: illegal(); break; case 0x53: comx(); break; case 0x54: lsrx(); break; case 0x55: illegal(); break; case 0x56: rorx(); break; case 0x57: asrx(); break; case 0x58: aslx(); break; case 0x59: rolx(); break; case 0x5a: decx(); break; case 0x5b: illegal(); break; case 0x5c: incx(); break; case 0x5d: tstx(); break; case 0x5e: illegal(); break; case 0x5f: clrx(); break; case 0x60: neg_ix1(); break; case 0x61: illegal(); break; case 0x62: illegal(); break; case 0x63: com_ix1(); break; case 0x64: lsr_ix1(); break; case 0x65: illegal(); break; case 0x66: ror_ix1(); break; case 0x67: asr_ix1(); break; case 0x68: lsl_ix1(); break; case 0x69: rol_ix1(); break; case 0x6a: dec_ix1(); break; case 0x6b: illegal(); break; case 0x6c: inc_ix1(); break; case 0x6d: tst_ix1(); break; case 0x6e: illegal(); break; case 0x6f: clr_ix1(); break; case 0x70: neg_ix(); break; case 0x71: illegal(); break; case 0x72: illegal(); break; case 0x73: com_ix(); break; case 0x74: lsr_ix(); break; case 0x75: illegal(); break; case 0x76: ror_ix(); break; case 0x77: asr_ix(); break; case 0x78: lsl_ix(); break; case 0x79: rol_ix(); break; case 0x7a: dec_ix(); break; case 0x7b: illegal(); break; case 0x7c: inc_ix(); break; case 0x7d: tst_ix(); break; case 0x7e: illegal(); break; case 0x7f: clr_ix(); break; case 0x80: rti(); break; case 0x81: rts(); break; case 0x82: illegal(); break; case 0x83: swi(); break; case 0x84: illegal(); break; case 0x85: illegal(); break; case 0x86: illegal(); break; case 0x87: illegal(); break; case 0x88: illegal(); break; case 0x89: illegal(); break; case 0x8a: illegal(); break; case 0x8b: illegal(); break; case 0x8c: illegal(); break; case 0x8d: illegal(); break; case 0x8e: illegal(); break; case 0x8f: illegal(); break; case 0x90: illegal(); break; case 0x91: illegal(); break; case 0x92: illegal(); break; case 0x93: illegal(); break; case 0x94: illegal(); break; case 0x95: illegal(); break; case 0x96: illegal(); break; case 0x97: tax(); break; case 0x98: CLC; break; case 0x99: SEC; break; #if IRQ_LEVEL_DETECT case 0x9a: CLI; if (m6805.irq_state != CLEAR_LINE) m6805.pending_interrupts |= 1<<M6805_IRQ_LINE; break; #else case 0x9a: CLI; break; #endif case 0x9b: SEI; break; case 0x9c: rsp(); break; case 0x9d: nop(); break; case 0x9e: illegal(); break; case 0x9f: txa(); break; case 0xa0: suba_im(); break; case 0xa1: cmpa_im(); break; case 0xa2: sbca_im(); break; case 0xa3: cpx_im(); break; case 0xa4: anda_im(); break; case 0xa5: bita_im(); break; case 0xa6: lda_im(); break; case 0xa7: illegal(); break; case 0xa8: eora_im(); break; case 0xa9: adca_im(); break; case 0xaa: ora_im(); break; case 0xab: adda_im(); break; case 0xac: illegal(); break; case 0xad: bsr(); break; case 0xae: ldx_im(); break; case 0xaf: illegal(); break; case 0xb0: suba_di(); break; case 0xb1: cmpa_di(); break; case 0xb2: sbca_di(); break; case 0xb3: cpx_di(); break; case 0xb4: anda_di(); break; case 0xb5: bita_di(); break; case 0xb6: lda_di(); break; case 0xb7: sta_di(); break; case 0xb8: eora_di(); break; case 0xb9: adca_di(); break; case 0xba: ora_di(); break; case 0xbb: adda_di(); break; case 0xbc: jmp_di(); break; case 0xbd: jsr_di(); break; case 0xbe: ldx_di(); break; case 0xbf: stx_di(); break; case 0xc0: suba_ex(); break; case 0xc1: cmpa_ex(); break; case 0xc2: sbca_ex(); break; case 0xc3: cpx_ex(); break; case 0xc4: anda_ex(); break; case 0xc5: bita_ex(); break; case 0xc6: lda_ex(); break; case 0xc7: sta_ex(); break; case 0xc8: eora_ex(); break; case 0xc9: adca_ex(); break; case 0xca: ora_ex(); break; case 0xcb: adda_ex(); break; case 0xcc: jmp_ex(); break; case 0xcd: jsr_ex(); break; case 0xce: ldx_ex(); break; case 0xcf: stx_ex(); break; case 0xd0: suba_ix2(); break; case 0xd1: cmpa_ix2(); break; case 0xd2: sbca_ix2(); break; case 0xd3: cpx_ix2(); break; case 0xd4: anda_ix2(); break; case 0xd5: bita_ix2(); break; case 0xd6: lda_ix2(); break; case 0xd7: sta_ix2(); break; case 0xd8: eora_ix2(); break; case 0xd9: adca_ix2(); break; case 0xda: ora_ix2(); break; case 0xdb: adda_ix2(); break; case 0xdc: jmp_ix2(); break; case 0xdd: jsr_ix2(); break; case 0xde: ldx_ix2(); break; case 0xdf: stx_ix2(); break; case 0xe0: suba_ix1(); break; case 0xe1: cmpa_ix1(); break; case 0xe2: sbca_ix1(); break; case 0xe3: cpx_ix1(); break; case 0xe4: anda_ix1(); break; case 0xe5: bita_ix1(); break; case 0xe6: lda_ix1(); break; case 0xe7: sta_ix1(); break; case 0xe8: eora_ix1(); break; case 0xe9: adca_ix1(); break; case 0xea: ora_ix1(); break; case 0xeb: adda_ix1(); break; case 0xec: jmp_ix1(); break; case 0xed: jsr_ix1(); break; case 0xee: ldx_ix1(); break; case 0xef: stx_ix1(); break; case 0xf0: suba_ix(); break; case 0xf1: cmpa_ix(); break; case 0xf2: sbca_ix(); break; case 0xf3: cpx_ix(); break; case 0xf4: anda_ix(); break; case 0xf5: bita_ix(); break; case 0xf6: lda_ix(); break; case 0xf7: sta_ix(); break; case 0xf8: eora_ix(); break; case 0xf9: adca_ix(); break; case 0xfa: ora_ix(); break; case 0xfb: adda_ix(); break; case 0xfc: jmp_ix(); break; case 0xfd: jsr_ix(); break; case 0xfe: ldx_ix(); break; case 0xff: stx_ix(); break; } m6805_ICount -= cycles1[ireg]; m6805.nTotalCycles += cycles1[ireg]; } while( m6805_ICount > 0 ); return cycles - m6805_ICount; }