static inline void m_can_config_endisable(const struct m_can_priv *priv, bool enable) { u32 cccr = m_can_read(priv, M_CAN_CCCR); u32 timeout = 10; u32 val = 0; if (enable) { /* enable m_can configuration */ m_can_write(priv, M_CAN_CCCR, cccr | CCCR_INIT); udelay(5); /* CCCR.CCE can only be set/reset while CCCR.INIT = '1' */ m_can_write(priv, M_CAN_CCCR, cccr | CCCR_INIT | CCCR_CCE); } else { m_can_write(priv, M_CAN_CCCR, cccr & ~(CCCR_INIT | CCCR_CCE)); } /* there's a delay for module initialization */ if (enable) val = CCCR_INIT | CCCR_CCE; while ((m_can_read(priv, M_CAN_CCCR) & (CCCR_INIT | CCCR_CCE)) != val) { if (timeout == 0) { netdev_warn(priv->dev, "Failed to init module\n"); return; } timeout--; udelay(1); } }
static inline void m_can_disable_all_interrupts(const struct m_can_priv *priv) { m_can_write(priv, M_CAN_ILE, 0x0); }
static inline void m_can_enable_all_interrupts(const struct m_can_priv *priv) { m_can_write(priv, M_CAN_ILE, ILE_EINT0 | ILE_EINT1); }
static inline void m_can_enable_all_interrupts(const struct m_can_priv *priv) { /* Only interrupt line 0 is used in this driver */ m_can_write(priv, M_CAN_ILE, ILE_EINT0); }