inline uint32_t get_efikamx_rev(void)
{
if (machine_is_efikamx())
return get_mx_rev();
else if (machine_is_efikasb())
return get_sb_rev();
}
static inline uint32_t efika_mmc_cd(void)
{
if (machine_is_efikamx())
return MX51_PIN_GPIO1_0;
else
return MX51_PIN_EIM_CS2;
}
static inline uint32_t efikamx_mmc_getcd(u32 base)
{
if (base == MMC_SDHC1_BASE_ADDR)
if (machine_is_efikamx())
return EFIKAMX_SDHC1_CD;
else
return EFIKASB_SDHC1_CD;
else
return EFIKASB_SDHC2_CD;
}
int checkboard(void)
{
u32 rev = get_efikamx_rev();
printf("Board: Genesi Efika MX ");
if (machine_is_efikamx())
printf("Smarttop (1.%i)\n", rev & 0xf);
else if (machine_is_efikasb())
printf("Smartbook\n");
return 0;
}
void efikamx_toggle_led(uint32_t mask)
{
if (machine_is_efikamx()) {
gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9),
mask & EFIKAMX_LED_BLUE);
gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_VSYNC),
mask & EFIKAMX_LED_GREEN);
gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_HSYNC),
mask & EFIKAMX_LED_RED);
} else {
gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_CS0),
mask & EFIKAMX_LED_BLUE);
gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_3),
!(mask & EFIKAMX_LED_GREEN));
}
}
int board_late_init(void)
{
if (machine_is_efikamx()) {
/*
* Set up Blue LED for "In U-Boot" status.
* We're all relocated and ready to U-Boot!
*/
gpio_set_value(EFIKAMX_LED_RED, 0);
gpio_set_value(EFIKAMX_LED_GREEN, 0);
gpio_set_value(EFIKAMX_LED_BLUE, 1);
}
power_init();
imx_iomux_v3_setup_multiple_pads(efikamx_pata_pads,
ARRAY_SIZE(efikamx_pata_pads));
setup_iomux_usb();
return 0;
}
int board_mmc_init(bd_t *bis)
{
int ret;
/*
* All Efika MX boards use eSDHC1 with a common write-protect GPIO
*/
imx_iomux_v3_setup_multiple_pads(efikamx_sdhc1_pads,
ARRAY_SIZE(efikamx_sdhc1_pads));
gpio_direction_input(EFIKAMX_SDHC1_WP);
/*
* Smartbook and Smarttop differ on the location of eSDHC1
* carrier-detect GPIO
*/
if (machine_is_efikamx()) {
imx_iomux_v3_setup_pad(efikamx_sdhc1_cd_pads[0]);
gpio_direction_input(EFIKAMX_SDHC1_CD);
} else if (machine_is_efikasb()) {
imx_iomux_v3_setup_pad(efikamx_sdhc1_cd_pads[1]);
gpio_direction_input(EFIKASB_SDHC1_CD);
}
esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
if (machine_is_efikasb()) {
imx_iomux_v3_setup_multiple_pads(efikasb_sdhc2_pads,
ARRAY_SIZE(efikasb_sdhc2_pads));
gpio_direction_input(EFIKASB_SDHC2_CD);
gpio_direction_input(EFIKASB_SDHC2_WP);
if (!ret)
ret = fsl_esdhc_initialize(bis, &esdhc_cfg[1]);
}
return ret;
}
int checkboard(void)
{
u32 rev = get_efika_rev();
if (machine_is_efikamx()) {
printf("Board: Efika MX, rev1.%i\n", rev & 0xf);
return 0;
} else {
switch (rev) {
case EFIKASB_BOARD_REV_13:
printf("Board: Efika SB rev1.3\n");
break;
case EFIKASB_BOARD_REV_20:
printf("Board: Efika SB rev2.0\n");
break;
default:
printf("Board: Efika SB, rev Unknown\n");
break;
}
}
return 0;
}
/*
* Board initialization
*/
int board_early_init_f(void)
{
if (machine_is_efikasb()) {
imx_iomux_v3_setup_multiple_pads(efikasb_led_pads,
ARRAY_SIZE(efikasb_led_pads));
gpio_direction_output(EFIKASB_CAPSLOCK_LED, 0);
gpio_direction_output(EFIKASB_MESSAGE_LED, 1);
} else if (machine_is_efikamx()) {
/*
* Set up GPIO directions for LEDs.
* IOMUX has been done in the DCD already.
* Turn the red LED on for pre-relocation code.
*/
gpio_direction_output(EFIKAMX_LED_BLUE, 0);
gpio_direction_output(EFIKAMX_LED_GREEN, 0);
gpio_direction_output(EFIKAMX_LED_RED, 1);
}
/*
* Both these pad configurations for UART and SPI are kind of redundant
* since they are the Power-On Defaults for the i.MX51. But, it seems we
* should make absolutely sure that they are set up correctly.
*/
imx_iomux_v3_setup_multiple_pads(efikamx_uart_pads,
ARRAY_SIZE(efikamx_uart_pads));
imx_iomux_v3_setup_multiple_pads(efikamx_spi_pads,
ARRAY_SIZE(efikamx_spi_pads));
/* not technically required for U-Boot operation but do it anyway. */
gpio_direction_input(EFIKAMX_PMIC_IRQ);
/* Deselect both CS for now, otherwise NOR doesn't probe properly. */
gpio_direction_output(EFIKAMX_SPI_SS0, 0);
gpio_direction_output(EFIKAMX_SPI_SS1, 1);
return 0;
}
/*
* LED configuration
*/
void setup_iomux_led(void)
{
if (machine_is_efikamx()) {
/* Blue LED */
mxc_request_iomux(MX51_PIN_CSI1_D9, IOMUX_CONFIG_ALT3);
gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9), 0);
/* Green LED */
mxc_request_iomux(MX51_PIN_CSI1_VSYNC, IOMUX_CONFIG_ALT3);
gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_VSYNC), 0);
/* Red LED */
mxc_request_iomux(MX51_PIN_CSI1_HSYNC, IOMUX_CONFIG_ALT3);
gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_HSYNC), 0);
} else {
/* CAPS-LOCK LED */
mxc_request_iomux(MX51_PIN_EIM_CS0, IOMUX_CONFIG_GPIO);
gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_CS0), 0);
/* ALARM-LED LED */
mxc_request_iomux(MX51_PIN_GPIO1_3, IOMUX_CONFIG_GPIO);
gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_GPIO1_3), 0);
}
}
int board_mmc_init(bd_t *bis)
{
int ret;
uint32_t cd = efika_mmc_cd();
/* SDHC1 is used on all revisions, setup control pins first */
mxc_request_iomux(cd,
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
mxc_iomux_set_pad(cd,
PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU |
PAD_CTL_ODE_OPENDRAIN_NONE |
PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
mxc_request_iomux(MX51_PIN_GPIO1_1,
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE |
PAD_CTL_SRE_FAST);
gpio_direction_input(IOMUX_TO_GPIO(cd));
gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_1));
/* Internal SDHC1 IOMUX + SDHC2 IOMUX on old boards */
if (machine_is_efikasb() || (machine_is_efikamx() &&
(get_efika_rev() < EFIKAMX_BOARD_REV_12))) {
/* SDHC1 IOMUX */
mxc_request_iomux(MX51_PIN_SD1_CMD,
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
mxc_request_iomux(MX51_PIN_SD1_CLK,
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
mxc_request_iomux(MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
mxc_request_iomux(MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
mxc_request_iomux(MX51_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
mxc_request_iomux(MX51_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
/* SDHC2 IOMUX */
mxc_request_iomux(MX51_PIN_SD2_CMD,
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
mxc_iomux_set_pad(MX51_PIN_SD2_CMD,
PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
mxc_request_iomux(MX51_PIN_SD2_CLK,
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
mxc_iomux_set_pad(MX51_PIN_SD2_CLK,
PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
mxc_request_iomux(MX51_PIN_SD2_DATA0, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX51_PIN_SD2_DATA0,
PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
mxc_request_iomux(MX51_PIN_SD2_DATA1, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX51_PIN_SD2_DATA1,
PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
mxc_request_iomux(MX51_PIN_SD2_DATA2, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX51_PIN_SD2_DATA2,
PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
mxc_request_iomux(MX51_PIN_SD2_DATA3, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX51_PIN_SD2_DATA3,
PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
/* SDHC2 Control lines IOMUX */
mxc_request_iomux(MX51_PIN_GPIO1_7,
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
mxc_iomux_set_pad(MX51_PIN_GPIO1_7,
PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU |
PAD_CTL_ODE_OPENDRAIN_NONE |
PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
mxc_request_iomux(MX51_PIN_GPIO1_8,
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
mxc_iomux_set_pad(MX51_PIN_GPIO1_8,
PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE |
PAD_CTL_SRE_FAST);
gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8));
gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_7));
ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
if (!ret)
ret = fsl_esdhc_initialize(bis, &esdhc_cfg[1]);
} else { /* New boards use only SDHC1 */
/* SDHC1 IOMUX */
mxc_request_iomux(MX51_PIN_SD1_CMD,
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
mxc_request_iomux(MX51_PIN_SD1_CLK,
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
mxc_request_iomux(MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
mxc_request_iomux(MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
mxc_request_iomux(MX51_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
mxc_request_iomux(MX51_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
}
return ret;
}
