static void __init mx51_efikamx_board_init(void)
{
mxc_cpu_common_init();
mxc_register_gpios();
CONFIG_IOMUX(mx51_efikamx_general_iomux_pins);
/* do ID pins first! */
if (machine_is_mx51_efikamx()) {
CONFIG_IOMUX(mx51_efikamx_id_iomux_pins);
} else if (machine_is_mx51_efikasb()) {
CONFIG_IOMUX(mx51_efikasb_id_iomux_pins);
CONFIG_IOMUX(mx51_efikasb_general_iomux_pins);
}
/* common platform configuration for all boards */
mx51_efikamx_init_uart();
mx51_efikamx_init_soc();
mx51_efikamx_init_nor();
mx51_efikamx_init_spi();
mx51_efikamx_init_i2c();
mx51_efikamx_init_pata();
/* we do board id late because it takes time to settle */
mx51_efikamx_board_id();
/* these all depend on board id */
mx51_efikamx_init_display();
mx51_efikamx_init_audio();
mx51_efikamx_init_pmic();
mx51_efikamx_init_mmc();
mx51_efikamx_init_leds();
mx51_efikamx_init_periph();
mx51_efikamx_init_usb();
pm_power_off = mx51_efikamx_power_off;
if (machine_is_mx51_efikamx()) {
mxc_free_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT2);
mxc_free_iomux(MX51_PIN_GPIO1_3, IOMUX_CONFIG_ALT2);
mxc_free_iomux(MX51_PIN_EIM_LBA, IOMUX_CONFIG_GPIO);
DBG(("Smarttop Revision 1.%u", mx51_efikamx_revision() ));
} else if (machine_is_mx51_efikasb()) {
mx51_efikamx_init_battery();
/* dastardly code to give us 1.3 or 2.0 out of "1" or "2" */
DBG(("Smartbook Revision %u.%u\n",
mx51_efikamx_revision(),
((mx51_efikamx_revision() == 1) ? 3 : 0) ));
DBG(("Memory type %s\n", mx51_efikamx_memory() ));
}
}
int __init mx51_efikamx_init_pmic(void)
{
CONFIG_IOMUX(mx51_efikamx_pmic_iomux_pins);
/* disable power gating for some reason */
if (machine_is_mx51_efikasb())
pmic_write_reg(REG_POWER_MISC, ~(PWGT1SPIEN|PWGT2SPIEN), (PWGT1SPIEN|PWGT2SPIEN));
if (machine_is_mx51_efikamx() && (mx51_efikamx_revision() == 1)) {
CONFIG_IOMUX(mx51_efikamx_watchdog_pins);
gpio_free(IOMUX_TO_GPIO(EFIKAMX_WATCHDOG_REBOOT));
gpio_request(IOMUX_TO_GPIO(EFIKAMX_WATCHDOG_REBOOT), "sys:reboot");
gpio_direction_output(IOMUX_TO_GPIO(EFIKAMX_WATCHDOG_REBOOT), 1);
} else {
CONFIG_IOMUX(mx51_efikasb_watchdog_pins);
gpio_free(IOMUX_TO_GPIO(EFIKASB_WATCHDOG_REBOOT));
gpio_request(IOMUX_TO_GPIO(EFIKASB_WATCHDOG_REBOOT), "sys:reboot");
gpio_direction_output(IOMUX_TO_GPIO(EFIKASB_WATCHDOG_REBOOT), 1);
if (machine_is_mx51_efikasb()) {
CONFIG_IOMUX(mx51_efikasb_power_pins);
gpio_free(IOMUX_TO_GPIO(EFIKASB_POWERGOOD));
gpio_request(IOMUX_TO_GPIO(EFIKASB_POWERGOOD), "sys:powergood");
gpio_direction_input(IOMUX_TO_GPIO(EFIKASB_POWERGOOD));
}
}
return spi_register_board_info(mc13892_spi_device, ARRAY_SIZE(mc13892_spi_device));
}
/*
* Reset the system. It is called by machine_restart().
*/
void arch_reset(char mode, const char *cmd)
{
unsigned int wcr_enable;
#ifdef CONFIG_ARCH_MX6
/* wait for reset to assert... */
wcr_enable = (1 << 2);
__raw_writew(wcr_enable, wdog_base);
/* errata TKT039676, SRS bit may be missed when
SRC sample it, need to write the wdog controller
twice to avoid it */
__raw_writew(wcr_enable, wdog_base);
/* wait for reset to assert... */
mdelay(500);
printk(KERN_ERR "Watchdog reset failed to assert reset\n");
return;
#endif
#ifdef CONFIG_ARCH_MXC91231
if (cpu_is_mxc91231()) {
mxc91231_arch_reset(mode, cmd);
return;
}
#endif
#ifdef CONFIG_MACH_MX51_EFIKAMX
if (machine_is_mx51_efikamx()) {
mx51_efikamx_reset();
return;
}
#endif
if (cpu_is_mx1()) {
wcr_enable = (1 << 0);
} else {
struct clk *clk;
clk = clk_get_sys("imx2-wdt.0", NULL);
if (!IS_ERR(clk))
clk_enable(clk);
wcr_enable = (1 << 2);
}
/* Assert SRS signal */
__raw_writew(wcr_enable, wdog_base);
/* wait for reset to assert... */
mdelay(500);
printk(KERN_ERR "Watchdog reset failed to assert reset\n");
/* delay to allow the serial port to show the message */
mdelay(50);
/* we'll take a jump through zero as a poor second */
cpu_reset(0);
}
int mx51_efikamx_revision(void)
{
if (machine_is_mx51_efikamx()) {
return(mx51_efikamx_id & 0xf);
} else if (machine_is_mx51_efikasb()) {
return(mx51_efikamx_id);
}
return 0;
}
void __init mx51_efikamx_init_leds(void)
{
if (machine_is_mx51_efikamx()) {
CONFIG_IOMUX(mx51_efikamx_led_iomux_pins);
/*
Request each color and set a default output.
Since Green is our power light by default, turn it on.
Since Red & Blue are disk activity, turn them off (the trigger will activate it)
*/
gpio_request(IOMUX_TO_GPIO(EFIKAMX_BLUE_LED), "blue_led");
gpio_direction_output(IOMUX_TO_GPIO(EFIKAMX_BLUE_LED), 0);
gpio_free(IOMUX_TO_GPIO(EFIKAMX_BLUE_LED));
gpio_request(IOMUX_TO_GPIO(EFIKAMX_GREEN_LED), "green_led");
gpio_direction_output(IOMUX_TO_GPIO(EFIKAMX_GREEN_LED), 1);
gpio_free(IOMUX_TO_GPIO(EFIKAMX_GREEN_LED));
gpio_request(IOMUX_TO_GPIO(EFIKAMX_RED_LED), "red_led");
gpio_direction_output(IOMUX_TO_GPIO(EFIKAMX_RED_LED), 0);
gpio_free(IOMUX_TO_GPIO(EFIKAMX_RED_LED));
if (mx51_efikamx_revision() >= 2)
{
/* on 1.2 and above there is no second SD controller,
* so the previous external "mmc1" is not valid anymore.
* change the trigger to mmc0 to activate the LED for
* the external slot for the newer boards
*/
mx51_efikamx_leds[2].default_trigger = "mmc0";
}
(void)platform_device_register(&mx51_efikamx_leds_device);
} else {
CONFIG_IOMUX(mx51_efikasb_led_iomux_pins);
gpio_request(IOMUX_TO_GPIO(EFIKASB_CAPSLOCK_LED), "led:capslock");
gpio_direction_output(IOMUX_TO_GPIO(EFIKASB_CAPSLOCK_LED), 0);
gpio_free(IOMUX_TO_GPIO(EFIKASB_CAPSLOCK_LED));
gpio_request(IOMUX_TO_GPIO(EFIKASB_ALARM_LED), "led:alarm");
gpio_direction_output(IOMUX_TO_GPIO(EFIKASB_ALARM_LED), 1);
gpio_free(IOMUX_TO_GPIO(EFIKASB_ALARM_LED));
gpio_request(IOMUX_TO_GPIO(EFIKASB_PWM_BACKLIGHT_EN), "backlight:en#");
gpio_direction_output(IOMUX_TO_GPIO(EFIKASB_PWM_BACKLIGHT_EN), 0);
mxc_register_device(&mxc_pwm1_device, NULL);
#if defined(CONFIG_BACKLIGHT_PWM)
mxc_register_device(&mxc_pwm_backlight_device, &mx51_efikasb_backlight_data);
#elif defined(CONFIG_LEDS_PWM)
(void)platform_device_register(&mx51_efikasb_backlight_device);
#endif
(void)platform_device_register(&mx51_efikasb_leds_device);
}
}
int mx51_efikamx_reboot(void)
{
if ( machine_is_mx51_efikamx() && (mx51_efikamx_revision() == 1) ) /* board rev1.1 */
gpio_direction_output(IOMUX_TO_GPIO(EFIKAMX_WATCHDOG_REBOOT), 0);
else
gpio_direction_output(IOMUX_TO_GPIO(EFIKASB_WATCHDOG_REBOOT), 0);
return 0;
}
static int __init mx51_efikamx_power_init(void)
{
if (machine_is_mx51_efikamx()) {
pwgt1 = regulator_get(NULL, "pwgt1");
pwgt2 = regulator_get(NULL, "pwgt2");
if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
regulator_enable(pwgt1);
regulator_enable(pwgt2);
}
gpio_request(EFIKAMX_POWEROFF, "poweroff");
pm_power_off = mx51_efikamx_power_off;
/* enable coincell charger. maybe need a small power driver ? */
coincell = regulator_get(NULL, "coincell");
if (!IS_ERR(coincell)) {
regulator_set_voltage(coincell, 3000000, 3000000);
regulator_enable(coincell);
}
regulator_has_full_constraints();
}
return 0;
}
/*
* Reset the system. It is called by machine_restart().
*/
void arch_reset(char mode, const char *cmd)
{
unsigned int wcr_enable;
#ifdef CONFIG_MACH_MX51_EFIKAMX
if (machine_is_mx51_efikamx()) {
mx51_efikamx_reset();
return;
}
#endif
if (cpu_is_mx1()) {
wcr_enable = (1 << 0);
} else {
struct clk *clk;
clk = clk_get_sys("imx2-wdt.0", NULL);
if (!IS_ERR(clk))
clk_enable(clk);
wcr_enable = (1 << 2);
}
/* Assert SRS signal */
__raw_writew(wcr_enable, wdog_base);
/* wait for reset to assert... */
mdelay(500);
printk(KERN_ERR "Watchdog reset failed to assert reset\n");
/* delay to allow the serial port to show the message */
mdelay(50);
/* we'll take a jump through zero as a poor second */
cpu_reset(0);
}
static int ehci_mxc_drv_probe(struct platform_device *pdev)
{
struct mxc_usbh_platform_data *pdata = pdev->dev.platform_data;
struct usb_hcd *hcd;
struct resource *res;
int irq, ret;
unsigned int flags;
struct ehci_mxc_priv *priv;
struct device *dev = &pdev->dev;
struct ehci_hcd *ehci;
dev_info(&pdev->dev, "initializing i.MX USB Controller\n");
if (!pdata) {
dev_err(dev, "No platform data given, bailing out.\n");
return -EINVAL;
}
irq = platform_get_irq(pdev, 0);
hcd = usb_create_hcd(&ehci_mxc_hc_driver, dev, dev_name(dev));
if (!hcd)
return -ENOMEM;
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
if (!priv) {
ret = -ENOMEM;
goto err_alloc;
}
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(dev, "Found HC with no register addr. Check setup!\n");
ret = -ENODEV;
goto err_get_resource;
}
hcd->rsrc_start = res->start;
hcd->rsrc_len = resource_size(res);
if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) {
dev_dbg(dev, "controller already in use\n");
ret = -EBUSY;
goto err_request_mem;
}
hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
if (!hcd->regs) {
dev_err(dev, "error mapping memory\n");
ret = -EFAULT;
goto err_ioremap;
}
/* enable clocks */
priv->usbclk = clk_get(dev, "usb");
if (IS_ERR(priv->usbclk)) {
ret = PTR_ERR(priv->usbclk);
goto err_clk;
}
clk_enable(priv->usbclk);
if (!cpu_is_mx35() && !cpu_is_mx25()) {
priv->ahbclk = clk_get(dev, "usb_ahb");
if (IS_ERR(priv->ahbclk)) {
ret = PTR_ERR(priv->ahbclk);
goto err_clk_ahb;
}
clk_enable(priv->ahbclk);
}
/* "dr" device has its own clock on i.MX51 */
if (cpu_is_mx51() && (pdev->id == 0)) {
priv->phy1clk = clk_get(dev, "usb_phy1");
if (IS_ERR(priv->phy1clk)) {
ret = PTR_ERR(priv->phy1clk);
goto err_clk_phy;
}
clk_enable(priv->phy1clk);
}
/* call platform specific init function */
if (pdata->init) {
ret = pdata->init(pdev);
if (ret) {
dev_err(dev, "platform init failed\n");
goto err_init;
}
/* platforms need some time to settle changed IO settings */
mdelay(10);
}
ehci = hcd_to_ehci(hcd);
/* EHCI registers start at offset 0x100 */
ehci->caps = hcd->regs + 0x100;
ehci->regs = hcd->regs + 0x100 +
HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
/* set up the PORTSCx register */
ehci_writel(ehci, pdata->portsc, &ehci->regs->port_status[0]);
/* is this really needed? */
msleep(10);
/* Initialize the transceiver */
if (pdata->otg) {
pdata->otg->io_priv = hcd->regs + ULPI_VIEWPORT_OFFSET;
ret = otg_init(pdata->otg);
if (ret) {
dev_err(dev, "unable to init transceiver, probably missing\n");
ret = -ENODEV;
goto err_add;
}
ret = otg_set_vbus(pdata->otg, 1);
if (ret) {
dev_err(dev, "unable to enable vbus on transceiver\n");
goto err_add;
}
}
priv->hcd = hcd;
platform_set_drvdata(pdev, priv);
ret = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED);
if (ret)
goto err_add;
if (pdata->otg) {
/*
* efikamx and efikasb have some hardware bug which is
* preventing usb to work unless CHRGVBUS is set.
* It's in violation of USB specs
*/
if (machine_is_mx51_efikamx() || machine_is_mx51_efikasb()) {
flags = otg_io_read(pdata->otg, ULPI_OTG_CTRL);
flags |= ULPI_OTG_CTRL_CHRGVBUS;
ret = otg_io_write(pdata->otg, flags, ULPI_OTG_CTRL);
if (ret) {
dev_err(dev, "unable to set CHRVBUS\n");
goto err_add;
}
}
}
return 0;
err_add:
if (pdata && pdata->exit)
pdata->exit(pdev);
err_init:
if (priv->phy1clk) {
clk_disable(priv->phy1clk);
clk_put(priv->phy1clk);
}
err_clk_phy:
if (priv->ahbclk) {
clk_disable(priv->ahbclk);
clk_put(priv->ahbclk);
}
err_clk_ahb:
clk_disable(priv->usbclk);
clk_put(priv->usbclk);
err_clk:
iounmap(hcd->regs);
err_ioremap:
release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
err_request_mem:
err_get_resource:
kfree(priv);
err_alloc:
usb_put_hcd(hcd);
return ret;
}
void mx51_efikamx_board_id(void)
{
if (machine_is_mx51_efikamx()) {
int pcbid[3];
mx51_efikamx_id = 0x10; /* can't get less than 1.0 */
/* NOTE:
IOMUX settings have to settle so run the iomux setup long before this
function has to otherwise it will give freakish results.
*/
gpio_request(IOMUX_TO_GPIO(EFIKAMX_PCBID0), "efikamx:pcbid0");
gpio_direction_input(IOMUX_TO_GPIO(EFIKAMX_PCBID0));
pcbid[0] = gpio_get_value(IOMUX_TO_GPIO(EFIKAMX_PCBID0));
gpio_request(IOMUX_TO_GPIO(EFIKAMX_PCBID1), "efikamx:pcbid1");
gpio_direction_input(IOMUX_TO_GPIO(EFIKAMX_PCBID1));
pcbid[1] = gpio_get_value(IOMUX_TO_GPIO(EFIKAMX_PCBID1));
gpio_request(IOMUX_TO_GPIO(EFIKAMX_PCBID2), "efikamx:pcbid2");
gpio_direction_input(IOMUX_TO_GPIO(EFIKAMX_PCBID2));
pcbid[2] = gpio_get_value(IOMUX_TO_GPIO(EFIKAMX_PCBID2));
/*
* PCBID2 PCBID1 PCBID0 STATE
* 1 1 1 ER1:rev1.1
* 1 1 0 ER2:rev1.2
* 1 0 1 ER3:rev1.3
* 1 0 0 ER4:rev1.4
*/
if (pcbid[2] == 1) {
if (pcbid[1] == 1) {
if (pcbid[0] == 1) {
mx51_efikamx_id = 0x11;
} else {
mx51_efikamx_id = 0x12;
}
} else {
if (pcbid[0] == 1) {
mx51_efikamx_id = 0x13;
} else {
mx51_efikamx_id = 0x14;
}
}
}
if ( (mx51_efikamx_id == 0x10) || /* "developer edition" */
(mx51_efikamx_id == 0x12) || /* unreleased, broken PATA */
(mx51_efikamx_id == 0x14) ) { /* unreleased.. */
DBG(("PCB Identification Error!\n"));
DBG(("Unsupported board revision 1.%u - USE AT YOUR OWN RISK!\n",
mx51_efikamx_revision() ));
}
} else if (machine_is_mx51_efikasb()) {
int pcbid[2], memid[2];
gpio_request(IOMUX_TO_GPIO(EFIKASB_MEMID0), "efikasb:memid0");
gpio_direction_input(IOMUX_TO_GPIO(EFIKASB_MEMID0));
memid[0] = gpio_get_value(IOMUX_TO_GPIO(EFIKASB_MEMID0));
gpio_request(IOMUX_TO_GPIO(EFIKASB_MEMID1), "efikasb:memid1");
gpio_direction_input(IOMUX_TO_GPIO(EFIKASB_MEMID1));
memid[1] = gpio_get_value(IOMUX_TO_GPIO(EFIKASB_MEMID1));
gpio_request(IOMUX_TO_GPIO(EFIKASB_PCBID0), "efikasb:pcbid0");
gpio_direction_input(IOMUX_TO_GPIO(EFIKASB_PCBID0));
pcbid[0] = gpio_get_value(IOMUX_TO_GPIO(EFIKASB_PCBID0));
gpio_request(IOMUX_TO_GPIO(EFIKASB_PCBID1), "efikasb:pcbid1");
gpio_direction_input(IOMUX_TO_GPIO(EFIKASB_PCBID1));
pcbid[1] = gpio_get_value(IOMUX_TO_GPIO(EFIKASB_PCBID1));
/*
* PCBID1 PCBID0 STATE
* 0 1 TO2: Revision 1.3
* 1 0 TO3: Revision 2.0
*/
/* gives us 0x1 or 0x2 */
mx51_efikamx_id = pcbid[0] | (pcbid[1] << 1);
mx51_efikamx_mem = memid[0] | (memid[1] << 1);
}
}
/*
* Reset the system. It is called by machine_restart().
*/
void arch_reset(char mode, const char *cmd)
{
unsigned int wcr_enable;
arch_reset_special_mode(mode, cmd);
#ifdef CONFIG_ARCH_MX6
/* wait for reset to assert... */
if (enable_ldo_mode == LDO_MODE_BYPASSED && !(machine_is_mx6sl_evk()
|| machine_is_mx6sl_arm2())) {
/*On Sabresd board use WDOG2 to reset external PMIC, so here do
* more WDOG2 reset.*/
wcr_enable = 0x04;//rudolph add for reboot. 0x14 --> 0x04 20150302
__raw_writew(wcr_enable, IO_ADDRESS(MX6Q_WDOG2_BASE_ADDR));
__raw_writew(wcr_enable, IO_ADDRESS(MX6Q_WDOG2_BASE_ADDR));
} else {
wcr_enable = (1 << 2);
__raw_writew(wcr_enable, wdog_base);
/* errata TKT039676, SRS bit may be missed when
SRC sample it, need to write the wdog controller
twice to avoid it */
__raw_writew(wcr_enable, wdog_base);
}
/* wait for reset to assert... */
mdelay(500);
printk(KERN_ERR "Watchdog reset failed to assert reset\n");
return;
#endif
#ifdef CONFIG_MACH_MX51_EFIKAMX
if (machine_is_mx51_efikamx()) {
mx51_efikamx_reset();
return;
}
#endif
#ifdef CONFIG_ARCH_MX51
/* Workaround to reset NFC_CONFIG3 register
* due to the chip warm reset does not reset it
*/
if (cpu_is_mx53())
__raw_writel(0x20600, MX53_IO_ADDRESS(MX53_NFC_BASE_ADDR)+0x28);
if (cpu_is_mx51())
__raw_writel(0x20600, MX51_IO_ADDRESS(MX51_NFC_BASE_ADDR)+0x28);
#endif
#ifdef CONFIG_ARCH_MX5
/* Stop DVFS-CORE before reboot. */
if (dvfs_core_is_active)
stop_dvfs();
#endif
if (cpu_is_mx1()) {
wcr_enable = (1 << 0);
} else {
struct clk *clk;
clk = clk_get_sys("imx2-wdt.0", NULL);
if (!IS_ERR(clk))
clk_enable(clk);
wcr_enable = (1 << 2);
}
/* Assert SRS signal */
__raw_writew(wcr_enable, wdog_base);
/* wait for reset to assert... */
mdelay(500);
printk(KERN_ERR "Watchdog reset failed to assert reset\n");
/* delay to allow the serial port to show the message */
mdelay(50);
/* we'll take a jump through zero as a poor second */
cpu_reset(0);
}
static int mc13892_regulator_init(struct mc13892 *mc13892)
{
unsigned int value, register_mask;
printk("Initializing regulators for Efika MX\n");
if (mxc_cpu_is_rev(CHIP_REV_2_0) < 0) {
sw2_init.constraints.state_mem.uV = 1100000;
} else if (mxc_cpu_is_rev(CHIP_REV_2_0) == 1) {
sw2_init.constraints.state_mem.uV = 1250000;
sw1_init.constraints.state_mem.uV = 1000000;
}
/* enable standby control for all regulators */
pmic_read_reg(REG_MODE_0, &value, 0xffffff);
value |= REG_MODE_0_ALL_MASK;
pmic_write_reg(REG_MODE_0, value, 0xffffff);
pmic_read_reg(REG_MODE_1, &value, 0xffffff);
value |= REG_MODE_1_ALL_MASK;
pmic_write_reg(REG_MODE_1, value, 0xffffff);
/* enable switch auto mode (ENGR00120510 ENGR00121057) */
pmic_read_reg(REG_IDENTIFICATION, &value, 0xffffff);
/* only for mc13892 2.0A */
if ((value & 0x0000FFFF) == 0x45d0) {
pmic_read_reg(REG_SW_4, &value, 0xffffff);
register_mask = (SWMODE_MASK << SW1MODE_LSB) |
(SWMODE_MASK << SW2MODE_LSB);
value &= ~register_mask;
value |= (SWMODE_AUTO << SW1MODE_LSB) |
(SWMODE_AUTO << SW2MODE_LSB);
pmic_write_reg(REG_SW_4, value, 0xffffff);
pmic_read_reg(REG_SW_5, &value, 0xffffff);
register_mask = (SWMODE_MASK << SW3MODE_LSB) |
(SWMODE_MASK << SW4MODE_LSB);
value &= ~register_mask;
value |= (SWMODE_AUTO << SW3MODE_LSB) |
(SWMODE_AUTO << SW4MODE_LSB);
pmic_write_reg(REG_SW_5, value, 0xffffff);
}
if (machine_is_mx51_efikamx()) {
/* Enable coin cell charger */
value = BITFVAL(COINCHEN, 1) | BITFVAL(VCOIN, VCOIN_3_0V);
register_mask = BITFMASK(COINCHEN) | BITFMASK(VCOIN);
pmic_write_reg(REG_POWER_CTL0, value, register_mask);
}
#if defined(CONFIG_RTC_DRV_MXC_V2) || defined(CONFIG_RTC_DRV_MXC_V2_MODULE)
value = BITFVAL(DRM, 1);
register_mask = BITFMASK(DRM);
pmic_write_reg(REG_POWER_CTL0, value, register_mask);
#endif
mc13892_register_regulator(mc13892, MC13892_SW1, &sw1_init);
mc13892_register_regulator(mc13892, MC13892_SW2, &sw2_init);
mc13892_register_regulator(mc13892, MC13892_SW3, &sw3_init);
mc13892_register_regulator(mc13892, MC13892_SW4, &sw4_init);
mc13892_register_regulator(mc13892, MC13892_SWBST, &swbst_init);
mc13892_register_regulator(mc13892, MC13892_VIOHI, &viohi_init);
mc13892_register_regulator(mc13892, MC13892_VPLL, &vpll_init);
mc13892_register_regulator(mc13892, MC13892_VDIG, &vdig_init);
mc13892_register_regulator(mc13892, MC13892_VSD, &vsd_init);
mc13892_register_regulator(mc13892, MC13892_VUSB2, &vusb2_init);
mc13892_register_regulator(mc13892, MC13892_VVIDEO, &vvideo_init);
mc13892_register_regulator(mc13892, MC13892_VAUDIO, &vaudio_init);
mc13892_register_regulator(mc13892, MC13892_VCAM, &vcam_init);
mc13892_register_regulator(mc13892, MC13892_VGEN1, &vgen1_init);
mc13892_register_regulator(mc13892, MC13892_VGEN2, &vgen2_init);
mc13892_register_regulator(mc13892, MC13892_VGEN3, &vgen3_init);
mc13892_register_regulator(mc13892, MC13892_VUSB, &vusb_init);
mc13892_register_regulator(mc13892, MC13892_GPO1, &gpo1_init);
mc13892_register_regulator(mc13892, MC13892_GPO2, &gpo2_init);
mc13892_register_regulator(mc13892, MC13892_GPO3, &gpo3_init);
mc13892_register_regulator(mc13892, MC13892_GPO4, &gpo4_init);
// regulator_has_full_constraints();
return 0;
}
