static void fsp_run_silicon_init(int is_s3_wakeup)
{
FSP_INFO_HEADER *fsp_info_header;
FSP_SILICON_INIT fsp_silicon_init;
SILICON_INIT_UPD *original_params;
SILICON_INIT_UPD silicon_init_params;
EFI_STATUS status;
UPD_DATA_REGION *upd_ptr;
VPD_DATA_REGION *vpd_ptr;
/* Find the FSP image */
fsp_info_header = fsp_get_fih();
if (fsp_info_header == NULL) {
printk(BIOS_ERR, "FSP_INFO_HEADER not set!\n");
return;
}
print_fsp_info(fsp_info_header);
/* Initialize the UPD values */
vpd_ptr = (VPD_DATA_REGION *)(fsp_info_header->CfgRegionOffset +
fsp_info_header->ImageBase);
printk(BIOS_DEBUG, "0x%p: VPD Data\n", vpd_ptr);
upd_ptr = (UPD_DATA_REGION *)(vpd_ptr->PcdUpdRegionOffset +
fsp_info_header->ImageBase);
printk(BIOS_DEBUG, "0x%p: UPD Data\n", upd_ptr);
original_params = (void *)((u8 *)upd_ptr +
upd_ptr->SiliconInitUpdOffset);
memcpy(&silicon_init_params, original_params,
sizeof(silicon_init_params));
soc_silicon_init_params(&silicon_init_params);
/* Locate VBT and pass to FSP GOP */
if (IS_ENABLED(CONFIG_GOP_SUPPORT))
load_vbt(is_s3_wakeup, &silicon_init_params);
mainboard_silicon_init_params(&silicon_init_params);
/* Display the UPD data */
if (IS_ENABLED(CONFIG_DISPLAY_UPD_DATA))
soc_display_silicon_init_params(original_params,
&silicon_init_params);
/* Perform silicon initialization after RAM is configured */
printk(BIOS_DEBUG, "Calling FspSiliconInit\n");
fsp_silicon_init = (FSP_SILICON_INIT)(fsp_info_header->ImageBase
+ fsp_info_header->FspSiliconInitEntryOffset);
timestamp_add_now(TS_FSP_SILICON_INIT_START);
printk(BIOS_DEBUG, "Calling FspSiliconInit(0x%p) at 0x%p\n",
&silicon_init_params, fsp_silicon_init);
status = fsp_silicon_init(&silicon_init_params);
timestamp_add_now(TS_FSP_SILICON_INIT_END);
printk(BIOS_DEBUG, "FspSiliconInit returned 0x%08x\n", status);
display_hob_info(fsp_info_header);
soc_after_silicon_init();
}
/* UPD parameters to be initialized before SiliconInit */
void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
{
int i;
FSP_S_CONFIG *params = &supd->FspsConfig;
FSP_S_TEST_CONFIG *tconfig = &supd->FspsTestConfig;
struct device *dev = SA_DEV_ROOT;
config_t *config = dev->chip_info;
/* Parse device tree and enable/disable devices */
parse_devicetree(params);
/* Load VBT before devicetree-specific config. */
params->GraphicsConfigPtr = (uintptr_t)vbt_get();
/* Set USB OC pin to 0 first */
for (i = 0; i < ARRAY_SIZE(params->Usb2OverCurrentPin); i++) {
params->Usb2OverCurrentPin[i] = 0;
}
for (i = 0; i < ARRAY_SIZE(params->Usb3OverCurrentPin); i++) {
params->Usb3OverCurrentPin[i] = 0;
}
mainboard_silicon_init_params(params);
/* Set PsysPmax if it is available from DT */
if (config->psys_pmax) {
printk(BIOS_DEBUG, "psys_pmax = %dW\n", config->psys_pmax);
/* PsysPmax is in unit of 1/8 Watt */
tconfig->PsysPmax = config->psys_pmax * 8;
}
/* Unlock upper 8 bytes of RTC RAM */
params->PchLockDownRtcMemoryLock = 0;
/* SATA */
dev = dev_find_slot(0, PCH_DEVFN_SATA);
if (!dev)
params->SataEnable = 0;
else {
params->SataEnable = dev->enabled;
params->SataMode = config->SataMode;
params->SataSalpSupport = config->SataSalpSupport;
memcpy(params->SataPortsEnable, config->SataPortsEnable,
sizeof(params->SataPortsEnable));
memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp,
sizeof(params->SataPortsDevSlp));
}
/* Lan */
dev = dev_find_slot(0, PCH_DEVFN_GBE);
if (!dev)
params->PchLanEnable = 0;
else {
params->PchLanEnable = dev->enabled;
if (config->s0ix_enable) {
params->SlpS0WithGbeSupport = 1;
params->PchPmSlpS0VmRuntimeControl = 0;
params->PchPmSlpS0Vm070VSupport = 0;
params->PchPmSlpS0Vm075VSupport = 0;
ignore_gbe_ltr();
}
}
/* Audio */
params->PchHdaDspEnable = config->PchHdaDspEnable;
params->PchHdaAudioLinkHda = config->PchHdaAudioLinkHda;
params->PchHdaAudioLinkDmic0 = config->PchHdaAudioLinkDmic0;
params->PchHdaAudioLinkDmic1 = config->PchHdaAudioLinkDmic1;
params->PchHdaAudioLinkSsp0 = config->PchHdaAudioLinkSsp0;
params->PchHdaAudioLinkSsp1 = config->PchHdaAudioLinkSsp1;
params->PchHdaAudioLinkSsp2 = config->PchHdaAudioLinkSsp2;
params->PchHdaAudioLinkSndw1 = config->PchHdaAudioLinkSndw1;
params->PchHdaAudioLinkSndw2 = config->PchHdaAudioLinkSndw2;
params->PchHdaAudioLinkSndw3 = config->PchHdaAudioLinkSndw3;
params->PchHdaAudioLinkSndw4 = config->PchHdaAudioLinkSndw4;
/* eDP device */
params->DdiPortEdp = config->DdiPortEdp;
/* HPD of DDI ports */
params->DdiPortBHpd = config->DdiPortBHpd;
params->DdiPortCHpd = config->DdiPortCHpd;
params->DdiPortDHpd = config->DdiPortDHpd;
params->DdiPortFHpd = config->DdiPortFHpd;
/* DDC of DDI ports */
params->DdiPortBDdc = config->DdiPortBDdc;
params->DdiPortCDdc = config->DdiPortCDdc;
params->DdiPortDDdc = config->DdiPortDDdc;
params->DdiPortFDdc = config->DdiPortFDdc;
/* S0ix */
params->PchPmSlpS0Enable = config->s0ix_enable;
/* disable Legacy PME */
memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));
/* USB */
for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
params->PortUsb20Enable[i] = config->usb2_ports[i].enable;
params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin;
params->Usb2AfePetxiset[i] = config->usb2_ports[i].pre_emp_bias;
params->Usb2AfeTxiset[i] = config->usb2_ports[i].tx_bias;
params->Usb2AfePredeemp[i] =
config->usb2_ports[i].tx_emp_enable;
params->Usb2AfePehalfbit[i] = config->usb2_ports[i].pre_emp_bit;
}
for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) {
params->PortUsb30Enable[i] = config->usb3_ports[i].enable;
params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;
if (config->usb3_ports[i].tx_de_emp) {
params->Usb3HsioTxDeEmphEnable[i] = 1;
params->Usb3HsioTxDeEmph[i] =
config->usb3_ports[i].tx_de_emp;
}
if (config->usb3_ports[i].tx_downscale_amp) {
params->Usb3HsioTxDownscaleAmpEnable[i] = 1;
params->Usb3HsioTxDownscaleAmp[i] =
config->usb3_ports[i].tx_downscale_amp;
}
}
/* Enable xDCI controller if enabled in devicetree and allowed */
dev = dev_find_slot(0, PCH_DEVFN_USBOTG);
if (!xdci_can_enable())
dev->enabled = 0;
params->XdciEnable = dev->enabled;
/* Set Debug serial port */
params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE;
/* Enable CNVi Wifi if enabled in device tree */
dev = dev_find_slot(0, PCH_DEVFN_CNViWIFI);
#if IS_ENABLED(CONFIG_SOC_INTEL_COMETLAKE)
params->CnviMode = dev->enabled;
#else
params->PchCnviMode = dev->enabled;
#endif
/* PCI Express */
for (i = 0; i < ARRAY_SIZE(config->PcieClkSrcUsage); i++) {
if (config->PcieClkSrcUsage[i] == 0)
config->PcieClkSrcUsage[i] = PCIE_CLK_NOTUSED;
}
memcpy(params->PcieClkSrcUsage, config->PcieClkSrcUsage,
sizeof(config->PcieClkSrcUsage));
memcpy(params->PcieClkSrcClkReq, config->PcieClkSrcClkReq,
sizeof(config->PcieClkSrcClkReq));
memcpy(params->PcieRpLtrEnable, config->PcieRpLtrEnable,
sizeof(config->PcieRpLtrEnable));
memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug,
sizeof(config->PcieRpHotPlug));
/* eMMC and SD */
dev = dev_find_slot(0, PCH_DEVFN_EMMC);
if (!dev)
params->ScsEmmcEnabled = 0;
else {
params->ScsEmmcEnabled = dev->enabled;
params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled;
params->PchScsEmmcHs400DllDataValid = config->EmmcHs400DllNeed;
if (config->EmmcHs400DllNeed == 1) {
params->PchScsEmmcHs400RxStrobeDll1 =
config->EmmcHs400RxStrobeDll1;
params->PchScsEmmcHs400TxDataDll =
config->EmmcHs400TxDataDll;
}
}
dev = dev_find_slot(0, PCH_DEVFN_SDCARD);
if (!dev) {
params->ScsSdCardEnabled = 0;
} else {
params->ScsSdCardEnabled = dev->enabled;
params->SdCardPowerEnableActiveHigh =
CONFIG(MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE);
}
dev = dev_find_slot(0, PCH_DEVFN_UFS);
if (!dev)
params->ScsUfsEnabled = 0;
else
params->ScsUfsEnabled = dev->enabled;
params->Heci3Enabled = config->Heci3Enabled;
params->Device4Enable = config->Device4Enable;
/* VrConfig Settings for 5 domains
* 0 = System Agent, 1 = IA Core, 2 = Ring,
* 3 = GT unsliced, 4 = GT sliced */
for (i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++)
fill_vr_domain_config(params, i, &config->domain_vr_config[i]);
/* Acoustic Noise Mitigation */
params->AcousticNoiseMitigation = config->AcousticNoiseMitigation;
params->SlowSlewRateForIa = config->SlowSlewRateForIa;
params->SlowSlewRateForGt = config->SlowSlewRateForGt;
params->SlowSlewRateForSa = config->SlowSlewRateForSa;
params->SlowSlewRateForFivr = config->SlowSlewRateForFivr;
params->FastPkgCRampDisableIa = config->FastPkgCRampDisableIa;
params->FastPkgCRampDisableGt = config->FastPkgCRampDisableGt;
params->FastPkgCRampDisableSa = config->FastPkgCRampDisableSa;
params->FastPkgCRampDisableFivr = config->FastPkgCRampDisableFivr;
/* Power Optimizer */
params->PchPwrOptEnable = config->dmipwroptimize;
params->SataPwrOptEnable = config->satapwroptimize;
/* Apply minimum assertion width settings if non-zero */
if (config->PchPmSlpS3MinAssert)
params->PchPmSlpS3MinAssert = config->PchPmSlpS3MinAssert;
if (config->PchPmSlpS4MinAssert)
params->PchPmSlpS4MinAssert = config->PchPmSlpS4MinAssert;
if (config->PchPmSlpSusMinAssert)
params->PchPmSlpSusMinAssert = config->PchPmSlpSusMinAssert;
if (config->PchPmSlpAMinAssert)
params->PchPmSlpAMinAssert = config->PchPmSlpAMinAssert;
/* Set TccActivationOffset */
tconfig->TccActivationOffset = config->tcc_offset;
/* Unlock all GPIO pads */
tconfig->PchUnlockGpioPads = config->PchUnlockGpioPads;
}
static void fsp_run_silicon_init(int is_s3_wakeup)
{
FSP_INFO_HEADER *fsp_info_header;
FSP_SILICON_INIT fsp_silicon_init;
SILICON_INIT_UPD *original_params;
SILICON_INIT_UPD silicon_init_params;
EFI_STATUS status;
UPD_DATA_REGION *upd_ptr;
VPD_DATA_REGION *vpd_ptr;
/* Find the FSP image */
fsp_info_header = fsp_get_fih();
if (fsp_info_header == NULL) {
printk(BIOS_ERR, "FSP_INFO_HEADER not set!\n");
return;
}
print_fsp_info(fsp_info_header);
/* Initialize the UPD values */
vpd_ptr = (VPD_DATA_REGION *)(fsp_info_header->CfgRegionOffset +
fsp_info_header->ImageBase);
printk(BIOS_DEBUG, "0x%p: VPD Data\n", vpd_ptr);
upd_ptr = (UPD_DATA_REGION *)(vpd_ptr->PcdUpdRegionOffset +
fsp_info_header->ImageBase);
printk(BIOS_DEBUG, "0x%p: UPD Data\n", upd_ptr);
original_params = (void *)((u8 *)upd_ptr +
upd_ptr->SiliconInitUpdOffset);
memcpy(&silicon_init_params, original_params,
sizeof(silicon_init_params));
soc_silicon_init_params(&silicon_init_params);
/* Locate VBT and pass to FSP GOP */
if (IS_ENABLED(CONFIG_GOP_SUPPORT))
load_vbt(is_s3_wakeup, &silicon_init_params);
mainboard_silicon_init_params(&silicon_init_params);
/* Display the UPD data */
if (IS_ENABLED(CONFIG_DISPLAY_UPD_DATA))
soc_display_silicon_init_params(original_params,
&silicon_init_params);
/* Perform silicon initialization after RAM is configured */
printk(BIOS_DEBUG, "Calling FspSiliconInit\n");
fsp_silicon_init = (FSP_SILICON_INIT)(fsp_info_header->ImageBase
+ fsp_info_header->FspSiliconInitEntryOffset);
timestamp_add_now(TS_FSP_SILICON_INIT_START);
printk(BIOS_DEBUG, "Calling FspSiliconInit(0x%p) at 0x%p\n",
&silicon_init_params, fsp_silicon_init);
status = fsp_silicon_init(&silicon_init_params);
timestamp_add_now(TS_FSP_SILICON_INIT_END);
printk(BIOS_DEBUG, "FspSiliconInit returned 0x%08x\n", status);
#if IS_ENABLED(CONFIG_DISPLAY_HOBS)
/* Verify the HOBs */
const EFI_GUID graphics_info_guid = EFI_PEI_GRAPHICS_INFO_HOB_GUID;
void *hob_list_ptr = get_hob_list();
int missing_hob = 0;
if (hob_list_ptr == NULL)
die("ERROR - HOB pointer is NULL!\n");
print_hob_type_structure(0, hob_list_ptr);
/*
* Verify that FSP is generating the required HOBs:
* 7.1: FSP_BOOTLOADER_TEMP_MEMORY_HOB only produced for FSP 1.0
* 7.2: FSP_RESERVED_MEMORY_RESOURCE_HOB verified by raminit
* 7.3: FSP_NON_VOLATILE_STORAGE_HOB verified by raminit
* 7.4: FSP_BOOTLOADER_TOLUM_HOB verified by raminit
* 7.5: EFI_PEI_GRAPHICS_INFO_HOB verified below,
* if the ImageAttribute bit is set
* FSP_SMBIOS_MEMORY_INFO HOB verified by raminit
*/
if ((fsp_info_header->ImageAttribute & GRAPHICS_SUPPORT_BIT) &&
!get_next_guid_hob(&graphics_info_guid, hob_list_ptr)) {
printk(BIOS_ERR, "7.5: EFI_PEI_GRAPHICS_INFO_HOB missing!\n");
missing_hob = 1;
}
if (missing_hob)
die("ERROR - Missing one or more required FSP HOBs!\n");
#endif
soc_after_silicon_init();
}
