/* gpi_sts is GPIO 47:32 */ void mainboard_smi_gpi(u32 gpi_sts) { if (gpi_sts & (1 << (EC_SMI_GPI - 32))) { /* Process all pending events */ while (mainboard_smi_ec() != 0); } }
/* The entire 32-bit ALT_GPIO_SMI register is passed as a parameter. Note, that * this includes the enable bits in the lower 16 bits. */ void mainboard_smi_gpi(uint32_t alt_gpio_smi) { if (alt_gpio_smi & (1 << EC_SMI_GPI)) { /* Process all pending events */ while (mainboard_smi_ec() != 0); } }
void mainboard_smi_gpi_handler(const struct gpi_status *sts) { if (gpi_status_get(sts, EC_SMI_GPI)) { /* Process all pending events */ while (mainboard_smi_ec() != 0) ; } }
/* * The entire 32-bit ALT_GPIO_SMI register is passed as a parameter. Note, that * this includes the enable bits in the lower 16 bits. */ void mainboard_smi_gpi(uint32_t alt_gpio_smi) { #if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) if (alt_gpio_smi & (1 << EC_SMI_GPI)) { /* Process all pending events */ while (mainboard_smi_ec() != 0) ; } #endif }
void mainboard_smi_gpi(u16 gpi_sts) { if (gpi_sts & (1 << EC_SMI_GPI)) { /* Process all pending EC requests */ ec_set_ports(EC_MAILBOX_PORT, EC_MAILBOX_PORT+1); while (mainboard_smi_ec() != 0xff); /* The EC may keep asserting SMI# for some * period unless we kick it here. */ send_ec_command(EC_SMI_DISABLE); send_ec_command(EC_SMI_ENABLE); } }
void mainboard_smi_gpi(u32 gpi_sts) { printk(BIOS_DEBUG, "mainboard_smi_gpi: %x\n", gpi_sts); if (gpi_sts & (1 << EC_SMI_GPI)) { /* Process all pending events from EC */ while (mainboard_smi_ec() != EC_NO_EVENT); } else if (gpi_sts & (1 << EC_LID_GPI)) { printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); #if CONFIG(ELOG_GSMI) elog_add_event_byte(ELOG_TYPE_EC_EVENT, EC_EVENT_LID_CLOSED); #endif /* Go to S5 */ write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) | (0xf << 10)); } }