static int reset_modem_trusted(struct pil_desc *pil)
{
int ret;
make_modem_proxy_votes();
ret = pas_auth_and_reset(PAS_MODEM);
if (ret)
remove_modem_proxy_votes_now();
return ret;
}
static int reset_modem_trusted(void)
{
int ret;
make_modem_proxy_votes();
ret = auth_and_reset_trusted(PAS_MODEM);
if (ret)
remove_modem_proxy_votes_now();
return ret;
}
static int modem_reset_trusted(struct pil_desc *pil)
{
int ret;
struct modem_data *drv = dev_get_drvdata(pil->dev);
make_modem_proxy_votes(pil->dev);
ret = pas_auth_and_reset(PAS_MODEM);
if (ret)
remove_modem_proxy_votes_now(drv);
return ret;
}
static int reset_modem_untrusted(struct pil_desc *pil)
{
u32 reg;
make_modem_proxy_votes();
/* Put modem AHB0,1,2 clocks into reset */
__raw_writel(BIT(0) | BIT(1), MAHB0_SFAB_PORT_RESET);
__raw_writel(BIT(7), MAHB1_CLK_CTL);
__raw_writel(BIT(7), MAHB2_CLK_CTL);
/* Vote for pll8 on behalf of the modem */
reg = __raw_readl(PLL_ENA_MARM);
reg |= BIT(8);
__raw_writel(reg, PLL_ENA_MARM);
/* Wait for PLL8 to enable */
while (!(__raw_readl(PLL8_STATUS) & BIT(16)))
cpu_relax();
/* Set MAHB1 divider to Div-5 to run MAHB1,2 and sfab at 79.8 Mhz*/
__raw_writel(0x4, MAHB1_NS);
/* Vote for modem AHB1 and 2 clocks to be on on behalf of the modem */
reg = __raw_readl(MARM_CLK_BRANCH_ENA_VOTE);
reg |= BIT(0) | BIT(1);
__raw_writel(reg, MARM_CLK_BRANCH_ENA_VOTE);
/* Source marm_clk off of PLL8 */
reg = __raw_readl(MARM_CLK_SRC_CTL);
if ((reg & 0x1) == 0) {
__raw_writel(0x3, MARM_CLK_SRC1_NS);
reg |= 0x1;
} else {
__raw_writel(0x3, MARM_CLK_SRC0_NS);
reg &= ~0x1;
}
__raw_writel(reg | 0x2, MARM_CLK_SRC_CTL);
/*
* Force core on and periph on signals to remain active during halt
* for marm_clk and mahb2_clk
*/
__raw_writel(0x6F, MARM_CLK_FS);
__raw_writel(0x6F, MAHB2_CLK_FS);
/*
* Enable all of the marm_clk branches, cxo sourced marm branches,
* and sleep clock branches
*/
__raw_writel(0x10, MARM_CLK_CTL);
__raw_writel(0x10, MAHB0_CLK_CTL);
__raw_writel(0x10, SFAB_MSS_S_HCLK_CTL);
__raw_writel(0x10, MSS_MODEM_CXO_CLK_CTL);
__raw_writel(0x10, MSS_SLP_CLK_CTL);
__raw_writel(0x10, MSS_MARM_SYS_REF_CLK_CTL);
/* Wait for above clocks to be turned on */
while (__raw_readl(CLK_HALT_MSS_SMPSS_MISC_STATE) & (BIT(7) | BIT(8) |
BIT(9) | BIT(10) | BIT(4) | BIT(6)))
cpu_relax();
/* Take MAHB0,1,2 clocks out of reset */
__raw_writel(0x0, MAHB2_CLK_CTL);
__raw_writel(0x0, MAHB1_CLK_CTL);
__raw_writel(0x0, MAHB0_SFAB_PORT_RESET);
/* Setup exception vector table base address */
__raw_writel(modem_start | 0x1, MARM_BOOT_CONTROL);
/* Wait for vector table to be setup */
mb();
/* Bring modem out of reset */
__raw_writel(0x0, MARM_RESET);
return 0;
}
