void mali_dev_restore(void)
{
#ifndef CONFIG_MALI_DVFS
mali_dvfs_threshold_table * pdvfs = pmali_plat->dvfs_table;
//mali_perf_set_num_pp_cores(num_cores_enabled);
mali_clock_set(pdvfs[currentStep].freq_index);
#endif
}
/* Fuction that platform callback for freq setting, needed when CONFIG_MALI_DVFS enabled */
int meson_platform_set_freq(int setting_clock_step) {
if (cur_gpu_clk_index == setting_clock_step) {
return 0;
}
mali_clock_set(setting_clock_step);
cur_gpu_clk_index = setting_clock_step;
printk("set cur_gpu_clk_index =%d\n", cur_gpu_clk_index);
return 0;
}
static void do_scaling(struct work_struct *work)
{
mali_dvfs_threshold_table * pdvfs = pmali_plat->dvfs_table;
int err = mali_perf_set_num_pp_cores(num_cores_enabled);
MALI_DEBUG_ASSERT(0 == err);
MALI_IGNORE(err);
if (pdvfs[currentStep].freq_index != pdvfs[lastStep].freq_index) {
mali_dev_pause();
mali_clock_set(pdvfs[currentStep].freq_index);
mali_dev_resume();
lastStep = currentStep;
}
#ifdef CONFIG_MALI400_PROFILING
_mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
MALI_PROFILING_EVENT_CHANNEL_GPU |
MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
get_current_frequency(),
0, 0, 0, 0);
#endif
}
int mali_clock_init(mali_plat_info_t* mali_plat)
{
u32 def_clk_data;
if (mali_plat == NULL) {
printk(" Mali platform data is NULL!!!\n");
return -1;
}
pmali_plat = mali_plat;
if (pmali_plat->have_switch) {
def_clk_data = pmali_plat->clk[pmali_plat->def_clock];
writel(def_clk_data | (def_clk_data << 16), (u32*)P_HHI_MALI_CLK_CNTL);
setbits_le32((u32)P_HHI_MALI_CLK_CNTL, 1 << 24);
setbits_le32((u32)P_HHI_MALI_CLK_CNTL, 1 << 8);
} else {
mali_clock_set(pmali_plat->def_clock);
}
mali_extr_backup = pmali_plat->clk[pmali_plat->clk_len - 1];
mali_extr_sample_backup = pmali_plat->clk_sample[pmali_plat->clk_len - 1];
return 0;
}
static inline void mali_clk_exected(void)
{
mali_dvfs_threshold_table * pdvfs = pmali_plat->dvfs_table;
uint32_t execStep = currentStep;
mali_dvfs_threshold_table *dvfs_tbl = &pmali_plat->dvfs_table[currentStep];
if (0 == strcmp(dvfs_tbl->clk_parent, "gp0_pll")) {
gp_pll_request(gp_pll_user_gpu);
if (!is_gp_pll_get) {
//printk("not get pll\n");
execStep = currentStep - 1;
}
} else {
//not get the gp pll, do need put
is_gp_pll_get = 0;
is_gp_pll_put = 0;
gp_pll_release(gp_pll_user_gpu);
}
//if (pdvfs[currentStep].freq_index == pdvfs[lastStep].freq_index) return;
if (pdvfs[execStep].freq_index == pdvfs[lastStep].freq_index) {
return;
}
//mali_dev_pause();
mali_clock_set(pdvfs[execStep].freq_index);
//mali_dev_resume();
lastStep = execStep;
if (is_gp_pll_put) {
//printk("release gp0 pll\n");
gp_pll_release(gp_pll_user_gpu);
gp_pll_request(gp_pll_user_gpu);
is_gp_pll_get = 0;
is_gp_pll_put = 0;
}
}
