/* * Masks and ACKs an IRQ */ static void level_mask_and_ack_msc_irq(unsigned int irq) { mask_msc_irq(irq); if (!cpu_has_veic) MSCIC_WRITE(MSC01_IC_EOI, 0); /* This actually needs to be a call into platform code */ smtc_im_ack_irq(irq); }
static void level_mask_and_ack_msc_irq(struct irq_data *d) { unsigned int irq = d->irq; mask_msc_irq(d); if (!cpu_has_veic) MSCIC_WRITE(MSC01_IC_EOI, 0); smtc_im_ack_irq(irq); }
/* * Masks and ACKs an IRQ */ static void level_mask_and_ack_msc_irq(unsigned int irq) { mask_msc_irq(irq); if (!cpu_has_veic) MSCIC_WRITE(MSC01_IC_EOI, 0); #ifdef CONFIG_MIPS_MT_SMTC /* This actually needs to be a call into platform code */ if (irq_hwmask[irq] & ST0_IM) set_c0_status(irq_hwmask[irq] & ST0_IM); #endif /* CONFIG_MIPS_MT_SMTC */ }
/* * Masks and ACKs an IRQ */ static void edge_mask_and_ack_msc_irq(unsigned int irq) { mask_msc_irq(irq); if (!cpu_has_veic) MSCIC_WRITE(MSC01_IC_EOI, 0); else { u32 r; MSCIC_READ(MSC01_IC_SUP+irq*8, r); MSCIC_WRITE(MSC01_IC_SUP+irq*8, r | ~MSC01_IC_SUP_EDGE_BIT); MSCIC_WRITE(MSC01_IC_SUP+irq*8, r); } smtc_im_ack_irq(irq); }
/* * Masks and ACKs an IRQ */ static void edge_mask_and_ack_msc_irq(unsigned int irq) { mask_msc_irq(irq); if (!cpu_has_veic) MSCIC_WRITE(MSC01_IC_EOI, 0); else { u32 r; MSCIC_READ(MSC01_IC_SUP+irq*8, r); MSCIC_WRITE(MSC01_IC_SUP+irq*8, r | ~MSC01_IC_SUP_EDGE_BIT); MSCIC_WRITE(MSC01_IC_SUP+irq*8, r); } #ifdef CONFIG_MIPS_MT_SMTC if (irq_hwmask[irq] & ST0_IM) set_c0_status(irq_hwmask[irq] & ST0_IM); #endif /* CONFIG_MIPS_MT_SMTC */ }
/* * Disables the IRQ on SOC-it */ static void disable_msc_irq(unsigned int irq) { mask_msc_irq(irq); }