static void max14577_muic_set_adcdbset(struct max14577_muic_data *muic_data,
int value)
{
int ret;
u8 val;
u8 cntl3_before, cntl3_after;
if (value > 3) {
pr_err("%s:%s invalid value(%d)\n", MUIC_DEV_NAME, __func__,
value);
return;
}
if (!muic_data->i2c) {
pr_err("%s:%s no muic i2c client\n", MUIC_DEV_NAME, __func__);
return;
}
val = (value << CTRL3_ADCDBSET_SHIFT);
max14577_read_reg(muic_data->i2c, MAX14577_MUIC_REG_CONTROL3,
&cntl3_before);
ret = max14577_write_reg(muic_data->i2c, MAX14577_MUIC_REG_CONTROL3,
val);
if (ret < 0)
pr_err("%s: fail to write reg\n", __func__);
max14577_read_reg(muic_data->i2c, MAX14577_MUIC_REG_CONTROL3,
&cntl3_after);
pr_info("%s:%s CNTL3: before(0x%02x), value(0x%02x), after(0x%02x)\n",
MUIC_DEV_NAME, __func__, cntl3_before, val, cntl3_after);
}
static int write_muic_ctrl_reg(struct max14577_muic_data *muic_data,
const u8 reg, const u8 val)
{
struct i2c_client *i2c = muic_data->i2c;
int ret = 0;
u8 reg_val = 0;
ret = max14577_read_reg(i2c, reg, ®_val);
if (ret < 0)
pr_err("%s:%s err read REG(0x%02x) [%d]\n", MUIC_DEV_NAME,
__func__, reg, ret);
if (reg_val ^ val) {
pr_info("%s:%s overwrite REG(0x%02x) from [0x%x] to [0x%x]\n",
MUIC_DEV_NAME, __func__, reg, reg_val, val);
ret = max14577_write_reg(i2c, reg, val);
if (ret < 0)
pr_err("%s:%s err write REG(0x%02x)\n", MUIC_DEV_NAME,
__func__, reg);
} else {
pr_info("%s:%s REG(0x%02x) already [0x%x], just return\n",
MUIC_DEV_NAME, __func__, reg, reg_val);
}
ret = max14577_read_reg(i2c, reg, ®_val);
if (ret < 0)
pr_err("%s:%s err read REG(0x%02x) [%d]\n", MUIC_DEV_NAME,
__func__, reg, ret);
else
pr_info("%s:%s REG(0x%02x) after change [0x%x]\n", MUIC_DEV_NAME,
__func__, reg, reg_val);
return ret;
}
static void max14577_irq_sync_unlock(struct irq_data *data)
{
struct max14577_dev *max14577 = irq_get_chip_data(data->irq);
struct i2c_client *i2c = max14577->i2c;
int i;
for (i = 0; i < MAX14577_IRQ_REGS_NUM; i++) {
u8 mask_reg = max14577_mask_reg[i];
if (mask_reg == MAX14577_REG_INVALID ||
IS_ERR_OR_NULL(i2c))
continue;
max14577->irq_masks_cache[i] = max14577->irq_masks_cur[i];
max14577_write_reg(i2c, max14577_mask_reg[i],
max14577->irq_masks_cur[i]);
}
mutex_unlock(&max14577->irq_lock);
}
ssize_t sec_hal_chg_store_attrs(struct device *dev,
const ptrdiff_t offset,
const char *buf, size_t count)
{
struct power_supply *psy = dev_get_drvdata(dev);
struct sec_charger_info *chg =
container_of(psy, struct sec_charger_info, psy_chg);
int ret = 0;
int x = 0;
u8 data = 0;
switch (offset) {
case CHG_REG:
if (sscanf(buf, "%x\n", &x) == 1) {
chg->reg_addr = x;
max14577_read_reg(chg->client,
chg->reg_addr, &data);
chg->reg_data = data;
dev_dbg(dev, "%s: (read) addr = 0x%x, data = 0x%x\n",
__func__, chg->reg_addr, chg->reg_data);
ret = count;
}
break;
case CHG_DATA:
if (sscanf(buf, "%x\n", &x) == 1) {
data = (u8)x;
dev_dbg(dev, "%s: (write) addr = 0x%x, data = 0x%x\n",
__func__, chg->reg_addr, data);
max14577_write_reg(chg->client,
chg->reg_addr, data);
ret = count;
}
break;
default:
ret = -EINVAL;
break;
}
return ret;
}
static void max14577_set_command(struct sec_charger_info *charger,
int reg, int datum)
{
int val;
u8 data = 0;
val = max14577_read_reg(charger->client, (u8)reg, &data);
if (val >= 0) {
dev_dbg(&charger->client->dev, "%s : reg(0x%02x): 0x%02x",
__func__, reg, data);
if (data != datum) {
data = datum;
if (max14577_write_reg(charger->client,
(u8)reg, data) < 0)
dev_err(&charger->client->dev,
"%s : error!\n", __func__);
val = max14577_read_reg(charger->client,
(u8)reg, &data);
if (val >= 0)
dev_dbg(&charger->client->dev,
" => 0x%02x\n", data);
}
}
}
int max14577_irq_init(struct max14577_dev *max14577)
{
struct max14577_platform_data *pdata = max14577->pdata;
struct i2c_client *i2c = max14577->i2c;
int i;
int cur_irq;
int ret;
if (!pdata->irq_gpio) {
pr_warn("%s:%s No interrupt specified.\n", MFD_DEV_NAME,
__func__);
pdata->irq_base = 0;
return 0;
}
if (!pdata->irq_base) {
pr_err("%s:%s No interrupt base specified.\n", MFD_DEV_NAME,
__func__);
return 0;
}
mutex_init(&max14577->irq_lock);
max14577->irq = gpio_to_irq(pdata->irq_gpio);
ret = gpio_request(pdata->irq_gpio, "max14577_irq");
if (ret) {
pr_err("%s:%s failed requesting gpio(%d)\n", MFD_DEV_NAME,
__func__, pdata->irq_gpio);
return ret;
}
gpio_direction_input(pdata->irq_gpio);
gpio_free(pdata->irq_gpio);
pr_info("%s:%s\n", MFD_DEV_NAME, __func__);
#ifdef CONFIG_MFD_MAX77836
/* MAX77836 INTSRC for MUIC UNMASK */
max14577_write_reg(max14577->i2c_pmic,
MAX77836_PMIC_REG_INTSRC_MASK, 0xF7);
#endif
/* Mask individual interrupt sources */
for (i = 0; i < MAX14577_IRQ_REGS_NUM; i++) {
/* IRQ 0:MASK 1:NOT MASK */
max14577->irq_masks_cur[i] = 0x00;
max14577->irq_masks_cache[i] = 0x00;
if (IS_ERR_OR_NULL(i2c))
continue;
if (max14577_mask_reg[i] == MAX14577_REG_INVALID)
continue;
max14577_write_reg(i2c, max14577_mask_reg[i],
max14577->irq_masks_cur[i]);
}
/* Register with genirq */
for (i = 0; i < MAX14577_IRQ_NUM; i++) {
cur_irq = i + pdata->irq_base;
irq_set_chip_data(cur_irq, max14577);
irq_set_chip_and_handler(cur_irq, &max14577_irq_chip,
handle_edge_irq);
irq_set_nested_thread(cur_irq, true);
#ifdef CONFIG_ARM
set_irq_flags(cur_irq, IRQF_VALID);
#else
irq_set_noprobe(cur_irq);
#endif
}
ret = request_threaded_irq(max14577->irq, NULL, max14577_irq_thread,
IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
"max14577-irq", max14577);
if (ret) {
pr_err("%s:%s Failed to request IRQ(%d) ret(%d)\n",
MFD_DEV_NAME, __func__, max14577->irq, ret);
return ret;
}
return 0;
}
int max14577_set_control2_reg(struct i2c_client *i2c, u8 val)
{
pr_info("%s:%s(0x%02x)\n", MFD_DEV_NAME, __func__, val);
return max14577_write_reg(i2c, MAX14577_REG_CONTROL2, val);
}
int max14577_set_cdetctrl1_reg(struct i2c_client *i2c, u8 val)
{
pr_info("%s:%s(0x%02x)\n", MFD_DEV_NAME, __func__, val);
return max14577_write_reg(i2c, MAX14577_REG_CDETCTRL1, val);
}
