/* * get_clocks() fills in gd->cpu_clock and gd->bus_clk */ int get_clocks (void) { #if defined(CONFIG_M5249) || defined(CONFIG_M5253) volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR); unsigned long pllcr; #ifndef CFG_PLL_BYPASS #ifdef CONFIG_M5249 /* Setup the PLL to run at the specified speed */ #ifdef CFG_FAST_CLK pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */ #else pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */ #endif #endif /* CONFIG_M5249 */ #ifdef CONFIG_M5253 pllcr = CFG_PLLCR; #endif /* CONFIG_M5253 */ cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */ mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */ mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */ pllcr ^= 0x00000001; /* Set pll bypass to 1 */ mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */ udelay(0x20); /* Wait for a lock ... */ #endif /* #ifndef CFG_PLL_BYPASS */ #endif /* CONFIG_M5249 || CONFIG_M5253 */ #if defined(CONFIG_M5275) volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL); /* Setup PLL */ pll->syncr = 0x01080000; while (!(pll->synsr & FMPLL_SYNSR_LOCK)) ; pll->syncr = 0x01000000; while (!(pll->synsr & FMPLL_SYNSR_LOCK)) ; #endif gd->cpu_clk = CFG_CLK; #if defined(CONFIG_M5249) || defined(CONFIG_M5253) || defined(CONFIG_M5275) gd->bus_clk = gd->cpu_clk / 2; #else gd->bus_clk = gd->cpu_clk; #endif #ifdef CONFIG_FSL_I2C gd->i2c1_clk = gd->bus_clk; #ifdef CFG_I2C2_OFFSET gd->i2c2_clk = gd->bus_clk; #endif #endif return (0); }
/* * Breath some life into the CPU... * * Set up the memory map, * initialize a bunch of registers, * initialize the UPM's */ void cpu_init_f(void) { /* * NOTE: by setting the GPIO_FUNCTION registers, we ensure that the UART pins * (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins * which is their primary function. * ~Jeremy */ mbar2_writeLong(MCFSIM_GPIO_FUNC, CONFIG_SYS_GPIO_FUNC); mbar2_writeLong(MCFSIM_GPIO1_FUNC, CONFIG_SYS_GPIO1_FUNC); mbar2_writeLong(MCFSIM_GPIO_EN, CONFIG_SYS_GPIO_EN); mbar2_writeLong(MCFSIM_GPIO1_EN, CONFIG_SYS_GPIO1_EN); mbar2_writeLong(MCFSIM_GPIO_OUT, CONFIG_SYS_GPIO_OUT); mbar2_writeLong(MCFSIM_GPIO1_OUT, CONFIG_SYS_GPIO1_OUT); /* * dBug Compliance: * You can verify these values by using dBug's 'ird' * (Internal Register Display) command * ~Jeremy * */ mbar_writeByte(MCFSIM_MPARK, 0x30); /* 5249 Internal Core takes priority over DMA */ mbar_writeByte(MCFSIM_SYPCR, 0x00); mbar_writeByte(MCFSIM_SWIVR, 0x0f); mbar_writeByte(MCFSIM_SWSR, 0x00); mbar_writeLong(MCFSIM_IMR, 0xfffffbff); mbar_writeByte(MCFSIM_SWDICR, 0x00); mbar_writeByte(MCFSIM_TIMER1ICR, 0x00); mbar_writeByte(MCFSIM_TIMER2ICR, 0x88); mbar_writeByte(MCFSIM_I2CICR, 0x00); mbar_writeByte(MCFSIM_UART1ICR, 0x00); mbar_writeByte(MCFSIM_UART2ICR, 0x00); mbar_writeByte(MCFSIM_ICR6, 0x00); mbar_writeByte(MCFSIM_ICR7, 0x00); mbar_writeByte(MCFSIM_ICR8, 0x00); mbar_writeByte(MCFSIM_ICR9, 0x00); mbar_writeByte(MCFSIM_QSPIICR, 0x00); mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080); mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */ mbar2_writeByte(MCFSIM_SPURVEC, 0x00); mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); /* Enable a 1 cycle pre-drive cycle on CS1 */ /* Setup interrupt priorities for gpio7 */ /* mbar2_writeLong(MCFSIM_INTLEV5, 0x70000000); */ /* IDE Config registers */ mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); mbar2_writeLong(MCFSIM_IDECONFIG2, 0x00000000); /* FlexBus Chipselect */ init_fbcs(); /* enable instruction cache now */ icache_enable(); }
/* * Breath some life into the CPU... * * Set up the memory map, * initialize a bunch of registers, * initialize the UPM's */ void cpu_init_f(void) { mbar_writeByte(MCFSIM_MPARK, 0x40); /* 5249 Internal Core takes priority over DMA */ mbar_writeByte(MCFSIM_SYPCR, 0x00); mbar_writeByte(MCFSIM_SWIVR, 0x0f); mbar_writeByte(MCFSIM_SWSR, 0x00); mbar_writeByte(MCFSIM_SWDICR, 0x00); mbar_writeByte(MCFSIM_TIMER1ICR, 0x00); mbar_writeByte(MCFSIM_TIMER2ICR, 0x88); mbar_writeByte(MCFSIM_I2CICR, 0x00); mbar_writeByte(MCFSIM_UART1ICR, 0x00); mbar_writeByte(MCFSIM_UART2ICR, 0x00); mbar_writeByte(MCFSIM_ICR6, 0x00); mbar_writeByte(MCFSIM_ICR7, 0x00); mbar_writeByte(MCFSIM_ICR8, 0x00); mbar_writeByte(MCFSIM_ICR9, 0x00); mbar_writeByte(MCFSIM_QSPIICR, 0x00); mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080); mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */ mbar2_writeByte(MCFSIM_SPURVEC, 0x00); /*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); */ /* Enable a 1 cycle pre-drive cycle on CS1 */ /* FlexBus Chipselect */ init_fbcs(); #ifdef CONFIG_FSL_I2C CONFIG_SYS_I2C_PINMUX_REG = CONFIG_SYS_I2C_PINMUX_REG & CONFIG_SYS_I2C_PINMUX_CLR; CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET; #ifdef CONFIG_SYS_I2C2_OFFSET CONFIG_SYS_I2C2_PINMUX_REG &= CONFIG_SYS_I2C2_PINMUX_CLR; CONFIG_SYS_I2C2_PINMUX_REG |= CONFIG_SYS_I2C2_PINMUX_SET; #endif #endif /* enable instruction cache now */ icache_enable(); }
/* * Breath some life into the CPU... * * Set up the memory map, * initialize a bunch of registers, * initialize the UPM's */ void cpu_init_f (void) { #ifndef CFG_PLL_BYPASS /* * Setup the PLL to run at the specified speed * */ volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR); unsigned long pllcr; #ifdef CFG_FAST_CLK pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */ #else pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */ #endif cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */ mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */ mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */ pllcr ^= 0x00000001; /* Set pll bypass to 1 */ mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */ udelay(0x20); /* Wait for a lock ... */ #endif /* #ifndef CFG_PLL_BYPASS */ /* * NOTE: by setting the GPIO_FUNCTION registers, we ensure that the UART pins * (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins * which is their primary function. * ~Jeremy */ mbar2_writeLong(MCFSIM_GPIO_FUNC, CFG_GPIO_FUNC); mbar2_writeLong(MCFSIM_GPIO1_FUNC, CFG_GPIO1_FUNC); mbar2_writeLong(MCFSIM_GPIO_EN, CFG_GPIO_EN); mbar2_writeLong(MCFSIM_GPIO1_EN, CFG_GPIO1_EN); mbar2_writeLong(MCFSIM_GPIO_OUT, CFG_GPIO_OUT); mbar2_writeLong(MCFSIM_GPIO1_OUT, CFG_GPIO1_OUT); /* * dBug Compliance: * You can verify these values by using dBug's 'ird' * (Internal Register Display) command * ~Jeremy * */ mbar_writeByte(MCFSIM_MPARK, 0x30); /* 5249 Internal Core takes priority over DMA */ mbar_writeByte(MCFSIM_SYPCR, 0x00); mbar_writeByte(MCFSIM_SWIVR, 0x0f); mbar_writeByte(MCFSIM_SWSR, 0x00); mbar_writeLong(MCFSIM_IMR, 0xfffffbff); mbar_writeByte(MCFSIM_SWDICR, 0x00); mbar_writeByte(MCFSIM_TIMER1ICR, 0x00); mbar_writeByte(MCFSIM_TIMER2ICR, 0x88); mbar_writeByte(MCFSIM_I2CICR, 0x00); mbar_writeByte(MCFSIM_UART1ICR, 0x00); mbar_writeByte(MCFSIM_UART2ICR, 0x00); mbar_writeByte(MCFSIM_ICR6, 0x00); mbar_writeByte(MCFSIM_ICR7, 0x00); mbar_writeByte(MCFSIM_ICR8, 0x00); mbar_writeByte(MCFSIM_ICR9, 0x00); mbar_writeByte(MCFSIM_QSPIICR, 0x00); mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080); mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */ mbar2_writeByte(MCFSIM_SPURVEC, 0x00); mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); /* Enable a 1 cycle pre-drive cycle on CS1 */ /* Setup interrupt priorities for gpio7 */ /* mbar2_writeLong(MCFSIM_INTLEV5, 0x70000000); */ /* IDE Config registers */ mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); mbar2_writeLong(MCFSIM_IDECONFIG2, 0x00000000); /* * Setup chip selects... */ mbar_writeShort(MCFSIM_CSAR1, CFG_CSAR1); mbar_writeShort(MCFSIM_CSCR1, CFG_CSCR1); mbar_writeLong(MCFSIM_CSMR1, CFG_CSMR1); mbar_writeShort(MCFSIM_CSAR0, CFG_CSAR0); mbar_writeShort(MCFSIM_CSCR0, CFG_CSCR0); mbar_writeLong(MCFSIM_CSMR0, CFG_CSMR0); /* enable instruction cache now */ icache_enable(); }
int FpgaIspInit (void) { #ifdef __uClinux__ uint32_t dwReg; // set initial data dwReg = mbar2_readLong(MCFSIM2_GPIOWRITE); dwReg = dwReg & ~ISP_TCK; mbar2_writeLong(MCFSIM2_GPIOWRITE, dwReg); dwReg = mbar2_readLong(MCFSIM2_GPIO1WRITE); dwReg = dwReg & ~(ISP_TMS|ISP_TDI); mbar2_writeLong(MCFSIM2_GPIO1WRITE, dwReg); // set port directions 1 = output dwReg = mbar2_readLong(MCFSIM2_GPIOENABLE); dwReg = dwReg | ISP_TCK; mbar2_writeLong(MCFSIM2_GPIOENABLE, dwReg); dwReg = mbar2_readLong(MCFSIM2_GPIO1ENABLE); dwReg = (dwReg | (ISP_TMS|ISP_TDI)) | (dwReg & ~ISP_TDO); mbar2_writeLong(MCFSIM2_GPIO1ENABLE, dwReg); // set port function 1 = gpio dwReg = mbar2_readLong(MCFSIM2_GPIOFUNC); dwReg = dwReg | ISP_TCK; mbar2_writeLong(MCFSIM2_GPIOFUNC, dwReg); dwReg = mbar2_readLong(MCFSIM2_GPIO1FUNC); dwReg = dwReg | (ISP_TMS|ISP_TDI|ISP_TDO); mbar2_writeLong(MCFSIM2_GPIO1FUNC, dwReg); #else if(g_gpiomap) { printf("FPGA programming interface is already initialized!\n"); return 0; } g_pgsize = getpagesize(); g_pgnumber = (int)ceil((double)(MAP_MASK + 1) / (double)g_pgsize); #if defined(AF_MINI) || defined(AF_MINI_REVA) || defined(BEAGLE_BONE) || defined(BEAGLE_BONE_REVA1) /* make sure that pads are configured correctly */ void* configmap; volatile unsigned int* pad_conf; g_memfiledesc = open("/dev/mem", O_RDWR | O_SYNC); if (g_memfiledesc < 0) { perror("open(\"/dev/mem\")"); return errno; } configmap = mmap(0, g_pgnumber * g_pgsize, PROT_READ | PROT_WRITE, MAP_SHARED, g_memfiledesc, AM335X_CONF_BASE & ~MAP_MASK); if (MAP_FAILED == configmap) { perror("mmap()"); close(g_memfiledesc); return errno; } printf("Configuring pads\n"); pad_conf = (unsigned int *) ((char *) configmap + AM335X_TMS); *pad_conf = 0x00000047; pad_conf = (unsigned int *) ((char *) configmap + AM335X_TDI); *pad_conf = 0x00000047; pad_conf = (unsigned int *) ((char *) configmap + AM335X_TCK); *pad_conf = 0x00000047; pad_conf = (unsigned int *) ((char *) configmap + AM335X_TDO); *pad_conf = 0x00000067; /* unmap SCM registers memory */ if (0 != munmap(configmap, (size_t) (g_pgnumber * g_pgsize))) { perror("munmap()"); close(g_memfiledesc); return errno; } #if defined(BEAGLE_BONE) || defined(BEAGLE_BONE_REVA1) /* make sure GPIO3 module's clock is enabled */ configmap = mmap(0, g_pgnumber * g_pgsize, PROT_READ | PROT_WRITE, MAP_SHARED, g_memfiledesc, AM335X_CM_PER & ~MAP_MASK); if (MAP_FAILED == configmap) { perror("mmap()"); close(g_memfiledesc); return errno; } pad_conf = (unsigned int *) ((char *) configmap + GPIO3_CLK_CTRL); printf("GPIO3_CLKCTRL init value: 0x%08x\n", *pad_conf); *pad_conf |= 0x00000002; // enable clock printf("GPIO3_CLKCTRL new value: 0x%08x\n", *pad_conf); if (0 != munmap(configmap, (size_t) (g_pgnumber * g_pgsize))) { perror("munmap()"); close(g_memfiledesc); return errno; } #endif close(g_memfiledesc); #endif g_memfiledesc = open("/dev/mem", O_RDWR | O_SYNC); if (g_memfiledesc < 0) { perror("open(\"/dev/mem\")"); return errno; } g_gpiomap = mmap(0, g_pgnumber * g_pgsize, PROT_READ | PROT_WRITE, MAP_SHARED, g_memfiledesc, GPIO_BASE_ADDR & ~MAP_MASK); if (MAP_FAILED == g_gpiomap) { perror("mmap()"); close(g_memfiledesc); return errno; } #if defined(BEAGLE_BONE) || defined(BEAGLE_BONE_REVA1) g_gpiomap3 = mmap(0, g_pgnumber * g_pgsize, PROT_READ | PROT_WRITE, MAP_SHARED, g_memfiledesc, GPIO_BASE_ADDR3 & ~MAP_MASK); if (MAP_FAILED == g_gpiomap3) { perror("mmap() 3"); close(g_memfiledesc); return errno; } #endif //disable wake-up and interrupt requests on GPIO pins writeTmsRegister(GPIO_CLEARIRQENABLE1, ISP_TMS); writeTmsRegister(GPIO_CLEARIRQENABLE2, ISP_TMS); writeTdoRegister(GPIO_CLEARIRQENABLE1, ISP_TDO); writeTdoRegister(GPIO_CLEARIRQENABLE2, ISP_TDO); writeTckRegister(GPIO_CLEARIRQENABLE1, ISP_TCK); writeTckRegister(GPIO_CLEARIRQENABLE2, ISP_TCK); writeTdiRegister(GPIO_CLEARIRQENABLE1, ISP_TDI); writeTdiRegister(GPIO_CLEARIRQENABLE2, ISP_TDI); #if !defined(AF_MINI) && !defined(AF_MINI_REVA) && !defined(BEAGLE_BONE) && !defined(BEAGLE_BONE_REVA1) writeTmsRegister(GPIO_CLEARWKUENA, ISP_TMS); writeTckRegister(GPIO_CLEARWKUENA, ISP_TCK); writeTdoRegister(GPIO_CLEARWKUENA, ISP_TDO); writeTdiRegister(GPIO_CLEARWKUENA, ISP_TDI); #endif // set initial data writeTckRegister(GPIO_CLEARDATAOUT, ISP_TCK); writeTmsRegister(GPIO_CLEARDATAOUT, ISP_TMS); writeTdiRegister(GPIO_CLEARDATAOUT, ISP_TDI); //set ISP_TCK, ISP_TMS, ISP_TDI pins as outputs and ISP_TDO as input printf("Initial OE: 0x%x (TCK), 0x%x (TMS), 0x%x (TDI), 0x%x (TDO)\n", readTckRegister(GPIO_OE), readTmsRegister(GPIO_OE), readTdiRegister(GPIO_OE), readTdoRegister(GPIO_OE)); unsigned int enableout = readTckRegister(GPIO_OE); writeTckRegister(GPIO_OE, enableout & ~(ISP_TCK)); enableout = readTmsRegister(GPIO_OE); writeTmsRegister(GPIO_OE, enableout & ~(ISP_TMS)); enableout = readTdiRegister(GPIO_OE); writeTdiRegister(GPIO_OE, enableout & ~(ISP_TDI)); enableout = readTdoRegister(GPIO_OE); writeTdoRegister(GPIO_OE, ISP_TDO | enableout); printf("New OE: 0x%x (TCK), 0x%x (TMS), 0x%x (TDI), 0x%x (TDO)\n", readTckRegister(GPIO_OE), readTmsRegister(GPIO_OE), readTdiRegister(GPIO_OE), readTdoRegister(GPIO_OE)); #endif printf("FPGA programming interface has been successfully initialized\n"); return 0; }