static int mc13892_regulator_init(struct mc13892 *mc13892)
{
unsigned int value, register_mask;
printk("Initializing regulators for Sharp Netwalker.\n");
if (mxc_cpu_is_rev(CHIP_REV_2_0) < 0)
sw2_init.constraints.state_mem.uV = 1100000;
else if (mxc_cpu_is_rev(CHIP_REV_2_0) >= 1) {
sw2_init.constraints.state_mem.uV = 1250000;
sw1_init.constraints.state_mem.uV = 1000000;
}
/* Enable coin cell charger */
value = BITFVAL(CIONCHEN, 1) | BITFVAL(VCOIN, VCOIN_3_0V);
register_mask = BITFMASK(CIONCHEN) | BITFMASK(VCOIN);
pmic_write_reg(REG_POWER_CTL0, value, register_mask);
#if defined(CONFIG_RTC_DRV_MXC_V2) || defined(CONFIG_RTC_DRV_MXC_V2_MODULE)
value = BITFVAL(DRM, 1);
register_mask = BITFMASK(DRM);
pmic_write_reg(REG_POWER_CTL0, value, register_mask);
#endif
// mc13892_register_regulator(mc13892, MC13892_SW1, &sw1_init);
// mc13892_register_regulator(mc13892, MC13892_SW2, &sw2_init);
// mc13892_register_regulator(mc13892, MC13892_SW3, &sw3_init);
// mc13892_register_regulator(mc13892, MC13892_SW4, &sw4_init);
// mc13892_register_regulator(mc13892, MC13892_SWBST, &swbst_init);
// mc13892_register_regulator(mc13892, MC13892_VIOHI, &viohi_init);
// mc13892_register_regulator(mc13892, MC13892_VPLL, &vpll_init);
// mc13892_register_regulator(mc13892, MC13892_VDIG, &vdig_init);
// mc13892_register_regulator(mc13892, MC13892_VSD, &vsd_init);
// mc13892_register_regulator(mc13892, MC13892_VUSB2, &vusb2_init);
// mc13892_register_regulator(mc13892, MC13892_VVIDEO, &vvideo_init);
mc13892_register_regulator(mc13892, MC13892_VAUDIO, &vaudio_init);
// mc13892_register_regulator(mc13892, MC13892_VCAM, &vcam_init);
// mc13892_register_regulator(mc13892, MC13892_VGEN1, &vgen1_init);
// mc13892_register_regulator(mc13892, MC13892_VGEN2, &vgen2_init);
// mc13892_register_regulator(mc13892, MC13892_VGEN3, &vgen3_init);
mc13892_register_regulator(mc13892, MC13892_VUSB, &vusb_init);
mc13892_register_regulator(mc13892, MC13892_GPO1, &gpo1_init);
mc13892_register_regulator(mc13892, MC13892_GPO2, &gpo2_init);
mc13892_register_regulator(mc13892, MC13892_GPO3, &gpo3_init);
mc13892_register_regulator(mc13892, MC13892_GPO4, &gpo4_init);
regulator_has_full_constraints();
return 0;
}
static int mc13892_regulator_init(struct mc13892 *mc13892)
{
unsigned int value, register_mask;
printk("Initializing regulators for mx50 arm2.\n");
/* enable standby controll for all regulators */
pmic_read_reg(REG_MODE_0, &value, 0xffffff);
value |= REG_MODE_0_ALL_MASK;
pmic_write_reg(REG_MODE_0, value, 0xffffff);
pmic_read_reg(REG_MODE_1, &value, 0xffffff);
value |= REG_MODE_1_ALL_MASK;
pmic_write_reg(REG_MODE_1, value, 0xffffff);
/* enable switch audo mode */
pmic_read_reg(REG_IDENTIFICATION, &value, 0xffffff);
/* only for mc13892 2.0A */
if ((value & 0x0000FFFF) == 0x45d0) {
pmic_read_reg(REG_SW_4, &value, 0xffffff);
register_mask = (SWMODE_MASK << SW1MODE_LSB) |
(SWMODE_MASK << SW2MODE_LSB);
value &= ~register_mask;
value |= (SWMODE_AUTO << SW1MODE_LSB) |
(SWMODE_AUTO << SW2MODE_LSB);
pmic_write_reg(REG_SW_4, value, 0xffffff);
pmic_read_reg(REG_SW_5, &value, 0xffffff);
register_mask = (SWMODE_MASK << SW3MODE_LSB) |
(SWMODE_MASK << SW4MODE_LSB);
value &= ~register_mask;
value |= (SWMODE_AUTO << SW3MODE_LSB) |
(SWMODE_AUTO << SW4MODE_LSB);
pmic_write_reg(REG_SW_5, value, 0xffffff);
}
/* Enable coin cell charger */
value = BITFVAL(COINCHEN, 1) | BITFVAL(VCOIN, VCOIN_3_0V);
register_mask = BITFMASK(COINCHEN) | BITFMASK(VCOIN);
pmic_write_reg(REG_POWER_CTL0, value, register_mask);
#if defined(CONFIG_RTC_DRV_MXC_V2) || defined(CONFIG_RTC_DRV_MXC_V2_MODULE)
value = BITFVAL(DRM, 1);
register_mask = BITFMASK(DRM);
pmic_write_reg(REG_POWER_CTL0, value, register_mask);
#endif
mc13892_register_regulator(mc13892, MC13892_SW1, &sw1_init);
mc13892_register_regulator(mc13892, MC13892_SW2, &sw2_init);
mc13892_register_regulator(mc13892, MC13892_SW3, &sw3_init);
mc13892_register_regulator(mc13892, MC13892_SW4, &sw4_init);
mc13892_register_regulator(mc13892, MC13892_SWBST, &swbst_init);
mc13892_register_regulator(mc13892, MC13892_VIOHI, &viohi_init);
mc13892_register_regulator(mc13892, MC13892_VPLL, &vpll_init);
mc13892_register_regulator(mc13892, MC13892_VDIG, &vdig_init);
mc13892_register_regulator(mc13892, MC13892_VSD, &vsd_init);
mc13892_register_regulator(mc13892, MC13892_VUSB2, &vusb2_init);
mc13892_register_regulator(mc13892, MC13892_VVIDEO, &vvideo_init);
mc13892_register_regulator(mc13892, MC13892_VAUDIO, &vaudio_init);
mc13892_register_regulator(mc13892, MC13892_VCAM, &vcam_init);
mc13892_register_regulator(mc13892, MC13892_VGEN1, &vgen1_init);
mc13892_register_regulator(mc13892, MC13892_VGEN2, &vgen2_init);
mc13892_register_regulator(mc13892, MC13892_VGEN3, &vgen3_init);
mc13892_register_regulator(mc13892, MC13892_VUSB, &vusb_init);
mc13892_register_regulator(mc13892, MC13892_GPO1, &gpo1_init);
mc13892_register_regulator(mc13892, MC13892_GPO2, &gpo2_init);
mc13892_register_regulator(mc13892, MC13892_GPO3, &gpo3_init);
mc13892_register_regulator(mc13892, MC13892_GPO4, &gpo4_init);
regulator_has_full_constraints();
return 0;
}
static int mc13892_regulator_init(struct mc13892 *mc13892)
{
unsigned int value, register_mask;
printk(KERN_DEBUG "Initializing regulators for mx50 yoshi.\n");
/* enable standby controll for all regulators */
pmic_read_reg(REG_MODE_0, &value, 0xffffff);
value |= REG_MODE_0_ALL_MASK;
pmic_write_reg(REG_MODE_0, value, 0xffffff);
pmic_read_reg(REG_MODE_1, &value, 0xffffff);
value |= REG_MODE_1_ALL_MASK;
pmic_write_reg(REG_MODE_1, value, 0xffffff);
/* enable switch audo mode */
pmic_read_reg(REG_IDENTIFICATION, &value, 0xffffff);
/* only for mc13892 2.0A */
if ((value & 0x0000FFFF) == 0x45d0) {
pmic_read_reg(REG_SW_4, &value, 0xffffff);
register_mask = (SWMODE_MASK << SW1MODE_LSB) |
(SWMODE_MASK << SW2MODE_LSB);
value &= ~register_mask;
value |= (SWMODE_AUTO << SW1MODE_LSB) |
(SWMODE_AUTO << SW2MODE_LSB);
pmic_write_reg(REG_SW_4, value, 0xffffff);
pmic_read_reg(REG_SW_5, &value, 0xffffff);
register_mask = (SWMODE_MASK << SW3MODE_LSB) |
(SWMODE_MASK << SW4MODE_LSB);
value &= ~register_mask;
value |= (SWMODE_AUTO << SW3MODE_LSB) |
(SWMODE_AUTO << SW4MODE_LSB);
pmic_write_reg(REG_SW_5, value, 0xffffff);
}
/* Enable coin cell charger */
value = BITFVAL(COINCHEN, 1) | BITFVAL(VCOIN, VCOIN_3_0V);
register_mask = BITFMASK(COINCHEN) | BITFMASK(VCOIN);
pmic_write_reg(REG_POWER_CTL0, value, register_mask);
#if defined(CONFIG_RTC_DRV_MXC_V2) || defined(CONFIG_RTC_DRV_MXC_V2_MODULE)
value = BITFVAL(DRM, 1);
register_mask = BITFMASK(DRM);
pmic_write_reg(REG_POWER_CTL0, value, register_mask);
#endif
mc13892_register_regulator(mc13892, MC13892_SW1, &sw1_init_evt2);
mc13892_register_regulator(mc13892, MC13892_SW2, &sw2_init_evt2);
mc13892_register_regulator(mc13892, MC13892_SW3, &sw3_init_evt2);
mc13892_register_regulator(mc13892, MC13892_SW4, &sw4_init);
mc13892_register_regulator(mc13892, MC13892_SWBST, &swbst_init);
mc13892_register_regulator(mc13892, MC13892_VIOHI, &viohi_init);
mc13892_register_regulator(mc13892, MC13892_VPLL, &vpll_init);
mc13892_register_regulator(mc13892, MC13892_VDIG, &vdig_init);
mc13892_register_regulator(mc13892, MC13892_VSD, &vsd_init);
mc13892_register_regulator(mc13892, MC13892_VUSB2, &vusb2_init);
mc13892_register_regulator(mc13892, MC13892_VVIDEO, &vvideo_init);
mc13892_register_regulator(mc13892, MC13892_VAUDIO, &vaudio_init);
mc13892_register_regulator(mc13892, MC13892_VCAM, &vcam_init);
mc13892_register_regulator(mc13892, MC13892_VGEN1, &vgen1_init);
mc13892_register_regulator(mc13892, MC13892_VGEN2, &vgen2_init);
mc13892_register_regulator(mc13892, MC13892_VGEN3, &vgen3_init);
mc13892_register_regulator(mc13892, MC13892_VUSB, &vusb_init);
mc13892_register_regulator(mc13892, MC13892_GPO1, &gpo1_init);
mc13892_register_regulator(mc13892, MC13892_GPO2, &gpo2_init);
mc13892_register_regulator(mc13892, MC13892_GPO3, &gpo3_init);
mc13892_register_regulator(mc13892, MC13892_GPO4, &gpo4_init);
/* Turn on VPLLSTBY */
pmic_write_reg(REG_MODE_0, VPLLSTBY_MASK, VPLLSTBY_MASK);
/* STANDBYINV set to 1 */
pmic_write_reg(REG_POWER_CTL2, STANDBYINV_VALUE, STANDBYINV_MASK);
regulator_has_full_constraints();
/* SW4 - AUTO mode */
pmic_write_reg(REG_SW_5, (SW_AUTO_MODE_VAL << 8), (SW_AUTO_MODE_MASK << 8));
/* SW2 - AUTO mode */
pmic_write_reg(REG_SW_4, (SW_AUTO_MODE_VAL << 10), (SW_AUTO_MODE_MASK << 10));
/* SW3 - Auto mode */
pmic_write_reg(REG_SW_5, (SW_AUTO_MODE_VAL << 0), (SW_AUTO_MODE_MASK << 0));
/* SW1 - Auto mode */
pmic_write_reg(REG_SW_4, (SW_AUTO_MODE_VAL << 0), (SW_AUTO_MODE_MASK << 0));
/* VGEN3 */
pmic_write_reg(REG_SETTING_0, (0 << VGEN3SETTING_SHIFT), (1 << VGEN3SETTING_SHIFT));
pmic_write_reg(REG_MODE_1, (1 << VGEN3CONFIG_SHIFT), (1 << VGEN3CONFIG_SHIFT));
/* configure the PMIC for WDIRESET */
pmic_write_reg(REG_POWER_CTL2, (1 << WDIRESET_LSH), (1 << WDIRESET_LSH));
/* Turn on RESTARTEN */
pmic_write_reg(REG_POWER_CTL2, (1 << RESTARTEN_LSH), (1 << RESTARTEN_LSH));
/* VGEN2 controlled by standby */
pmic_write_reg(REG_MODE_0, VGEN2STBY_MASK, VGEN2STBY_MASK);
/* set the debounce time on power buttons to 31.25ms */
/* Configure debounce time for power button 1 */
pmic_write_reg(REG_POWER_CTL2, (PMIC_BUTTON_DEBOUNCE_VALUE << 4),
(PMIC_BUTTON_DEBOUNCE_MASK << 4));
/* Configure debounce time for power button 2 */
pmic_write_reg(REG_POWER_CTL2, (PMIC_BUTTON_DEBOUNCE_VALUE << 6),
(PMIC_BUTTON_DEBOUNCE_MASK << 6));
/* Configure debounce time for power button 3 */
pmic_write_reg(REG_POWER_CTL2, (PMIC_BUTTON_DEBOUNCE_VALUE << 8),
(PMIC_BUTTON_DEBOUNCE_MASK << 8));
pmic_write_reg(REG_MODE_0, VUSB2STBY_MASK, VUSB2STBY_MASK);
return 0;
}
static int mc13892_regulator_init(struct mc13892 *mc13892)
{
unsigned int value;
pmic_event_callback_t power_key_event;
int register_mask;
printk("Initializing regulators for 3-stack.\n");
if (mxc_cpu_is_rev(CHIP_REV_2_0) < 0)
sw2_init.constraints.state_mem.uV = 1100000;
else if (mxc_cpu_is_rev(CHIP_REV_2_0) == 1) {
sw2_init.constraints.state_mem.uV = 1250000;
sw1_init.constraints.state_mem.uV = 1000000;
}
/* subscribe PWRON1 event to enable ON_OFF key */
power_key_event.param = NULL;
power_key_event.func = (void *)power_on_evt_handler;
pmic_event_subscribe(EVENT_PWRONI, power_key_event);
/* Bit 4 DRM: keep VSRTC and CLK32KMCU on for all states */
#if defined(CONFIG_RTC_DRV_MXC_V2) || defined(CONFIG_RTC_DRV_MXC_V2_MODULE)
value = BITFVAL(DRM, 1);
register_mask = BITFMASK(DRM);
pmic_write_reg(REG_POWER_CTL0, value, register_mask);
#endif
/* Set the STANDBYSECINV bit, so that STANDBY pin is
* interpreted as active low.
*/
value = BITFVAL(STANDBYSECINV, 1);
register_mask = BITFMASK(STANDBYSECINV);
pmic_write_reg(REG_POWER_CTL2, value, register_mask);
/* Enable coin cell charger */
value = BITFVAL(COINCHEN, 1) | BITFVAL(VCOIN, VCOIN_3_0V);
register_mask = BITFMASK(COINCHEN) | BITFMASK(VCOIN);
pmic_write_reg(REG_POWER_CTL0, value, register_mask);
mc13892_register_regulator(mc13892, MC13892_SW1, &sw1_init);
mc13892_register_regulator(mc13892, MC13892_SW2, &sw2_init);
mc13892_register_regulator(mc13892, MC13892_SW3, &sw3_init);
mc13892_register_regulator(mc13892, MC13892_SW4, &sw4_init);
mc13892_register_regulator(mc13892, MC13892_SWBST, &swbst_init);
mc13892_register_regulator(mc13892, MC13892_VIOHI, &viohi_init);
mc13892_register_regulator(mc13892, MC13892_VPLL, &vpll_init);
mc13892_register_regulator(mc13892, MC13892_VDIG, &vdig_init);
mc13892_register_regulator(mc13892, MC13892_VSD, &vsd_init);
mc13892_register_regulator(mc13892, MC13892_VUSB2, &vusb2_init);
mc13892_register_regulator(mc13892, MC13892_VVIDEO, &vvideo_init);
mc13892_register_regulator(mc13892, MC13892_VAUDIO, &vaudio_init);
mc13892_register_regulator(mc13892, MC13892_VCAM, &vcam_init);
mc13892_register_regulator(mc13892, MC13892_VGEN1, &vgen1_init);
mc13892_register_regulator(mc13892, MC13892_VGEN2, &vgen2_init);
mc13892_register_regulator(mc13892, MC13892_VGEN3, &vgen3_init);
mc13892_register_regulator(mc13892, MC13892_VUSB, &vusb_init);
mc13892_register_regulator(mc13892, MC13892_GPO1, &gpo1_init);
mc13892_register_regulator(mc13892, MC13892_GPO2, &gpo2_init);
mc13892_register_regulator(mc13892, MC13892_GPO3, &gpo3_init);
mc13892_register_regulator(mc13892, MC13892_GPO4, &gpo4_init);
return 0;
}
