int mdp4_dtv_off(struct platform_device *pdev)
{
	struct msm_fb_data_type *mfd;
	int ret = 0;
	int cndx = 0;
	int undx;
	struct vsycn_ctrl *vctrl;
	struct mdp4_overlay_pipe *pipe;
	struct vsync_update *vp;
	int mixer = 0;

	mfd = (struct msm_fb_data_type *)platform_get_drvdata(pdev);

	mutex_lock(&mfd->dma->ov_mutex);

	vctrl = &vsync_ctrl_db[cndx];

	mdp4_dtv_wait4vsync(cndx);
	mdp4_unmap_sec_resource(mfd);

	wake_up_interruptible_all(&vctrl->wait_queue);

	pipe = vctrl->base_pipe;
	if (pipe != NULL) {
		mixer = pipe->mixer_num;
		/* sanity check, free pipes besides base layer */
		mdp4_overlay_unset_mixer(mixer);
		if (hdmi_prim_display && mfd->ref_cnt == 0) {
			/* adb stop */
			if (pipe->pipe_type == OVERLAY_TYPE_BF)
				mdp4_overlay_borderfill_stage_down(pipe);

			/* pipe == rgb2 */
			vctrl->base_pipe = NULL;
		} else {
			mdp4_mixer_stage_down(pipe, 1);
			mdp4_overlay_pipe_free(pipe, 1);
			vctrl->base_pipe = NULL;
		}
	}

	mdp4_dtv_tg_off(vctrl);

	atomic_set(&vctrl->suspend, 1);

	mdp4_overlay_panel_mode_unset(MDP4_MIXER1, MDP4_PANEL_DTV);

	undx =  vctrl->update_ndx;
	vp = &vctrl->vlist[undx];
	if (vp->update_cnt) {
		/*
		 * pipe's iommu will be freed at next overlay play
		 * and iommu_drop statistic will be increased by one
		 */
		pr_warn("%s: update_cnt=%d\n", __func__, vp->update_cnt);
		mdp4_dtv_pipe_clean(vp);
	}

	ret = panel_next_off(pdev);
	mdp_footswitch_ctrl(FALSE);

	/*
	 * clean up ion freelist
	 * there need two stage to empty ion free list
	 * therefore need call unmap freelist twice
	 */
	mdp4_overlay_iommu_unmap_freelist(mixer);
	mdp4_overlay_iommu_unmap_freelist(mixer);

	/* Mdp clock disable */
	mdp_clk_ctrl(0);

	mutex_unlock(&mfd->dma->ov_mutex);

	pr_info("%s:\n", __func__);
	return ret;
}
Exemple #2
0
int mdp4_dtv_off(struct platform_device *pdev)
{
    struct msm_fb_data_type *mfd;
    int ret = 0;
    int cndx = 0;
    int undx;
    struct vsycn_ctrl *vctrl;
    struct mdp4_overlay_pipe *pipe;
    struct vsync_update *vp;
#if defined(CONFIG_VIDEO_MHL_V1) || defined(CONFIG_VIDEO_MHL_V2) || \
		defined(CONFIG_VIDEO_MHL_TAB_V2)
    if (hdmi_msm_state->hpd_on_offline) {
        pr_info("hpd_offline is not\n");
        return -ENODEV;
    }
#endif

    mfd = (struct msm_fb_data_type *)platform_get_drvdata(pdev);

    mutex_lock(&mfd->dma->ov_mutex);

    vctrl = &vsync_ctrl_db[cndx];

    mdp4_dtv_wait4vsync(cndx);

    atomic_set(&vctrl->vsync_resume, 0);

    complete_all(&vctrl->vsync_comp);
    vctrl->wait_vsync_cnt = 0;

    pipe = vctrl->base_pipe;
    if (pipe != NULL) {
        /* sanity check, free pipes besides base layer */
        mdp4_overlay_unset_mixer(pipe->mixer_num);
        if (hdmi_prim_display && mfd->ref_cnt == 0) {
            /* adb stop */
            if (pipe->pipe_type == OVERLAY_TYPE_BF)
                mdp4_overlay_borderfill_stage_down(pipe);

            /* base pipe may change after borderfill_stage_down */
            pipe = vctrl->base_pipe;
            mdp4_mixer_stage_down(pipe, 1);
            mdp4_overlay_pipe_free(pipe, 1);
            /* pipe == rgb2 */
            vctrl->base_pipe = NULL;
        } else {
            mdp4_mixer_stage_down(pipe, 1);
            mdp4_overlay_pipe_free(pipe, 1);
            vctrl->base_pipe = NULL;
        }
    }
    mdp4_dtv_tg_off(vctrl);
    atomic_set(&vctrl->suspend, 1);

    mdp4_overlay_panel_mode_unset(MDP4_MIXER1, MDP4_PANEL_DTV);
    if (vctrl->vsync_irq_enabled) {
        vctrl->vsync_irq_enabled = 0;
        vsync_irq_disable(INTR_PRIMARY_VSYNC, MDP_PRIM_VSYNC_TERM);
    }

    undx =  vctrl->update_ndx;
    vp = &vctrl->vlist[undx];
    if (vp->update_cnt) {
        /*
         * pipe's iommu will be freed at next overlay play
         * and iommu_drop statistic will be increased by one
         */
        pr_warn("%s: update_cnt=%d\n", __func__, vp->update_cnt);
        mdp4_dtv_pipe_clean(vp);
    }

    ret = panel_next_off(pdev);
    mdp_footswitch_ctrl(FALSE);

    /* Mdp clock disable */
    mdp_clk_ctrl(0);

    mutex_unlock(&mfd->dma->ov_mutex);

    pr_info("%s:\n", __func__);
    return ret;
}
Exemple #3
0
int mdp4_dtv_off(struct platform_device *pdev)
{
    struct msm_fb_data_type *mfd;
    int ret = 0;
    int cndx = 0;
    int undx;
    struct vsycn_ctrl *vctrl;
    struct mdp4_overlay_pipe *pipe;
    struct vsync_update *vp;

    mfd = (struct msm_fb_data_type *)platform_get_drvdata(pdev);

    vctrl = &vsync_ctrl_db[cndx];

    mdp4_dtv_wait4vsync(cndx);

    atomic_set(&vctrl->vsync_resume, 0);

    complete_all(&vctrl->vsync_comp);

    pipe = vctrl->base_pipe;
    if (pipe != NULL) {
        /* sanity check, free pipes besides base layer */
        mdp4_overlay_unset_mixer(pipe->mixer_num);
        if (hdmi_prim_display && mfd->ref_cnt == 0) {
            /* adb stop */
            if (pipe->pipe_type == OVERLAY_TYPE_BF)
                mdp4_overlay_borderfill_stage_down(pipe);

            /* base pipe may change after borderfill_stage_down */
            pipe = vctrl->base_pipe;
            mdp4_mixer_stage_down(pipe, 1);
            mdp4_overlay_pipe_free(pipe);
            /* pipe == rgb2 */
            vctrl->base_pipe = NULL;
        } else {
            mdp4_mixer_stage_down(pipe, 1);
            mdp4_overlay_pipe_free(pipe);
            vctrl->base_pipe = NULL;
        }
    }

    mdp4_dtv_tg_off(vctrl);

    atomic_set(&vctrl->suspend, 1);

    mdp4_overlay_panel_mode_unset(MDP4_MIXER1, MDP4_PANEL_DTV);

    undx =  vctrl->update_ndx;
    vp = &vctrl->vlist[undx];
    if (vp->update_cnt) {
        /*
         * pipe's iommu will be freed at next overlay play
         * and iommu_drop statistic will be increased by one
         */
        pr_warn("%s: update_cnt=%d\n", __func__, vp->update_cnt);
        mdp4_dtv_pipe_clean(vp);
    }

    ret = panel_next_off(pdev);
    mdp_footswitch_ctrl(FALSE);

    /* Mdp clock disable */
    mdp_clk_ctrl(0);

    pr_info("%s:\n", __func__);
    return ret;
}
Exemple #4
0
int mdp4_dtv_off(struct platform_device *pdev)
{
	struct msm_fb_data_type *mfd;
	int ret = 0;
	int cndx = 0;
	int undx;
	struct vsycn_ctrl *vctrl;
	struct mdp4_overlay_pipe *pipe;
	struct vsync_update *vp;
	int mixer = 0;

	mfd = (struct msm_fb_data_type *)platform_get_drvdata(pdev);

	mutex_lock(&mfd->dma->ov_mutex);

	vctrl = &vsync_ctrl_db[cndx];

	mdp4_dtv_wait4vsync(cndx);

	atomic_set(&vctrl->vsync_resume, 0);

	complete_all(&vctrl->vsync_comp);
	vctrl->wait_vsync_cnt = 0;

	pipe = vctrl->base_pipe;
	if (pipe != NULL) {
		mixer = pipe->mixer_num;
		
		mdp4_overlay_unset_mixer(mixer);
		if (hdmi_prim_display && mfd->ref_cnt == 0) {
			
			if (pipe->pipe_type == OVERLAY_TYPE_BF)
				mdp4_overlay_borderfill_stage_down(pipe);

			
			vctrl->base_pipe = NULL;
		} else {
			mdp4_mixer_stage_down(pipe, 1);
			mdp4_overlay_pipe_free(pipe, 1);
			vctrl->base_pipe = NULL;
		}
	}

	mdp4_dtv_tg_off(vctrl);

	atomic_set(&vctrl->suspend, 1);

	mdp4_overlay_panel_mode_unset(MDP4_MIXER1, MDP4_PANEL_DTV);

	undx =  vctrl->update_ndx;
	vp = &vctrl->vlist[undx];
	if (vp->update_cnt) {
		pr_warn("%s: update_cnt=%d\n", __func__, vp->update_cnt);
		mdp4_dtv_pipe_clean(vp);
	}

	ret = panel_next_off(pdev);
#if 0
	mdp_footswitch_ctrl(FALSE);
#endif

	mdp4_overlay_iommu_unmap_freelist(mixer);
	mdp4_overlay_iommu_unmap_freelist(mixer);

	
	mdp_clk_ctrl(0);

	mutex_unlock(&mfd->dma->ov_mutex);

	pr_info("%s:\n", __func__);
	return ret;
}