int mdp4_dsi_video_off(struct platform_device *pdev)
{
int ret = 0;
#if defined (CONFIG_MACH_MSM8960_MAGNUS)
ret = panel_next_off(pdev);
/* p13447 LS2 LCD shinbrad added for sleep current 120515 */
if(ret == 0)
{
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0);
mdp_pipe_ctrl(MDP_OVERLAY0_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
}
/* MDP cmd block enable */
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0);
dsi_video_enabled = 0;
/* MDP cmd block disable */
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
mdp_pipe_ctrl(MDP_OVERLAY0_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
mdp_histogram_ctrl_all(FALSE);
#else
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0);
dsi_video_enabled = 0;
/* MDP cmd block disable */
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
mdp_pipe_ctrl(MDP_OVERLAY0_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
mdp_histogram_ctrl_all(FALSE);
ret = panel_next_off(pdev);
/* p13447 LS2 LCD shinbrad added for sleep current 120515 */
if(ret == 0)
{
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0);
mdp_pipe_ctrl(MDP_OVERLAY0_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
}
#endif
/* dis-engage rgb0 from mixer0 */
if (dsi_pipe) {
mdp4_mixer_stage_down(dsi_pipe);
mdp4_iommu_unmap(dsi_pipe);
}
return ret;
}
int mdp4_atv_off(struct platform_device *pdev)
{
int ret = 0;
mdp_pipe_ctrl(MDP_OVERLAY1_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
ret = panel_next_off(pdev);
/* */
msleep(100);
/* */
if (atv_pipe) {
mdp4_mixer_stage_down(atv_pipe, 1);
mdp4_iommu_unmap(atv_pipe);
}
return ret;
}
int mdp4_atv_off(struct platform_device *pdev)
{
int ret = 0;
mdp_pipe_ctrl(MDP_OVERLAY1_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
ret = panel_next_off(pdev);
/* delay to make sure the last frame finishes */
msleep(100);
/* dis-engage rgb2 from mixer1 */
if (atv_pipe) {
mdp4_mixer_stage_down(atv_pipe, 1);
mdp4_iommu_unmap(atv_pipe);
}
return ret;
}
void mdp4_dsi_video_overlay(struct msm_fb_data_type *mfd)
{
struct fb_info *fbi = mfd->fbi;
uint8 *buf;
unsigned int buf_offset;
int bpp;
struct mdp4_overlay_pipe *pipe;
if (!mfd->panel_power_on)
return;
/* no need to power on cmd block since it's dsi video mode */
bpp = fbi->var.bits_per_pixel / 8;
buf = (uint8 *) fbi->fix.smem_start;
buf_offset = calc_fb_offset(mfd, fbi, bpp);
mutex_lock(&mfd->dma->ov_mutex);
pipe = dsi_pipe;
if (mfd->map_buffer) {
pipe->srcp0_addr = (unsigned int)mfd->map_buffer->iova[0] + \
buf_offset;
pr_debug("start 0x%lx srcp0_addr 0x%x\n", mfd->
map_buffer->iova[0], pipe->srcp0_addr);
} else {
pipe->srcp0_addr = (uint32)(buf + buf_offset);
}
#ifdef CONFIG_LGE_HIDDEN_RESET
if (on_hidden_reset)
pipe->srcp0_addr = (unsigned int)lge_get_hreset_fb_phys_addr();
#endif
mdp4_overlay_rgb_setup(pipe);
mdp4_mixer_stage_up(pipe);
mdp4_overlay_reg_flush(pipe, 0);
mdp4_overlay_dsi_video_start();
mdp4_overlay_dsi_video_vsync_push(mfd, pipe);
mdp4_iommu_unmap(pipe);
mutex_unlock(&mfd->dma->ov_mutex);
}
int mdp4_dsi_video_off(struct platform_device *pdev)
{
int ret = 0;
/* MDP cmd block enable */
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0);
/* MDP cmd block disable */
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
mdp_pipe_ctrl(MDP_OVERLAY0_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
mdp_histogram_ctrl_all(FALSE);
ret = panel_next_off(pdev);
/* dis-engage rgb0 from mixer0 */
if (dsi_pipe) {
mdp4_mixer_stage_down(dsi_pipe);
mdp4_iommu_unmap(dsi_pipe);
}
return ret;
}
void mdp4_dsi_cmd_overlay(struct msm_fb_data_type *mfd)
{
if (!mfd)
return;
mutex_lock(&mfd->dma->ov_mutex);
if (mfd->panel_power_on) {
mdp4_dsi_cmd_dma_busy_wait(mfd);
mdp4_overlay_update_dsi_cmd(mfd);
mdp4_dsi_cmd_kickoff_ui(mfd, dsi_pipe);
mdp4_iommu_unmap(dsi_pipe);
/* signal if pan function is waiting for the update completion */
if (mfd->pan_waiting) {
mfd->pan_waiting = FALSE;
complete(&mfd->pan_comp);
}
}
mutex_unlock(&mfd->dma->ov_mutex);
}
int mdp4_dtv_off(struct platform_device *pdev)
{
struct msm_fb_data_type *mfd;
int ret = 0;
mfd = (struct msm_fb_data_type *)platform_get_drvdata(pdev);
if (dtv_pipe != NULL) {
mdp4_dtv_stop(mfd);
mdp4_mixer_stage_down(dtv_pipe);
mdp4_overlay_pipe_free(dtv_pipe);
mdp4_iommu_unmap(dtv_pipe);
dtv_pipe = NULL;
msleep(20);
}
mdp4_overlay_panel_mode_unset(MDP4_MIXER1, MDP4_PANEL_DTV);
ret = panel_next_off(pdev);
mdp_footswitch_ctrl(FALSE);
dev_info(&pdev->dev, "mdp4_overlay_dtv: off");
return ret;
}
int mdp_lcdc_off(struct platform_device *pdev)
{
int ret = 0;
struct msm_fb_data_type *mfd;
mfd = (struct msm_fb_data_type *)platform_get_drvdata(pdev);
mutex_lock(&mfd->dma->ov_mutex);
ret = panel_next_off(pdev);
/* MDP cmd block enable */
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
MDP_OUTP(MDP_BASE + LCDC_BASE, 0);
lcdc_enabled = 0;
/* MDP cmd block disable */
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
mdp_pipe_ctrl(MDP_OVERLAY0_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
mdp_histogram_ctrl_all(FALSE);
/*ret = panel_next_off(pdev);*/
mutex_unlock(&mfd->dma->ov_mutex);
/* delay to make sure the last frame finishes */
msleep(16);
/* dis-engage rgb0 from mixer0 */
if (lcdc_pipe) {
mdp4_mixer_stage_down(lcdc_pipe);
mdp4_iommu_unmap(lcdc_pipe);
}
#ifdef CONFIG_MSM_BUS_SCALING
mdp_bus_scale_update_request(0);
#endif
return ret;
}
void mdp4_dtv_overlay(struct msm_fb_data_type *mfd)
{
struct mdp4_overlay_pipe *pipe;
if (!mfd->panel_power_on)
return;
if (!dtv_pipe) {
pr_debug("%s: no mixer1 base layer pipe allocated!\n",
__func__);
return;
}
mutex_lock(&mfd->dma->ov_mutex);
pipe = dtv_pipe;
if (pipe->pipe_type == OVERLAY_TYPE_RGB) {
pipe->srcp0_addr = (uint32) mfd->ibuf.buf;
mdp4_overlay_rgb_setup(pipe);
}
mdp4_overlay_reg_flush(pipe, 0);
mdp4_mixer_stage_up(pipe);
mdp4_overlay_dtv_start();
mdp4_overlay_dtv_ov_done_push(mfd, pipe);
mdp4_iommu_unmap(pipe);
mutex_unlock(&mfd->dma->ov_mutex);
}
void mdp4_dtv_overlay(struct msm_fb_data_type *mfd)
{
struct mdp4_overlay_pipe *pipe;
if (!mfd->panel_power_on)
return;
#ifdef CONFIG_MACH_LGE
/* QCT Patch : Prevent kernel Crash (mdp4_overlay1_done_dtv()) */
if (!dtv_pipe) {
pr_debug("%s: no mixer1 base layer pipe allocated!\n",
__func__);
return;
}
#endif
mutex_lock(&mfd->dma->ov_mutex);
if (dtv_pipe == NULL) {
if (mdp4_overlay_dtv_set(mfd, NULL)) {
pr_warn("%s: dtv_pipe == NULL\n", __func__);
mutex_unlock(&mfd->dma->ov_mutex);
return;
}
}
pipe = dtv_pipe;
if (pipe->pipe_type == OVERLAY_TYPE_RGB) {
pipe->srcp0_addr = (uint32) mfd->ibuf.buf;
mdp4_overlay_rgb_setup(pipe);
}
mdp4_mixer_stage_up(pipe);
mdp4_overlay_reg_flush(pipe, 0);
mdp4_overlay_dtv_start();
mdp4_overlay_dtv_ov_done_push(mfd, pipe);
mdp4_iommu_unmap(pipe);
mutex_unlock(&mfd->dma->ov_mutex);
}
void mdp4_lcdc_overlay(struct msm_fb_data_type *mfd)
{
struct fb_info *fbi = mfd->fbi;
uint8 *buf;
unsigned int buf_offset;
int bpp;
struct mdp4_overlay_pipe *pipe;
/* LGE_UPDATE_S [email protected] 20110717 hidden_reset_porting from Victor. */
#ifdef CONFIG_LGE_HIDDEN_RESET_PATCH
/* LGE_CHANGE
* add hidden reset module
* 2011-07-07, [email protected]
*/
unsigned int tmp;
#endif
/* LGE_UPDATE_E [email protected] 20110717 hidden_reset_porting from Victor. */
if (!mfd->panel_power_on)
return;
/* no need to power on cmd block since it's lcdc mode */
bpp = fbi->var.bits_per_pixel / 8;
/* LGE_UPDATE_S [email protected] 20110717 hidden_reset_porting from Victor. */
#ifdef CONFIG_LGE_HIDDEN_RESET_PATCH
/* LGE_CHANGE
* add hidden reset module
* 2011-07-07, [email protected]
*/
if (on_hidden_reset) {
tmp = (unsigned int)lge_get_fb_copy_virt_rgb888_addr();
buf = (unsigned char *)__pa((unsigned int)tmp);
} else {
buf = (uint8 *) fbi->fix.smem_start;
/* LGE_UPDATE_S youngrok.song QCT404023I patch */
#if 1
//buf_offset = calc_fb_offset(mfd, fbi, bpp);
#else
buf += fbi->var.xoffset * bpp +
fbi->var.yoffset * fbi->fix.line_length;
#endif
/* LGE_UPDATE_E youngrok.song QCT404023I patch */
}
#else
buf = (uint8 *) fbi->fix.smem_start;
#endif
buf_offset = calc_fb_offset(mfd, fbi, bpp);
/* LGE_UPDATE_E [email protected] 20110717 hidden_reset_porting from Victor. */
mutex_lock(&mfd->dma->ov_mutex);
pipe = lcdc_pipe;
if (mfd->map_buffer) {
pipe->srcp0_addr = (unsigned int)mfd->map_buffer->iova[0] + \
buf_offset;
pr_debug("start 0x%lx srcp0_addr 0x%x\n", mfd->
map_buffer->iova[0], pipe->srcp0_addr);
} else {
pipe->srcp0_addr = (uint32)(buf + buf_offset);
}
mdp4_overlay_rgb_setup(pipe);
mdp4_mixer_stage_up(pipe);
mdp4_overlay_reg_flush(pipe, 0);
mdp4_overlay_lcdc_start();
mdp4_overlay_lcdc_vsync_push(mfd, pipe);
mdp4_iommu_unmap(pipe);
mutex_unlock(&mfd->dma->ov_mutex);
}
