void mdp4_dtv_set_black_screen(void)
{
char *rgb_base;
/*Black color*/
uint32 color = 0x00000000;
uint32 temp_src_format;
int cndx = 0;
struct vsycn_ctrl *vctrl;
mdp4_mixer_late_commit();
vctrl = &vsync_ctrl_db[cndx];
if (vctrl->base_pipe == NULL || !hdmi_prim_display) {
pr_err("dtv_pipe is not configured yet\n");
return;
}
rgb_base = MDP_BASE + MDP4_RGB_BASE;
rgb_base += (MDP4_RGB_OFF * vctrl->base_pipe->pipe_num);
/*
* RGB Constant Color
*/
MDP_OUTP(rgb_base + 0x1008, color);
/*
* MDP_RGB_SRC_FORMAT
*/
temp_src_format = inpdw(rgb_base + 0x0050);
MDP_OUTP(rgb_base + 0x0050, temp_src_format | BIT(22));
mdp4_overlay_reg_flush(vctrl->base_pipe, 1);
mdp4_mixer_stage_up(vctrl->base_pipe, 0);
mdp4_mixer_stage_commit(vctrl->base_pipe->mixer_num);
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
}
void mdp4_lcdc_overlay(struct msm_fb_data_type *mfd)
{
struct fb_info *fbi = mfd->fbi;
uint8 *buf;
unsigned int buf_offset;
int bpp;
int cnt, cndx = 0;
struct vsycn_ctrl *vctrl;
struct mdp4_overlay_pipe *pipe;
vctrl = &vsync_ctrl_db[cndx];
pipe = vctrl->base_pipe;
if (!pipe || !mfd->panel_power_on)
return;
pr_debug("%s: cpu=%d pid=%d\n", __func__,
smp_processor_id(), current->pid);
if (pipe->pipe_type == OVERLAY_TYPE_RGB) {
bpp = fbi->var.bits_per_pixel / 8;
buf = (uint8 *) fbi->fix.smem_start;
buf_offset = calc_fb_offset(mfd, fbi, bpp);
if (mfd->map_buffer->iova[0]) {
pipe->srcp0_addr = mfd->map_buffer->iova[0]
+ buf_offset;
} else
pipe->srcp0_addr = (uint32)(buf + buf_offset);
mdp4_lcdc_pipe_queue(0, pipe);
}
mdp4_overlay_mdp_perf_upd(mfd, 1);
mutex_lock(&mfd->dma->ov_mutex);
cnt = mdp4_lcdc_pipe_commit(cndx, 0);
mutex_unlock(&mfd->dma->ov_mutex);
#if defined (CONFIG_EUR_MODEL_GT_I9210)
if (cnt >= 0)
#else
if (cnt)
#endif
{
if (pipe->ov_blt_addr)
mdp4_lcdc_wait4ov(cndx);
else
mdp4_lcdc_wait4dmap(cndx);
}
mdp4_mixer_late_commit();
mdp4_overlay_mdp_perf_upd(mfd, 0);
}
int mdp4_lcdc_off(struct platform_device *pdev)
{
int ret = 0;
int cndx = 0;
struct msm_fb_data_type *mfd;
struct vsycn_ctrl *vctrl;
struct mdp4_overlay_pipe *pipe;
unsigned long flags;
int need_wait = 0;
pr_err("[QC_DEBUG] %s Entry\n", __func__);
mdp4_mixer_late_commit();
mfd = (struct msm_fb_data_type *)platform_get_drvdata(pdev);
#if defined (CONFIG_EUR_MODEL_GT_I9210)
mutex_lock(&mfd->dma->ov_mutex);
#endif
vctrl = &vsync_ctrl_db[cndx];
pipe = vctrl->base_pipe;
#if defined (CONFIG_EUR_MODEL_GT_I9210)
pr_err("[QC_DEBUG] vctrl->wait_vsync_cnt: %d\n", vctrl->wait_vsync_cnt);
mdp4_lcdc_wait4vsync(cndx);
atomic_set(&vctrl->vsync_resume, 0);
#else
atomic_set(&vctrl->suspend, 1);
atomic_set(&vctrl->vsync_resume, 0);
msleep(20); /* >= 17 ms */
#endif
complete_all(&vctrl->vsync_comp);
if (pipe->ov_blt_addr) {
spin_lock_irqsave(&vctrl->spin_lock, flags);
if (vctrl->ov_koff != vctrl->ov_done)
need_wait = 1;
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
if (need_wait)
mdp4_lcdc_wait4ov(0);
}
#if !defined (CONFIG_EUR_MODEL_GT_I9210)
MDP_OUTP(MDP_BASE + LCDC_BASE, 0);
#endif
lcdc_enabled = 0;
mdp_histogram_ctrl_all(FALSE);
if (pipe) {
/* sanity check, free pipes besides base layer */
mdp4_overlay_unset_mixer(pipe->mixer_num);
if (mfd->ref_cnt == 0) {
/* adb stop */
if (pipe->pipe_type == OVERLAY_TYPE_BF)
mdp4_overlay_borderfill_stage_down(pipe);
vctrl->base_pipe = NULL;
} else {
/* system suspending */
mdp4_mixer_stage_down(vctrl->base_pipe, 1);
mdp4_overlay_iommu_pipe_free(
vctrl->base_pipe->pipe_ndx, 1);
}
}
#if defined (CONFIG_EUR_MODEL_GT_I9210)
mdp4_lcdc_tg_off(vctrl);
atomic_set(&vctrl->suspend, 1);
#endif
/* MDP clock disable */
mdp_clk_ctrl(0);
mdp_pipe_ctrl(MDP_OVERLAY0_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
#if defined (CONFIG_EUR_MODEL_GT_I9210)
mutex_unlock(&mfd->dma->ov_mutex);
pr_err("[QC_DEBUG] %s Exit\n", __func__);
#endif
return ret;
}
int mdp4_dsi_video_off(struct platform_device *pdev)
{
int ret = 0;
int cndx = 0;
struct msm_fb_data_type *mfd;
struct vsycn_ctrl *vctrl;
struct mdp4_overlay_pipe *pipe;
unsigned long flags;
int need_wait = 0;
mdp4_mixer_late_commit();
mfd = (struct msm_fb_data_type *)platform_get_drvdata(pdev);
vctrl = &vsync_ctrl_db[cndx];
pipe = vctrl->base_pipe;
atomic_set(&vctrl->suspend, 1);
atomic_set(&vctrl->vsync_resume, 0);
msleep(20); /* >= 17 ms */
complete_all(&vctrl->vsync_comp);
if (pipe->ov_blt_addr) {
spin_lock_irqsave(&vctrl->spin_lock, flags);
if (vctrl->ov_koff != vctrl->ov_done)
need_wait = 1;
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
if (need_wait)
mdp4_dsi_video_wait4ov(0);
}
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0);
dsi_video_enabled = 0;
mdp_histogram_ctrl_all(FALSE);
if (pipe) {
/* sanity check, free pipes besides base layer */
mdp4_overlay_unset_mixer(pipe->mixer_num);
if (mfd->ref_cnt == 0) {
/* adb stop */
if (pipe->pipe_type == OVERLAY_TYPE_BF)
mdp4_overlay_borderfill_stage_down(pipe);
vctrl->base_pipe = NULL;
} else {
/* system suspending */
mdp4_mixer_stage_down(vctrl->base_pipe, 1);
mdp4_overlay_iommu_pipe_free(
vctrl->base_pipe->pipe_ndx, 1);
}
}
/* mdp clock off */
mdp_clk_ctrl(0);
mdp_pipe_ctrl(MDP_OVERLAY0_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
return ret;
}
