static void mdp4_dsi_video_do_blt(struct msm_fb_data_type *mfd, int enable)
{
unsigned long flag;
int data;
int change = 0;
spin_lock_irqsave(&mdp_spin_lock, flag);
if (enable && dsi_pipe->blt_addr == 0) {
dsi_pipe->blt_addr = dsi_pipe->blt_base;
dsi_pipe->blt_cnt = 0;
dsi_pipe->ov_cnt = 0;
dsi_pipe->dmap_cnt = 0;
change++;
} else if (enable == 0 && dsi_pipe->blt_addr) {
dsi_pipe->blt_addr = 0;
change++;
}
pr_info("[MDP4] %s: enable=%d blt_addr=%x\n", __func__, enable, (int)dsi_pipe->blt_addr);
spin_unlock_irqrestore(&mdp_spin_lock, flag);
if (!change)
return;
/*
* may need mutex here to sync with whom dsiable
* timing generator
*/
data = inpdw(MDP_BASE + DSI_VIDEO_BASE);
if (data) { /* timing generatore enabled */
// apply qualcomm patch for writeback side effect
//mdp4_overlay_dsi_video_wait4event(mfd, INTR_DMA_P_DONE);
if (dsi_pipe->blt_addr) {
mdp4_overlay_dsi_video_wait4event(mfd, INTR_DMA_P_DONE);
}
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0);
// apply qualcomm patch for writeback side effect
//msleep(20); /* make sure last frame is finished */
mdelay(10); /* make sure last frame is finished */
mipi_dsi_controller_cfg(0);
}
mdp4_overlayproc_cfg(dsi_pipe);
mdp4_overlay_dmap_xy(dsi_pipe);
if (data) { /* timing generatore enabled */
// apply qualcomm patch for writeback side effect
//MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 1);
//mdp4_overlay_dsi_video_wait4event(mfd, INTR_DMA_P_DONE);
//mdp4_overlay_dsi_video_wait4event(mfd, INTR_DMA_P_DONE);
//MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0);
if (dsi_pipe->blt_addr) {
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 1);
mdp4_overlay_dsi_video_prefill(mfd);
mdp4_overlay_dsi_video_prefill(mfd);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0);
}
mipi_dsi_sw_reset();
mipi_dsi_controller_cfg(1);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 1);
}
}
/*
* make sure the MIPI_DSI_WRITEBACK_SIZE defined at boardfile
* has enough space h * w * 3 * 2
*/
static void mdp4_dsi_video_do_blt(struct msm_fb_data_type *mfd, int enable)
{
unsigned long flag;
int data;
int change = 0;
mdp4_allocate_writeback_buf(mfd, MDP4_MIXER0);
if (mfd->ov0_wb_buf->phys_addr == 0) {
pr_info("%s: no blt_base assigned\n", __func__);
return;
}
spin_lock_irqsave(&mdp_spin_lock, flag);
if (enable && dsi_pipe->blt_addr == 0) {
dsi_pipe->blt_addr = mfd->ov0_wb_buf->phys_addr;
dsi_pipe->blt_cnt = 0;
dsi_pipe->ov_cnt = 0;
dsi_pipe->dmap_cnt = 0;
mdp4_stat.blt_dsi_video++;
change++;
} else if (enable == 0 && dsi_pipe->blt_addr) {
dsi_pipe->blt_addr = 0;
change++;
}
pr_debug("%s: enable=%d blt_addr=%x\n", __func__,
enable, (int)dsi_pipe->blt_addr);
spin_unlock_irqrestore(&mdp_spin_lock, flag);
if (!change)
return;
/*
* may need mutex here to sync with whom dsiable
* timing generator
*/
data = inpdw(MDP_BASE + DSI_VIDEO_BASE);
data &= 0x01;
if (data) { /* timing generator enabled */
mdp4_overlay_dsi_video_wait4event(mfd, INTR_DMA_P_DONE);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0);
msleep(20); /* make sure last frame is finished */
mipi_dsi_controller_cfg(0);
}
mdp4_overlayproc_cfg(dsi_pipe);
mdp4_overlay_dmap_xy(dsi_pipe);
if (data) { /* timing generator enabled */
if (dsi_pipe->blt_addr) {
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 1);
mdp4_overlay_dsi_video_prefill(mfd);
mdp4_overlay_dsi_video_prefill(mfd);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0);
}
mipi_dsi_sw_reset();
mipi_dsi_controller_cfg(1);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 1);
}
}
/*
* make sure the MIPI_DSI_WRITEBACK_SIZE defined at boardfile
* has enough space h * w * 3 * 2
*/
static void mdp4_dsi_video_do_blt(struct msm_fb_data_type *mfd, int enable)
{
unsigned long flag;
int data;
int change = 0;
mdp4_allocate_writeback_buf(mfd, MDP4_MIXER0);
if (mfd->ov0_wb_buf->phys_addr == 0) {
pr_info("%s: no blt_base assigned\n", __func__);
return;
}
spin_lock_irqsave(&mdp_spin_lock, flag);
if (enable && dsi_pipe->blt_addr == 0) {
dsi_pipe->blt_addr = mfd->ov0_wb_buf->phys_addr;
dsi_pipe->blt_cnt = 0;
dsi_pipe->ov_cnt = 0;
dsi_pipe->dmap_cnt = 0;
mdp4_stat.blt_dsi_video++;
change++;
} else if (enable == 0 && dsi_pipe->blt_addr) {
dsi_pipe->blt_addr = 0;
change++;
}
if (!change) {
spin_unlock_irqrestore(&mdp_spin_lock, flag);
return;
}
pr_debug("%s: enable=%d blt_addr=%x\n", __func__,
enable, (int)dsi_pipe->blt_addr);
blt_cfg_changed = 1;
#if defined (LGE_BLT_LOCKUP_WR)
blt_ent++;
#endif
spin_unlock_irqrestore(&mdp_spin_lock, flag);
/*
* may need mutex here to sync with whom dsiable
* timing generator
*/
data = inpdw(MDP_BASE + DSI_VIDEO_BASE);
data &= 0x01;
if (data) { /* timing generator enabled */
mdp4_overlay_dsi_video_wait4event(mfd, INTR_DMA_P_DONE);
mdp4_overlay_dsi_video_wait4event(mfd, INTR_PRIMARY_VSYNC);
}
#if 0 /* removed by MSM8960AAAAANLYA1049A */
if (data) { /* timing generator enabled */
if (dsi_pipe->blt_addr) {
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 1);
mdp4_overlay_dsi_video_prefill(mfd);
mdp4_overlay_dsi_video_prefill(mfd);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0);
}
mipi_dsi_sw_reset();
mipi_dsi_controller_cfg(1);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 1);
}
#endif
}