void mdp4_dsi_video_overlay(struct msm_fb_data_type *mfd) { struct fb_info *fbi = mfd->fbi; uint8 *buf; int bpp; struct mdp4_overlay_pipe *pipe; #ifndef CONFIG_LGE_I_DISP_OV_MUTEX if (!mfd->panel_power_on) return; #endif /* no need to power on cmd block since it's dsi mode */ bpp = fbi->var.bits_per_pixel / 8; buf = (uint8 *) fbi->fix.smem_start; buf += fbi->var.xoffset * bpp + fbi->var.yoffset * fbi->fix.line_length; mutex_lock(&mfd->dma->ov_mutex); #ifdef CONFIG_LGE_I_DISP_OV_MUTEX if (!mfd->panel_power_on){ mutex_unlock(&mfd->dma->ov_mutex); return; } #endif pipe = dsi_pipe; pipe->srcp0_addr = (uint32) buf; mdp4_overlay_rgb_setup(pipe); mdp4_overlay_reg_flush(pipe, 1); mdp4_overlay_dsi_video_vsync_push(mfd, pipe); mutex_unlock(&mfd->dma->ov_mutex); mdp4_stat.kickoff_dsi++; }
void mdp4_dsi_video_overlay(struct msm_fb_data_type *mfd) { struct fb_info *fbi = mfd->fbi; uint8 *buf; unsigned int buf_offset; int bpp; struct mdp4_overlay_pipe *pipe; if (!mfd->panel_power_on) return; /* no need to power on cmd block since it's dsi video mode */ bpp = fbi->var.bits_per_pixel / 8; buf = (uint8 *) fbi->fix.smem_start; buf_offset = calc_fb_offset(mfd, fbi, bpp); mutex_lock(&mfd->dma->ov_mutex); pipe = dsi_pipe; if (mfd->display_iova) pipe->srcp0_addr = mfd->display_iova + buf_offset; else pipe->srcp0_addr = (uint32)(buf + buf_offset); mdp4_overlay_rgb_setup(pipe); mdp4_overlay_reg_flush(pipe, 0); mdp4_mixer_stage_up(pipe); mdp4_overlay_dsi_video_start(); mdp4_overlay_dsi_video_vsync_push(mfd, pipe); mdp4_iommu_unmap(pipe); mutex_unlock(&mfd->dma->ov_mutex); }
void mdp4_dsi_video_overlay(struct msm_fb_data_type *mfd) { struct fb_info *fbi = mfd->fbi; uint8 *buf; int bpp; struct mdp4_overlay_pipe *pipe; if (!mfd->panel_power_on) return; /* no need to power on cmd block since it's dsi video mode */ bpp = fbi->var.bits_per_pixel / 8; buf = (uint8 *) fbi->fix.smem_start; buf += fbi->var.xoffset * bpp + fbi->var.yoffset * fbi->fix.line_length; mutex_lock(&mfd->dma->ov_mutex); pipe = dsi_pipe; pipe->srcp0_addr = (uint32) buf; mdp4_overlay_rgb_setup(pipe); mdp4_mixer_stage_up(pipe); mdp4_overlay_reg_flush(pipe, 0); mdp4_overlay_dsi_video_vsync_push(mfd, pipe); mutex_unlock(&mfd->dma->ov_mutex); }
void mdp4_dsi_video_overlay(struct msm_fb_data_type *mfd) { struct fb_info *fbi = mfd->fbi; uint8 *buf; unsigned int buf_offset; int bpp; struct mdp4_overlay_pipe *pipe; if (!mfd->panel_power_on) return; /* no need to power on cmd block since it's dsi video mode */ bpp = fbi->var.bits_per_pixel / 8; buf = (uint8 *) fbi->fix.smem_start; buf_offset = calc_fb_offset(mfd, fbi, bpp); mutex_lock(&mfd->dma->ov_mutex); pipe = dsi_pipe; if (mfd->map_buffer) { pipe->srcp0_addr = (unsigned int)mfd->map_buffer->iova[0] + \ buf_offset; pr_debug("start 0x%lx srcp0_addr 0x%x\n", mfd-> map_buffer->iova[0], pipe->srcp0_addr); } else { pipe->srcp0_addr = (uint32)(buf + buf_offset); } #ifdef CONFIG_LGE_HIDDEN_RESET if (on_hidden_reset) pipe->srcp0_addr = (unsigned int)lge_get_hreset_fb_phys_addr(); #endif mdp4_overlay_rgb_setup(pipe); mdp4_mixer_stage_up(pipe); mdp4_overlay_reg_flush(pipe, 0); mdp4_overlay_dsi_video_start(); mdp4_overlay_dsi_video_vsync_push(mfd, pipe); mdp4_iommu_unmap(pipe); mutex_unlock(&mfd->dma->ov_mutex); }
void mdp4_dsi_video_overlay(struct msm_fb_data_type *mfd) { struct fb_info *fbi = mfd->fbi; uint8 *buf; int bpp; int data = 0; int vg_active = 0; struct mdp4_overlay_pipe *pipe; if (!mfd->panel_power_on) return; /* no need to power on cmd block since it's dsi mode */ bpp = fbi->var.bits_per_pixel / 8; buf = (uint8 *) fbi->fix.smem_start; buf += fbi->var.xoffset * bpp + fbi->var.yoffset * fbi->fix.line_length; mutex_lock(&mfd->dma->ov_mutex); pipe = dsi_pipe; pipe->srcp0_addr = (uint32) buf; mdp4_overlay_rgb_setup(pipe); mdp4_overlay_reg_flush(pipe, 1); mdp4_overlay_dsi_video_vsync_push(mfd, pipe); // This will check if there is any VG pipe connected to layermixer 0 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE); data = inpdw(MDP_BASE + 0x10100); rmb(); if (data & 0xff) vg_active = 1; else vg_active = 0; mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE); mutex_unlock(&mfd->dma->ov_mutex); if (vg_active) yield(); mdp4_stat.kickoff_dsi++; }
/* 3D side by side */ void mdp4_dsi_video_3d_sbys(struct msm_fb_data_type *mfd, struct msmfb_overlay_3d *r3d) { struct fb_info *fbi; struct mdp4_overlay_pipe *pipe; int bpp; uint8 *buf = NULL; if (dsi_pipe == NULL) return; dsi_pipe->is_3d = r3d->is_3d; dsi_pipe->src_height_3d = r3d->height; dsi_pipe->src_width_3d = r3d->width; pipe = dsi_pipe; if (pipe->is_3d) mdp4_overlay_panel_3d(pipe->mixer_num, MDP4_3D_SIDE_BY_SIDE); else mdp4_overlay_panel_3d(pipe->mixer_num, MDP4_3D_NONE); fbi = mfd->fbi; bpp = fbi->var.bits_per_pixel / 8; buf = (uint8 *) fbi->fix.smem_start; buf += fbi->var.xoffset * bpp + fbi->var.yoffset * fbi->fix.line_length; if (pipe->is_3d) { pipe->src_height = pipe->src_height_3d; pipe->src_width = pipe->src_width_3d; pipe->src_h = pipe->src_height_3d; pipe->src_w = pipe->src_width_3d; pipe->dst_h = pipe->src_height_3d; pipe->dst_w = pipe->src_width_3d; pipe->srcp0_ystride = msm_fb_line_length(0, pipe->src_width, bpp); } else { /* 2D */ pipe->src_height = fbi->var.yres; pipe->src_width = fbi->var.xres; pipe->src_h = fbi->var.yres; pipe->src_w = fbi->var.xres; pipe->dst_h = fbi->var.yres; pipe->dst_w = fbi->var.xres; pipe->srcp0_ystride = fbi->fix.line_length; } pipe->src_y = 0; pipe->src_x = 0; pipe->dst_y = 0; pipe->dst_x = 0; pipe->srcp0_addr = (uint32)buf; mdp4_overlay_rgb_setup(pipe); mdp4_overlayproc_cfg(pipe); mdp4_overlay_dmap_xy(pipe); mdp4_overlay_dmap_cfg(mfd, 1); mdp4_mixer_stage_up(pipe); mb(); /* wait for vsycn */ mdp4_overlay_dsi_video_vsync_push(mfd, pipe); }