void mdp4_mddi_overlay_kickoff(struct msm_fb_data_type *mfd,
struct mdp4_overlay_pipe *pipe)
{
/* change mdp clk while mdp is idle` */
mdp4_set_perf_level();
if (mdp_hw_revision == MDP4_REVISION_V2_1) {
if (mdp4_overlay_status_read(MDP4_OVERLAY_TYPE_UNSET)) {
uint32 data;
data = inpdw(MDP_BASE + 0x0028);
data &= ~0x0300; /* bit 8, 9, MASTER4 */
if (mfd->fbi->var.xres == 540) /* qHD, 540x960 */
data |= 0x0200;
else
data |= 0x0100;
MDP_OUTP(MDP_BASE + 0x00028, data);
mdp4_overlay_status_write(MDP4_OVERLAY_TYPE_UNSET,
false);
}
if (mdp4_overlay_status_read(MDP4_OVERLAY_TYPE_SET)) {
uint32 data;
data = inpdw(MDP_BASE + 0x0028);
data &= ~0x0300; /* bit 8, 9, MASTER4 */
MDP_OUTP(MDP_BASE + 0x00028, data);
mdp4_overlay_status_write(MDP4_OVERLAY_TYPE_SET, false);
}
}
mdp_enable_irq(MDP_OVERLAY0_TERM);
mfd->dma->busy = TRUE;
/* start OVERLAY pipe */
mdp_pipe_kickoff(MDP_OVERLAY0_TERM, mfd);
}
void mdp4_mddi_overlay_kickoff(struct msm_fb_data_type *mfd,
struct mdp4_overlay_pipe *pipe)
{
/*< DTS2010080403325 lijianzhao 20100804 begin */
/* use dma_p(overlay) pipe ,change bpp into 16 */
#ifdef CONFIG_FB_MSM_BPP_SWITCH
if(16 != mfd->panel_info.bpp)
{
mdp4_switch_bpp_config(mfd,16);
}
#endif
/* DTS2010080403325 lijianzhao 20100804 end >*/
/*< DTS2011072603082 fengwei 20110806 begin*/
/*for resolving freeze screen because of 60 frame freq and CTS TEST*/
if (mdp_hw_revision == MDP4_REVISION_V2_1) {
if (mdp4_overlay_status_read(MDP4_OVERLAY_TYPE_UNSET)) {
uint32 data;
data = inpdw(MDP_BASE + 0x0028);
data &= ~0x0300; /* bit 8, 9, MASTER4 */
if (mfd->fbi->var.xres == 540) /* qHD, 540x960 */
data |= 0x0200;
else
data |= 0x0100;
MDP_OUTP(MDP_BASE + 0x00028, data);
mdp4_overlay_status_write(MDP4_OVERLAY_TYPE_UNSET,
false);
}
if (mdp4_overlay_status_read(MDP4_OVERLAY_TYPE_SET)) {
uint32 data;
data = inpdw(MDP_BASE + 0x0028);
data &= ~0x0300; /* bit 8, 9, MASTER4 */
MDP_OUTP(MDP_BASE + 0x00028, data);
mdp4_overlay_status_write(MDP4_OVERLAY_TYPE_SET, false);
}
}
/*DTS2011072603082 fengwei 20110806 end >*/
mdp_enable_irq(MDP_OVERLAY0_TERM);
mfd->dma->busy = TRUE;
/* start OVERLAY pipe */
mdp_pipe_kickoff(MDP_OVERLAY0_TERM, mfd);
}
void mdp4_mddi_overlay_kickoff(struct msm_fb_data_type *mfd,
struct mdp4_overlay_pipe *pipe)
{
unsigned long flag;
if (mdp_hw_revision == MDP4_REVISION_V2_1) {
if (mdp4_overlay_status_read(MDP4_OVERLAY_TYPE_UNSET)) {
uint32 data;
data = inpdw(MDP_BASE + 0x0028);
data &= ~0x0300; /* bit 8, 9, MASTER4 */
if (mfd->fbi->var.xres == 540) /* qHD, 540x960 */
data |= 0x0200;
else
data |= 0x0100;
MDP_OUTP(MDP_BASE + 0x00028, data);
mdp4_overlay_status_write(MDP4_OVERLAY_TYPE_UNSET,
false);
}
if (mdp4_overlay_status_read(MDP4_OVERLAY_TYPE_SET)) {
uint32 data;
data = inpdw(MDP_BASE + 0x0028);
data &= ~0x0300; /* bit 8, 9, MASTER4 */
MDP_OUTP(MDP_BASE + 0x00028, data);
mdp4_overlay_status_write(MDP4_OVERLAY_TYPE_SET, false);
}
}
mdp_enable_irq(MDP_OVERLAY0_TERM);
spin_lock_irqsave(&mdp_spin_lock, flag);
mfd->dma->busy = TRUE;
if (mddi_pipe->blt_addr)
mfd->dma->dmap_busy = TRUE;
spin_unlock_irqrestore(&mdp_spin_lock, flag);
/* start OVERLAY pipe */
mdp_pipe_kickoff(MDP_OVERLAY0_TERM, mfd);
mdp4_stat.kickoff_ov0++;
}
void mdp4_mddi_overlay_kickoff(struct msm_fb_data_type *mfd,
struct mdp4_overlay_pipe *pipe)
{
#ifdef CONFIG_SHLCDC_BOARD
uint32 data;
int master4_invalid_backupflg = master4_invalid_flg;
#endif /*CONFIG_SHLCDC_BOARD*/
#ifdef CONFIG_SHLCDC_BOARD
if(mfd->dma->busy == TRUE){
mutex_unlock(&mfd->dma->ov_mutex);
down(&mfd->sem);
up(&mfd->sem);
mutex_lock(&mfd->dma->ov_mutex);
return;
}
down(&mfd->sem);
#endif /*CONFIG_SHLCDC_BOARD*/
#ifndef CONFIG_SHLCDC_BOARD
if (mdp_hw_revision == MDP4_REVISION_V2_1) {
if (mdp4_overlay_status_read(MDP4_OVERLAY_TYPE_UNSET)) {
uint32 data;
data = inpdw(MDP_BASE + 0x0028);
data &= ~0x0300; /* bit 8, 9, MASTER4 */
if (mfd->fbi->var.xres == 540) /* qHD, 540x960 */
data |= 0x0200;
else
data |= 0x0100;
MDP_OUTP(MDP_BASE + 0x00028, data);
mdp4_overlay_status_write(MDP4_OVERLAY_TYPE_UNSET,
false);
}
if (mdp4_overlay_status_read(MDP4_OVERLAY_TYPE_SET)) {
uint32 data;
data = inpdw(MDP_BASE + 0x0028);
data &= ~0x0300; /* bit 8, 9, MASTER4 */
MDP_OUTP(MDP_BASE + 0x00028, data);
mdp4_overlay_status_write(MDP4_OVERLAY_TYPE_SET, false);
}
}
#endif /*CONFIG_SHLCDC_BOARD*/
mdp_enable_irq(MDP_OVERLAY0_TERM);
mfd->dma->busy = TRUE;
#ifdef CONFIG_SHLCDC_BOARD
INIT_COMPLETION(pipe->comp);
pending_pipe = pipe;
mutex_unlock(&mfd->dma->ov_mutex);
mdp_wait_vsync(mfd);
mutex_lock(&mfd->dma->ov_mutex);
#endif /*CONFIG_SHLCDC_BOARD*/
#ifdef CONFIG_SHLCDC_BOARD
if( master4_invalid_status != master4_invalid_backupflg ){
if ((mdp_hw_revision == MDP4_REVISION_V2_1) && (master4_invalid_backupflg == 0)) {
data = inpdw(MDP_BASE + 0x0028);
data &= ~0x0300; /* bit 8, 9, MASTER4 */
if (mfd->fbi->var.xres == 540) /* qHD, 540x960 */
data |= 0x0200;
else
data |= 0x0100;
MDP_OUTP(MDP_BASE + 0x00028, data);
}else{
data = inpdw(MDP_BASE + 0x0028);
data &= ~0x0300; /* bit 8, 9, MASTER4 */
MDP_OUTP(MDP_BASE + 0x00028, data);
}
master4_invalid_status = master4_invalid_backupflg;
}
#endif /*CONFIG_SHLCDC_BOARD*/
/* start OVERLAY pipe */
mdp_pipe_kickoff(MDP_OVERLAY0_TERM, mfd);
#ifdef CONFIG_SHLCDC_BOARD
up(&mfd->sem);
/* wait until DMA finishes the current job */
if (!wait_for_completion_timeout(&pipe->comp, msecs_to_jiffies(100))) {
printk(KERN_ERR "%s: completion_timeout\n", __func__);
mdp4_overlay0_done_mddi(mfd->dma);
mdp_hw_cursor_done();
}
#endif /*CONFIG_SHLCDC_BOARD*/
}
