static int tvenc_on(struct platform_device *pdev)
{
int ret = 0;
#ifndef CONFIG_MSM_BUS_SCALING
struct msm_fb_data_type *mfd = platform_get_drvdata(pdev);
#endif
#ifdef CONFIG_MSM_BUS_SCALING
if (tvenc_bus_scale_handle > 0)
msm_bus_scale_client_update_request(tvenc_bus_scale_handle,
1);
#else
if (mfd->ebi1_clk)
clk_enable(mfd->ebi1_clk);
#endif
mdp_set_core_clk(1);
mdp4_extn_disp = 1;
if (tvenc_pdata && tvenc_pdata->pm_vid_en)
ret = tvenc_pdata->pm_vid_en(1);
if (ret) {
pr_err("%s: pm_vid_en(on) failed! %d\n",
__func__, ret);
return ret;
}
ret = tvenc_set_clock(CLOCK_ON);
if (ret) {
pr_err("%s: tvenc_set_clock(CLOCK_ON) failed! %d\n",
__func__, ret);
tvenc_pdata->pm_vid_en(0);
goto error;
}
ret = panel_next_on(pdev);
if (ret) {
pr_err("%s: tvout_on failed! %d\n",
__func__, ret);
tvenc_set_clock(CLOCK_OFF);
tvenc_pdata->pm_vid_en(0);
}
error:
return ret;
}
int mdp_hw_init(struct mdp_info *mdp)
{
int ret;
ret = mdp_out_if_register(&mdp->mdp_dev, MSM_MDDI_PMDH_INTERFACE, mdp,
MDP_DMA_P_DONE, mdp_dma_to_mddi);
if (ret)
return ret;
mdp_writel(mdp, 0, MDP_INTR_ENABLE);
mdp_writel(mdp, 0, MDP_DMA_P_HIST_INTR_ENABLE);
/* XXX: why set this? QCT says it should be > mdp_pclk,
* but they never set the clkrate of pclk */
mdp_set_core_clk(4);
pr_info("%s: mdp_clk=%lu\n", __func__, clk_get_rate(mdp->clk));
/* TODO: Configure the VG/RGB pipes fetch data */
/* this should work for any mdp_clk freq.
* TODO: use different value for mdp_clk freqs >= 90Mhz */
mdp_writel(mdp, 0x27, MDP_DMA_P_FETCH_CFG); /* 8 bytes-burst x 8 req */
mdp_writel(mdp, 0x3, MDP_EBI2_PORTMAP_MODE);
/* 3 pending requests */
mdp_writel(mdp, 0x02222, MDP_MAX_RD_PENDING_CMD_CONFIG);
/* no overlay processing, sw controls everything */
mdp_writel(mdp, 0, MDP_LAYERMIXER_IN_CFG);
mdp_writel(mdp, 1 << 3, MDP_OVERLAYPROC0_CFG);
mdp_writel(mdp, 1 << 3, MDP_OVERLAYPROC1_CFG);
/* XXX: HACK! hardcode to do mddi on primary */
mdp_writel(mdp, 0x2, MDP_DISP_INTF_SEL);
return 0;
}
static int dtv_on(struct platform_device *pdev)
{
int ret = 0;
struct msm_fb_data_type *mfd;
unsigned long panel_pixclock_freq , pm_qos_rate;
mfd = platform_get_drvdata(pdev);
panel_pixclock_freq = mfd->fbi->var.pixclock;
#ifdef CONFIG_MSM_NPA_SYSTEM_BUS
pm_qos_rate = MSM_AXI_FLOW_MDP_DTV_720P_2BPP;
#else
if (panel_pixclock_freq > 58000000)
/* pm_qos_rate should be in Khz */
pm_qos_rate = panel_pixclock_freq / 1000 ;
else
pm_qos_rate = 58000;
#endif
mdp_set_core_clk(1);
mdp4_extn_disp = 1;
#ifdef CONFIG_MSM_BUS_SCALING
if (dtv_bus_scale_handle > 0)
msm_bus_scale_client_update_request(dtv_bus_scale_handle,
1);
#else
if (ebi1_clk) {
clk_set_rate(ebi1_clk, pm_qos_rate * 1000);
clk_enable(ebi1_clk);
}
#endif
mfd = platform_get_drvdata(pdev);
ret = clk_set_rate(tv_src_clk, mfd->fbi->var.pixclock);
if (ret) {
pr_info("%s: clk_set_rate(%d) failed\n", __func__,
mfd->fbi->var.pixclock);
if (mfd->fbi->var.pixclock == 27030000)
mfd->fbi->var.pixclock = 27000000;
ret = clk_set_rate(tv_src_clk, mfd->fbi->var.pixclock);
}
pr_info("%s: tv_src_clk=%dkHz, pm_qos_rate=%ldkHz, [%d]\n", __func__,
mfd->fbi->var.pixclock/1000, pm_qos_rate, ret);
clk_enable(tv_enc_clk);
clk_enable(tv_dac_clk);
clk_enable(hdmi_clk);
clk_reset(hdmi_clk, CLK_RESET_ASSERT);
udelay(20);
clk_reset(hdmi_clk, CLK_RESET_DEASSERT);
if (mdp_tv_clk)
clk_enable(mdp_tv_clk);
if (dtv_pdata && dtv_pdata->lcdc_power_save)
dtv_pdata->lcdc_power_save(1);
if (dtv_pdata && dtv_pdata->lcdc_gpio_config)
ret = dtv_pdata->lcdc_gpio_config(1);
ret = panel_next_on(pdev);
return ret;
}
