int dsi_cmd_panel_config (struct msm_panel_info *pinfo, struct lcdc_panel_info *plcdc) { int ret = NO_ERROR; uint8_t lane_en = 0; uint8_t ystride = pinfo->bpp / 8; uint32_t panel_width = pinfo->xres; uint32_t final_xres, final_yres, final_width; uint32_t final_height; struct dsc_desc *dsc = NULL; if (pinfo->mipi.dual_dsi) panel_width = panel_width / 2; if (pinfo->mipi.data_lane0) lane_en |= (1 << 0); if (pinfo->mipi.data_lane1) lane_en |= (1 << 1); if (pinfo->mipi.data_lane2) lane_en |= (1 << 2); if (pinfo->mipi.data_lane3) lane_en |= (1 << 3); if (pinfo->compression_mode == COMPRESSION_DSC) { dsc = &pinfo->dsc; panel_width = dsc->pclk_per_line; } final_xres = panel_width; final_width = panel_width + pinfo->lcdc.xres_pad; if (pinfo->compression_mode == COMPRESSION_FBC) { if (pinfo->fbc.enabled && pinfo->fbc.comp_ratio) { final_xres /= pinfo->fbc.comp_ratio; final_width /= pinfo->fbc.comp_ratio; dprintf(SPEW, "DSI xres =%d final_width=%d\n", final_xres, final_width); } } final_yres = pinfo->yres; final_height = pinfo->yres + pinfo->lcdc.yres_pad; ret = mdss_dsi_cmd_mode_config(pinfo, final_width, final_height, final_xres, final_yres, pinfo->mipi.dst_format, ystride, lane_en, pinfo->mipi.interleave_mode, pinfo->mipi.ctl_base); if (pinfo->mipi.dual_dsi) ret = mdss_dsi_cmd_mode_config(pinfo, final_width, final_height, final_xres, final_yres, pinfo->mipi.dst_format, ystride, lane_en, pinfo->mipi.interleave_mode, pinfo->mipi.sctl_base); return ret; }
int mipi_truly_cmd_wvga_config(void *pdata) { int ret = NO_ERROR; /* 2 Lanes -- Enables Data Lane0, 1 */ unsigned char lane_en = 0x3; unsigned long low_pwr_stop_mode = 0; /* Needed or else will have blank line at top of display */ unsigned char eof_bllp_pwr = 0x9; unsigned char interleav = 0; struct lcdc_panel_info *lcdc = NULL; struct msm_panel_info *pinfo = (struct msm_panel_info *) pdata; if (pinfo == NULL) return ERR_INVALID_ARGS; lcdc = &(pinfo->lcdc); if (lcdc == NULL) return ERR_INVALID_ARGS; ret = mdss_dsi_cmd_mode_config((pinfo->xres + lcdc->xres_pad), (pinfo->yres + lcdc->yres_pad), (pinfo->xres), (pinfo->yres), pinfo->mipi.dst_format, pinfo->bpp / 8, lane_en, 0); return ret; }
int dsi_cmd_panel_config (struct msm_panel_info *pinfo, struct lcdc_panel_info *plcdc) { int ret = NO_ERROR; uint8_t lane_en = 0; uint8_t ystride = pinfo->bpp / 8; uint32_t panel_width = pinfo->xres; if (pinfo->mipi.dual_dsi) panel_width = panel_width / 2; if (pinfo->mipi.data_lane0) lane_en |= (1 << 0); if (pinfo->mipi.data_lane1) lane_en |= (1 << 1); if (pinfo->mipi.data_lane2) lane_en |= (1 << 2); if (pinfo->mipi.data_lane3) lane_en |= (1 << 3); ret = mdss_dsi_cmd_mode_config((panel_width + plcdc->xres_pad), (pinfo->yres + plcdc->yres_pad), panel_width, (pinfo->yres), pinfo->mipi.dst_format, ystride, lane_en, pinfo->mipi.interleave_mode, MIPI_DSI0_BASE); if (pinfo->mipi.dual_dsi) ret = mdss_dsi_cmd_mode_config((panel_width + plcdc->xres_pad), (pinfo->yres + plcdc->yres_pad), panel_width, (pinfo->yres), pinfo->mipi.dst_format, ystride, lane_en, pinfo->mipi.interleave_mode, MIPI_DSI1_BASE); return ret; }