int dsi_video_panel_config(struct msm_panel_info *pinfo,
struct lcdc_panel_info *plcdc
)
{
int ret = NO_ERROR;
uint8_t lane_enable = 0;
uint32_t panel_width = pinfo->xres;
if (pinfo->mipi.dual_dsi)
panel_width = panel_width / 2;
if (pinfo->mipi.data_lane0)
lane_enable |= (1 << 0);
if (pinfo->mipi.data_lane1)
lane_enable |= (1 << 1);
if (pinfo->mipi.data_lane2)
lane_enable |= (1 << 2);
if (pinfo->mipi.data_lane3)
lane_enable |= (1 << 3);
ret = mdss_dsi_video_mode_config((panel_width + plcdc->xres_pad),
(pinfo->yres + plcdc->yres_pad),
(panel_width),
(pinfo->yres),
(plcdc->h_front_porch),
(plcdc->h_back_porch + plcdc->h_pulse_width),
(plcdc->v_front_porch),
(plcdc->v_back_porch + plcdc->v_pulse_width),
(plcdc->h_pulse_width),
(plcdc->v_pulse_width),
pinfo->mipi.dst_format,
pinfo->mipi.traffic_mode,
lane_enable,
pinfo->mipi.hsa_power_stop,
pinfo->mipi.eof_bllp_power,
pinfo->mipi.interleave_mode,
MIPI_DSI0_BASE);
if (pinfo->mipi.dual_dsi)
ret = mdss_dsi_video_mode_config(
(panel_width + plcdc->xres_pad),
(pinfo->yres + plcdc->yres_pad),
(panel_width),
(pinfo->yres),
(plcdc->h_front_porch),
(plcdc->h_back_porch + plcdc->h_pulse_width),
(plcdc->v_front_porch),
(plcdc->v_back_porch + plcdc->v_pulse_width),
(plcdc->h_pulse_width),
(plcdc->v_pulse_width),
pinfo->mipi.dst_format,
pinfo->mipi.traffic_mode,
lane_enable,
pinfo->mipi.hsa_power_stop,
pinfo->mipi.eof_bllp_power,
pinfo->mipi.interleave_mode,
MIPI_DSI1_BASE);
return ret;
}
int mipi_truly_video_wvga_config(void *pdata)
{
int ret = NO_ERROR;
/* 2 Lanes -- Enables Data Lane0, 1 */
unsigned char lane_en = 3;
unsigned long low_pwr_stop_mode = 0;
/* Needed or else will have blank line at top of display */
unsigned char eof_bllp_pwr = 0x9;
unsigned char interleav = 0;
struct lcdc_panel_info *lcdc = NULL;
struct msm_panel_info *pinfo = (struct msm_panel_info *) pdata;
if (pinfo == NULL)
return ERR_INVALID_ARGS;
lcdc = &(pinfo->lcdc);
if (lcdc == NULL)
return ERR_INVALID_ARGS;
ret = mdss_dsi_video_mode_config((pinfo->xres),
(pinfo->yres),
(pinfo->xres),
(pinfo->yres),
(lcdc->h_front_porch),
(lcdc->h_back_porch + lcdc->h_pulse_width),
(lcdc->v_front_porch),
(lcdc->v_back_porch + lcdc->v_pulse_width),
(lcdc->h_pulse_width),
(lcdc->v_pulse_width),
pinfo->mipi.dst_format,
pinfo->mipi.traffic_mode,
lane_en,
low_pwr_stop_mode,
eof_bllp_pwr,
interleav,
MIPI_DSI0_BASE);
return ret;
}
int dsi_video_panel_config(struct msm_panel_info *pinfo,
struct lcdc_panel_info *plcdc
)
{
int ret = NO_ERROR;
uint8_t lane_enable = 0;
uint32_t panel_width = pinfo->xres;
uint32_t final_xres, final_yres, final_width;
uint32_t final_height, final_hbp, final_hfp,final_vbp;
uint32_t final_vfp, final_hpw, final_vpw, low_pwr_stop;
struct dsc_desc *dsc = NULL;
if (pinfo->mipi.dual_dsi)
panel_width = panel_width / 2;
if (pinfo->mipi.data_lane0)
lane_enable |= (1 << 0);
if (pinfo->mipi.data_lane1)
lane_enable |= (1 << 1);
if (pinfo->mipi.data_lane2)
lane_enable |= (1 << 2);
if (pinfo->mipi.data_lane3)
lane_enable |= (1 << 3);
if (pinfo->compression_mode == COMPRESSION_DSC) {
dsc = &pinfo->dsc;
panel_width = dsc->pclk_per_line;
}
final_xres = panel_width;
final_width = panel_width + pinfo->lcdc.xres_pad;
if (pinfo->fbc.enabled && pinfo->fbc.comp_ratio) {
final_xres /= pinfo->fbc.comp_ratio;
final_width /= pinfo->fbc.comp_ratio;
dprintf(SPEW, "DSI xres =%d final_width=%d\n",
final_xres, final_width);
}
final_yres = pinfo->yres;
final_height = pinfo->yres + pinfo->lcdc.yres_pad;
final_hbp = pinfo->lcdc.h_back_porch;
final_hfp = pinfo->lcdc.h_front_porch;
final_vbp = pinfo->lcdc.v_back_porch;
final_vfp = pinfo->lcdc.v_front_porch;
final_hpw = pinfo->lcdc.h_pulse_width;
final_vpw = pinfo->lcdc.v_pulse_width;
low_pwr_stop = (pinfo->mipi.hfp_power_stop << 8) |
(pinfo->mipi.hbp_power_stop << 4) |
pinfo->mipi.hsa_power_stop;
ret = mdss_dsi_video_mode_config(pinfo,
final_width, final_height,
final_xres, final_yres,
final_hfp, final_hbp + final_hpw,
final_vfp, final_vbp + final_vpw,
final_hpw, final_vpw,
pinfo->mipi.dst_format,
pinfo->mipi.traffic_mode,
lane_enable,
pinfo->mipi.pulse_mode_hsa_he,
low_pwr_stop,
pinfo->mipi.eof_bllp_power,
pinfo->mipi.interleave_mode,
pinfo->mipi.ctl_base);
if (pinfo->mipi.dual_dsi)
ret = mdss_dsi_video_mode_config(pinfo,
final_width, final_height,
final_xres, final_yres,
final_hfp, final_hbp + final_hpw,
final_vfp, final_vbp + final_vpw,
final_hpw, final_vpw,
pinfo->mipi.dst_format,
pinfo->mipi.traffic_mode,
lane_enable,
pinfo->mipi.pulse_mode_hsa_he,
low_pwr_stop,
pinfo->mipi.eof_bllp_power,
pinfo->mipi.interleave_mode,
pinfo->mipi.sctl_base);
return ret;
}
int dsi_video_panel_config(struct msm_panel_info *pinfo,
struct lcdc_panel_info *plcdc
)
{
int ret = NO_ERROR;
uint8_t lane_enable = 0;
uint32_t panel_width = pinfo->xres;
uint32_t final_xres, final_yres, final_width;
uint32_t final_height, final_hbp, final_hfp,final_vbp;
uint32_t final_vfp, final_hpw, final_vpw;
if (pinfo->mipi.dual_dsi)
panel_width = panel_width / 2;
if (pinfo->mipi.data_lane0)
lane_enable |= (1 << 0);
if (pinfo->mipi.data_lane1)
lane_enable |= (1 << 1);
if (pinfo->mipi.data_lane2)
lane_enable |= (1 << 2);
if (pinfo->mipi.data_lane3)
lane_enable |= (1 << 3);
final_xres = panel_width;
final_width = panel_width + pinfo->lcdc.xres_pad;
if (pinfo->fbc.enabled && pinfo->fbc.comp_ratio) {
final_xres /= pinfo->fbc.comp_ratio;
final_width /= pinfo->fbc.comp_ratio;
dprintf(SPEW, "DSI xres =%d final_width=%d\n", final_xres,
final_width);
}
final_yres = pinfo->yres;
final_height = pinfo->yres + pinfo->lcdc.yres_pad;
final_hbp = pinfo->lcdc.h_back_porch;
final_hfp = pinfo->lcdc.h_front_porch;
final_vbp = pinfo->lcdc.v_back_porch;
final_vfp = pinfo->lcdc.v_front_porch;
final_hpw = pinfo->lcdc.h_pulse_width;
final_vpw = pinfo->lcdc.v_pulse_width;
ret = mdss_dsi_video_mode_config(final_width, final_height,
final_xres, final_yres,
final_hfp, final_hbp + final_hpw,
final_vfp, final_vbp + final_vpw,
final_hpw, final_vpw,
pinfo->mipi.dst_format,
pinfo->mipi.traffic_mode,
lane_enable,
pinfo->mipi.hsa_power_stop,
pinfo->mipi.eof_bllp_power,
pinfo->mipi.interleave_mode,
MIPI_DSI0_BASE);
if (pinfo->mipi.dual_dsi)
ret = mdss_dsi_video_mode_config(final_width, final_height,
final_xres, final_yres,
final_hfp, final_hbp + final_hpw,
final_vfp, final_vbp + final_vpw,
final_hpw, final_vpw,
pinfo->mipi.dst_format,
pinfo->mipi.traffic_mode,
lane_enable,
pinfo->mipi.hsa_power_stop,
pinfo->mipi.eof_bllp_power,
pinfo->mipi.interleave_mode,
MIPI_DSI1_BASE);
return ret;
}
