void meson_vpp_init(struct meson_drm *priv) { /* set dummy data default YUV black */ if (meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu")) writel_relaxed(0x108080, priv->io_base + _REG(VPP_DUMMY_DATA1)); else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu")) { writel_bits_relaxed(0xff << 16, 0xff << 16, priv->io_base + _REG(VIU_MISC_CTRL1)); writel_relaxed(0x20000, priv->io_base + _REG(VPP_DOLBY_CTRL)); writel_relaxed(0x1020080, priv->io_base + _REG(VPP_DUMMY_DATA1)); } /* Initialize vpu fifo control registers */ writel_relaxed(readl_relaxed(priv->io_base + _REG(VPP_OFIFO_SIZE)) | 0x77f, priv->io_base + _REG(VPP_OFIFO_SIZE)); writel_relaxed(0x08080808, priv->io_base + _REG(VPP_HOLD_LINES)); /* Turn off preblend */ writel_bits_relaxed(VPP_PREBLEND_ENABLE, 0, priv->io_base + _REG(VPP_MISC)); /* Turn off POSTBLEND */ writel_bits_relaxed(VPP_POSTBLEND_ENABLE, 0, priv->io_base + _REG(VPP_MISC)); /* Force all planes off */ writel_bits_relaxed(VPP_OSD1_POSTBLEND | VPP_OSD2_POSTBLEND | VPP_VD1_POSTBLEND | VPP_VD2_POSTBLEND | VPP_VD1_PREBLEND | VPP_VD2_PREBLEND, 0, priv->io_base + _REG(VPP_MISC)); /* Setup default VD settings */ writel_relaxed(4096, priv->io_base + _REG(VPP_PREBLEND_VD1_H_START_END)); writel_relaxed(4096, priv->io_base + _REG(VPP_BLEND_VD2_H_START_END)); /* Disable Scalers */ writel_relaxed(0, priv->io_base + _REG(VPP_OSD_SC_CTRL0)); writel_relaxed(0, priv->io_base + _REG(VPP_OSD_VSC_CTRL0)); writel_relaxed(0, priv->io_base + _REG(VPP_OSD_HSC_CTRL0)); writel_relaxed(4 | (4 << 8) | BIT(15), priv->io_base + _REG(VPP_SC_MISC)); writel_relaxed(1, priv->io_base + _REG(VPP_VADJ_CTRL)); /* Write in the proper filter coefficients. */ meson_vpp_write_scaling_filter_coefs(priv, vpp_filter_coefs_4point_bspline, false); meson_vpp_write_scaling_filter_coefs(priv, vpp_filter_coefs_4point_bspline, true); /* Write the VD proper filter coefficients. */ meson_vpp_write_vd_scaling_filter_coefs(priv, vpp_filter_coefs_bicubic, false); meson_vpp_write_vd_scaling_filter_coefs(priv, vpp_filter_coefs_bicubic, true); }
void meson_viu_init(struct meson_drm *priv) { uint32_t reg; /* Disable OSDs */ writel_bits_relaxed(BIT(0) | BIT(21), 0, priv->io_base + _REG(VIU_OSD1_CTRL_STAT)); writel_bits_relaxed(BIT(0) | BIT(21), 0, priv->io_base + _REG(VIU_OSD2_CTRL_STAT)); /* On GXL/GXM, Use the 10bit HDR conversion matrix */ if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") || meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu")) meson_viu_load_matrix(priv); /* Initialize OSD1 fifo control register */ reg = BIT(0) | /* Urgent DDR request priority */ (4 << 5) | /* hold_fifo_lines */ (3 << 10) | /* burst length 64 */ (32 << 12) | /* fifo_depth_val: 32*8=256 */ (2 << 22) | /* 4 words in 1 burst */ (2 << 24); writel_relaxed(reg, priv->io_base + _REG(VIU_OSD1_FIFO_CTRL_STAT)); writel_relaxed(reg, priv->io_base + _REG(VIU_OSD2_FIFO_CTRL_STAT)); /* Set OSD alpha replace value */ writel_bits_relaxed(0xff << OSD_REPLACE_SHIFT, 0xff << OSD_REPLACE_SHIFT, priv->io_base + _REG(VIU_OSD1_CTRL_STAT2)); writel_bits_relaxed(0xff << OSD_REPLACE_SHIFT, 0xff << OSD_REPLACE_SHIFT, priv->io_base + _REG(VIU_OSD2_CTRL_STAT2)); /* Disable VD1 AFBC */ /* di_mif0_en=0 mif0_to_vpp_en=0 di_mad_en=0 */ writel_bits_relaxed(0x7 << 16, 0, priv->io_base + _REG(VIU_MISC_CTRL0)); /* afbc vd1 set=0 */ writel_bits_relaxed(BIT(20), 0, priv->io_base + _REG(VIU_MISC_CTRL0)); writel_relaxed(0, priv->io_base + _REG(AFBC_ENABLE)); writel_relaxed(0x00FF00C0, priv->io_base + _REG(VD1_IF0_LUMA_FIFO_SIZE)); writel_relaxed(0x00FF00C0, priv->io_base + _REG(VD2_IF0_LUMA_FIFO_SIZE)); priv->viu.osd1_enabled = false; priv->viu.osd1_commit = false; priv->viu.osd1_interlace = false; }
static int meson_dw_hdmi_bind(struct device *dev, struct device *master, void *data) { struct platform_device *pdev = to_platform_device(dev); const struct meson_dw_hdmi_data *match; struct meson_dw_hdmi *meson_dw_hdmi; struct drm_device *drm = data; struct meson_drm *priv = drm->dev_private; struct dw_hdmi_plat_data *dw_plat_data; struct drm_encoder *encoder; struct resource *res; int irq; int ret; DRM_DEBUG_DRIVER("\n"); if (!meson_hdmi_connector_is_available(dev)) { dev_info(drm->dev, "HDMI Output connector not available\n"); return -ENODEV; } match = of_device_get_match_data(&pdev->dev); if (!match) { dev_err(&pdev->dev, "failed to get match data\n"); return -ENODEV; } meson_dw_hdmi = devm_kzalloc(dev, sizeof(*meson_dw_hdmi), GFP_KERNEL); if (!meson_dw_hdmi) return -ENOMEM; meson_dw_hdmi->priv = priv; meson_dw_hdmi->dev = dev; meson_dw_hdmi->data = match; dw_plat_data = &meson_dw_hdmi->dw_plat_data; encoder = &meson_dw_hdmi->encoder; meson_dw_hdmi->hdmi_supply = devm_regulator_get_optional(dev, "hdmi"); if (IS_ERR(meson_dw_hdmi->hdmi_supply)) { if (PTR_ERR(meson_dw_hdmi->hdmi_supply) == -EPROBE_DEFER) return -EPROBE_DEFER; meson_dw_hdmi->hdmi_supply = NULL; } else { ret = regulator_enable(meson_dw_hdmi->hdmi_supply); if (ret) return ret; } meson_dw_hdmi->hdmitx_apb = devm_reset_control_get_exclusive(dev, "hdmitx_apb"); if (IS_ERR(meson_dw_hdmi->hdmitx_apb)) { dev_err(dev, "Failed to get hdmitx_apb reset\n"); return PTR_ERR(meson_dw_hdmi->hdmitx_apb); } meson_dw_hdmi->hdmitx_ctrl = devm_reset_control_get_exclusive(dev, "hdmitx"); if (IS_ERR(meson_dw_hdmi->hdmitx_ctrl)) { dev_err(dev, "Failed to get hdmitx reset\n"); return PTR_ERR(meson_dw_hdmi->hdmitx_ctrl); } meson_dw_hdmi->hdmitx_phy = devm_reset_control_get_exclusive(dev, "hdmitx_phy"); if (IS_ERR(meson_dw_hdmi->hdmitx_phy)) { dev_err(dev, "Failed to get hdmitx_phy reset\n"); return PTR_ERR(meson_dw_hdmi->hdmitx_phy); } res = platform_get_resource(pdev, IORESOURCE_MEM, 0); meson_dw_hdmi->hdmitx = devm_ioremap_resource(dev, res); if (IS_ERR(meson_dw_hdmi->hdmitx)) return PTR_ERR(meson_dw_hdmi->hdmitx); meson_dw_hdmi->hdmi_pclk = devm_clk_get(dev, "isfr"); if (IS_ERR(meson_dw_hdmi->hdmi_pclk)) { dev_err(dev, "Unable to get HDMI pclk\n"); return PTR_ERR(meson_dw_hdmi->hdmi_pclk); } clk_prepare_enable(meson_dw_hdmi->hdmi_pclk); meson_dw_hdmi->venci_clk = devm_clk_get(dev, "venci"); if (IS_ERR(meson_dw_hdmi->venci_clk)) { dev_err(dev, "Unable to get venci clk\n"); return PTR_ERR(meson_dw_hdmi->venci_clk); } clk_prepare_enable(meson_dw_hdmi->venci_clk); dw_plat_data->regm = devm_regmap_init(dev, NULL, meson_dw_hdmi, &meson_dw_hdmi_regmap_config); if (IS_ERR(dw_plat_data->regm)) return PTR_ERR(dw_plat_data->regm); irq = platform_get_irq(pdev, 0); if (irq < 0) { dev_err(dev, "Failed to get hdmi top irq\n"); return irq; } ret = devm_request_threaded_irq(dev, irq, dw_hdmi_top_irq, dw_hdmi_top_thread_irq, IRQF_SHARED, "dw_hdmi_top_irq", meson_dw_hdmi); if (ret) { dev_err(dev, "Failed to request hdmi top irq\n"); return ret; } /* Encoder */ drm_encoder_helper_add(encoder, &meson_venc_hdmi_encoder_helper_funcs); ret = drm_encoder_init(drm, encoder, &meson_venc_hdmi_encoder_funcs, DRM_MODE_ENCODER_TMDS, "meson_hdmi"); if (ret) { dev_err(priv->dev, "Failed to init HDMI encoder\n"); return ret; } encoder->possible_crtcs = BIT(0); DRM_DEBUG_DRIVER("encoder initialized\n"); /* Enable clocks */ regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, 0xffff, 0x100); /* Bring HDMITX MEM output of power down */ regmap_update_bits(priv->hhi, HHI_MEM_PD_REG0, 0xff << 8, 0); /* Reset HDMITX APB & TX & PHY */ reset_control_reset(meson_dw_hdmi->hdmitx_apb); reset_control_reset(meson_dw_hdmi->hdmitx_ctrl); reset_control_reset(meson_dw_hdmi->hdmitx_phy); /* Enable APB3 fail on error */ if (!meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) { writel_bits_relaxed(BIT(15), BIT(15), meson_dw_hdmi->hdmitx + HDMITX_TOP_CTRL_REG); writel_bits_relaxed(BIT(15), BIT(15), meson_dw_hdmi->hdmitx + HDMITX_DWC_CTRL_REG); } /* Bring out of reset */ meson_dw_hdmi->data->top_write(meson_dw_hdmi, HDMITX_TOP_SW_RESET, 0); msleep(20); meson_dw_hdmi->data->top_write(meson_dw_hdmi, HDMITX_TOP_CLK_CNTL, 0xff); /* Enable HDMI-TX Interrupt */ meson_dw_hdmi->data->top_write(meson_dw_hdmi, HDMITX_TOP_INTR_STAT_CLR, HDMITX_TOP_INTR_CORE); meson_dw_hdmi->data->top_write(meson_dw_hdmi, HDMITX_TOP_INTR_MASKN, HDMITX_TOP_INTR_CORE); /* Bridge / Connector */ dw_plat_data->mode_valid = dw_hdmi_mode_valid; dw_plat_data->phy_ops = &meson_dw_hdmi_phy_ops; dw_plat_data->phy_name = "meson_dw_hdmi_phy"; dw_plat_data->phy_data = meson_dw_hdmi; dw_plat_data->input_bus_format = MEDIA_BUS_FMT_YUV8_1X24; dw_plat_data->input_bus_encoding = V4L2_YCBCR_ENC_709; platform_set_drvdata(pdev, meson_dw_hdmi); meson_dw_hdmi->hdmi = dw_hdmi_bind(pdev, encoder, &meson_dw_hdmi->dw_plat_data); if (IS_ERR(meson_dw_hdmi->hdmi)) return PTR_ERR(meson_dw_hdmi->hdmi); DRM_DEBUG_DRIVER("HDMI controller initialized\n"); return 0; }