int board_eth_init(bd_t *bis) { int rv, n = 0; const char *devname; struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; rv = handle_mac_address(); if (rv) printf("No MAC address found!\n"); writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel); board_phy_init(); rv = cpsw_register(&cpsw_data); if (rv < 0) printf("Error %d registering CPSW switch\n", rv); else n += rv; /* * CPSW RGMII Internal Delay Mode is not supported in all PVT * operating points. So we must set the TX clock delay feature * in the AR8051 PHY. Since we only support a single ethernet * device, we only do this for the first instance. */ devname = miiphy_get_current_dev(); miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG, AR8051_DEBUG_RGMII_CLK_DLY_REG); miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG, AR8051_RGMII_TX_CLK_DLY); return n; }
static void enbw_cmc_switch(int port, int on) { const char *devname; unsigned char phyaddr = 3; unsigned char reg = 0; unsigned short data; if (port == 1) phyaddr = 2; devname = miiphy_get_current_dev(); if (!devname) { printf("Error: no mii device\n"); return; } if (miiphy_read(devname, phyaddr, reg, &data) != 0) { printf("Error reading from the PHY addr=%02x reg=%02x\n", phyaddr, reg); return; } if (on) data &= ~PHY_POWER; else data |= PHY_POWER; if (miiphy_write(devname, phyaddr, reg, data) != 0) { printf("Error writing to the PHY addr=%02x reg=%02x\n", phyaddr, reg); return; } }
void higmac_mdiobus_driver_exit(void) { if (!miiphy_get_current_dev()) return; higmac_mdio_exit(&higmac_mdio0); higmac_mdio_exit(&higmac_mdio1); }
void hieth_mdiobus_driver_exit(void) { /*add this to avoid the first time to use eth will print 'No such device: XXXXX' message.*/ if (!miiphy_get_current_dev()) return; /* UpEther PHY exit */ if(!get_phy_device(U_PHY_NAME,U_PHY_ADDR)) { miiphy_reset(U_PHY_NAME, U_PHY_ADDR); } /* DownEther PHY exit */ if(!get_phy_device(D_PHY_NAME,D_PHY_ADDR)) { miiphy_reset(D_PHY_NAME, D_PHY_ADDR); } hieth_mdio_exit(&mdio_bus_ld); }
void stmmac_mdiobus_driver_exit(void) { if (!miiphy_get_current_dev()) return; }
/* * MII device/info/read/write * * Syntax: * mii device {devname} * mii info {addr} * mii read {addr} {reg} * mii write {addr} {reg} {data} */ int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { char op; unsigned char addr, reg; unsigned short data; int rcode = 0; char *devname; if (argc < 2) { printf ("Usage:\n%s\n", cmdtp->usage); return 1; } #if defined(CONFIG_8xx) || defined(CONFIG_MCF52x2) mii_init (); #endif /* * We use the last specified parameters, unless new ones are * entered. */ op = last_op; addr = last_addr; data = last_data; reg = last_reg; if ((flag & CMD_FLAG_REPEAT) == 0) { op = argv[1][0]; if (argc >= 3) addr = simple_strtoul (argv[2], NULL, 16); if (argc >= 4) reg = simple_strtoul (argv[3], NULL, 16); if (argc >= 5) data = simple_strtoul (argv[4], NULL, 16); } /* use current device */ devname = miiphy_get_current_dev(); /* * check device/read/write/list. */ if (op == 'i') { unsigned char j, start, end; unsigned int oui; unsigned char model; unsigned char rev; /* * Look for any and all PHYs. Valid addresses are 0..31. */ if (argc >= 3) { start = addr; end = addr + 1; } else { start = 0; end = 31; } for (j = start; j < end; j++) { if (miiphy_info (devname, j, &oui, &model, &rev) == 0) { printf ("PHY 0x%02X: " "OUI = 0x%04X, " "Model = 0x%02X, " "Rev = 0x%02X, " "%3dbase%s, %s\n", j, oui, model, rev, miiphy_speed (devname, j), miiphy_is_1000base_x (devname, j) ? "X" : "T", (miiphy_duplex (devname, j) == FULL) ? "FDX" : "HDX"); } } } else if (op == 'r') { if (miiphy_read (devname, addr, reg, &data) != 0) { puts ("Error reading from the PHY\n"); rcode = 1; } else { printf ("%04X\n", data & 0x0000FFFF); } } else if (op == 'w') { if (miiphy_write (devname, addr, reg, data) != 0) { puts ("Error writing to the PHY\n"); rcode = 1; } } else if (op == 'd') { if (argc == 2) miiphy_listdev (); else miiphy_set_current_dev (argv[2]); } else { printf ("Usage:\n%s\n", cmdtp->usage); return 1; } /* * Save the parameters for repeats. */ last_op = op; last_addr = addr; last_data = data; last_reg = reg; return rcode; }
int board_eth_init(bd_t *bis) { int rv, n = 0; uint8_t mac_addr[6]; uint32_t mac_hi, mac_lo; __maybe_unused struct am335x_baseboard_id header; /* try reading mac address from efuse */ mac_lo = readl(&cdev->macid0l); mac_hi = readl(&cdev->macid0h); mac_addr[0] = mac_hi & 0xFF; mac_addr[1] = (mac_hi & 0xFF00) >> 8; mac_addr[2] = (mac_hi & 0xFF0000) >> 16; mac_addr[3] = (mac_hi & 0xFF000000) >> 24; mac_addr[4] = mac_lo & 0xFF; mac_addr[5] = (mac_lo & 0xFF00) >> 8; #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) if (!getenv("ethaddr")) { printf("<ethaddr> not set. Validating first E-fuse MAC\n"); if (is_valid_ether_addr(mac_addr)) eth_setenv_enetaddr("ethaddr", mac_addr); } #ifdef CONFIG_DRIVER_TI_CPSW mac_lo = readl(&cdev->macid1l); mac_hi = readl(&cdev->macid1h); mac_addr[0] = mac_hi & 0xFF; mac_addr[1] = (mac_hi & 0xFF00) >> 8; mac_addr[2] = (mac_hi & 0xFF0000) >> 16; mac_addr[3] = (mac_hi & 0xFF000000) >> 24; mac_addr[4] = mac_lo & 0xFF; mac_addr[5] = (mac_lo & 0xFF00) >> 8; if (!getenv("eth1addr")) { if (is_valid_ether_addr(mac_addr)) eth_setenv_enetaddr("eth1addr", mac_addr); } if (read_eeprom(&header) < 0) puts("Could not get board ID.\n"); if (board_is_bone(&header) || board_is_bone_lt(&header) || board_is_idk(&header)) { writel(MII_MODE_ENABLE, &cdev->miisel); cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_MII; } else { writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel); cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII; } rv = cpsw_register(&cpsw_data); if (rv < 0) printf("Error %d registering CPSW switch\n", rv); else n += rv; #endif /* * * CPSW RGMII Internal Delay Mode is not supported in all PVT * operating points. So we must set the TX clock delay feature * in the AR8051 PHY. Since we only support a single ethernet * device in U-Boot, we only do this for the first instance. */ #define AR8051_PHY_DEBUG_ADDR_REG 0x1d #define AR8051_PHY_DEBUG_DATA_REG 0x1e #define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5 #define AR8051_RGMII_TX_CLK_DLY 0x100 if (board_is_evm_sk(&header) || board_is_gp_evm(&header)) { const char *devname; devname = miiphy_get_current_dev(); miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG, AR8051_DEBUG_RGMII_CLK_DLY_REG); miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG, AR8051_RGMII_TX_CLK_DLY); } #endif #if defined(CONFIG_USB_ETHER) && \ (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT)) if (is_valid_ether_addr(mac_addr)) eth_setenv_enetaddr("usbnet_devaddr", mac_addr); rv = usb_eth_initialize(bis); if (rv < 0) printf("Error %d registering USB_ETHER\n", rv); else n += rv; #endif return n; }