int mdss_dsi_v2_phy_init(struct mipi_panel_info *mipi, uint32_t ctl_base)
{
struct mdss_dsi_phy_ctrl *pd;
uint32_t i, ln, off = 0, offset;
pd = mipi->mdss_dsi_phy_db;
/* DSI PHY configuration */
off = 0x480;
writel(pd->strength[0], ctl_base + off + (4 * 0));
writel(pd->strength[1], ctl_base + off + (4 * 2));
off = 0x470;
writel(0x10, ctl_base + off + (4 * 3));
writel(0x5F, ctl_base + off + (4 * 0));
off = 0x500;
/* use LDO mode */
writel(0x25, ctl_base + 0x4B0);
for (i = 0; i < 5; i++)
writel(pd->regulator[i], ctl_base + off + (4 * i));
mipi_dsi_calibration(ctl_base);
/* 4 lanes + clk lane configuration */
/* lane config n * (0 - 4) & DataPath setup */
for (ln = 0; ln < 5; ln++) {
off = 0x0300 + (ln * 0x40);
for (i = 0; i < 9; i++) {
offset = i + (ln * 9);
writel(pd->laneCfg[offset], ctl_base + off);
dmb();
off += 4;
}
}
off = 0x440;
for (i = 0; i < 12; i++)
writel(pd->timing[i], ctl_base + off + (4 * i));
if (1 == mipi->num_of_lanes)
writel(0x8, ctl_base + 0x200 + (4 * 11));
if (mipi->lane_swap)
writel(mipi->lane_swap, ctl_base + 0x0ac);
/* T_CLK_POST, T_CLK_PRE for CLK lane P/N HS 200 mV timing
length should > data lane HS timing length */
writel(0x41b, ctl_base + 0x0c0);
return 0;
}
void mipi_dsi_phy_init(int panel_ndx, struct msm_panel_info const *panel_info,
int target_type)
{
struct mipi_dsi_phy_ctrl *pd;
int i, off;
MIPI_OUTP(MIPI_DSI_BASE + 0x128, 0x0001);/* start phy sw reset */
#ifdef CONFIG_MACH_ACER_A9
usleep_range(2000, 2000);
#else
msleep(100);
#endif
MIPI_OUTP(MIPI_DSI_BASE + 0x128, 0x0000);/* end phy w reset */
MIPI_OUTP(MIPI_DSI_BASE + 0x500, 0x0003);/* regulator_ctrl_0 */
MIPI_OUTP(MIPI_DSI_BASE + 0x504, 0x0001);/* regulator_ctrl_1 */
MIPI_OUTP(MIPI_DSI_BASE + 0x508, 0x0001);/* regulator_ctrl_2 */
MIPI_OUTP(MIPI_DSI_BASE + 0x50c, 0x0000);/* regulator_ctrl_3 */
MIPI_OUTP(MIPI_DSI_BASE + 0x510, 0x0100);/* regulator_ctrl_4 */
pd = (panel_info->mipi).dsi_phy_db;
off = 0x0480; /* strength 0 - 2 */
for (i = 0; i < 3; i++) {
MIPI_OUTP(MIPI_DSI_BASE + off, pd->strength[i]);
wmb();
off += 4;
}
off = 0x0470; /* ctrl 0 - 3 */
for (i = 0; i < 4; i++) {
MIPI_OUTP(MIPI_DSI_BASE + off, pd->ctrl[i]);
wmb();
off += 4;
}
off = 0x0500; /* regulator ctrl 0 - 4 */
for (i = 0; i < 5; i++) {
MIPI_OUTP(MIPI_DSI_BASE + off, pd->regulator[i]);
wmb();
off += 4;
}
mipi_dsi_calibration();
off = 0x0204; /* pll ctrl 1 - 19, skip 0 */
for (i = 1; i < 20; i++) {
MIPI_OUTP(MIPI_DSI_BASE + off, pd->pll[i]);
wmb();
off += 4;
}
if (panel_info)
mipi_dsi_phy_pll_config(panel_info->clk_rate);
/* pll ctrl 0 */
MIPI_OUTP(MIPI_DSI_BASE + 0x200, pd->pll[0]);
wmb();
off = 0x0440; /* phy timing ctrl 0 - 11 */
for (i = 0; i < 12; i++) {
MIPI_OUTP(MIPI_DSI_BASE + off, pd->timing[i]);
wmb();
off += 4;
}
if (target_type == 1)
mipi_dsi_configure_serdes();
}
void mipi_dsi_phy_init(int panel_ndx, struct msm_panel_info const *panel_info,
int target_type)
{
struct mipi_dsi_phy_ctrl *pd;
int i, off;
MIPI_OUTP(MIPI_DSI_BASE + 0x128, 0x0001);/* start phy sw reset */
msleep(100);
MIPI_OUTP(MIPI_DSI_BASE + 0x128, 0x0000);/* end phy w reset */
MIPI_OUTP(MIPI_DSI_BASE + 0x2cc, 0x0003);/* regulator_ctrl_0 */
MIPI_OUTP(MIPI_DSI_BASE + 0x2d0, 0x0001);/* regulator_ctrl_1 */
MIPI_OUTP(MIPI_DSI_BASE + 0x2d4, 0x0001);/* regulator_ctrl_2 */
MIPI_OUTP(MIPI_DSI_BASE + 0x2d8, 0x0000);/* regulator_ctrl_3 */
#ifdef DSI_POWER
MIPI_OUTP(MIPI_DSI_BASE + 0x2dc, 0x0100);/* regulator_ctrl_4 */
#endif
pd = (panel_info->mipi).dsi_phy_db;
off = 0x02cc; /* regulator ctrl 0 */
for (i = 0; i < 4; i++) {
MIPI_OUTP(MIPI_DSI_BASE + off, pd->regulator[i]);
wmb();
off += 4;
}
off = 0x0260; /* phy timig ctrl 0 */
for (i = 0; i < 11; i++) {
MIPI_OUTP(MIPI_DSI_BASE + off, pd->timing[i]);
wmb();
off += 4;
}
off = 0x0290; /* ctrl 0 */
for (i = 0; i < 4; i++) {
MIPI_OUTP(MIPI_DSI_BASE + off, pd->ctrl[i]);
wmb();
off += 4;
}
off = 0x02a0; /* strength 0 */
for (i = 0; i < 4; i++) {
MIPI_OUTP(MIPI_DSI_BASE + off, pd->strength[i]);
wmb();
off += 4;
}
mipi_dsi_calibration();
off = 0x0204; /* pll ctrl 1, skip 0 */
for (i = 1; i < 21; i++) {
MIPI_OUTP(MIPI_DSI_BASE + off, pd->pll[i]);
wmb();
off += 4;
}
if (panel_info)
mipi_dsi_phy_pll_config(panel_info->clk_rate);
/* pll ctrl 0 */
MIPI_OUTP(MIPI_DSI_BASE + 0x200, pd->pll[0]);
wmb();
MIPI_OUTP(MIPI_DSI_BASE + 0x200, (pd->pll[0] | 0x01));
}
void mipi_dsi_phy_init(int panel_ndx, struct msm_panel_info const *panel_info,
int target_type)
{
struct mipi_dsi_phy_ctrl *pd;
int i, off;
MIPI_OUTP(MIPI_DSI_BASE + 0x128, 0x0001);/* start phy sw reset */
wmb();
usleep(1);
MIPI_OUTP(MIPI_DSI_BASE + 0x128, 0x0000);/* end phy w reset */
wmb();
usleep(1);
MIPI_OUTP(MIPI_DSI_BASE + 0x500, 0x0003);/* regulator_ctrl_0 */
MIPI_OUTP(MIPI_DSI_BASE + 0x504, 0x0001);/* regulator_ctrl_1 */
MIPI_OUTP(MIPI_DSI_BASE + 0x508, 0x0001);/* regulator_ctrl_2 */
MIPI_OUTP(MIPI_DSI_BASE + 0x50c, 0x0000);/* regulator_ctrl_3 */
MIPI_OUTP(MIPI_DSI_BASE + 0x510, 0x0100);/* regulator_ctrl_4 */
MIPI_OUTP(MIPI_DSI_BASE + 0x4b0, 0x04);/* DSIPHY_LDO_CNTRL */
pd = (panel_info->mipi).dsi_phy_db;
off = 0x0480; /* strength 0 - 2 */
for (i = 0; i < 3; i++) {
MIPI_OUTP(MIPI_DSI_BASE + off, pd->strength[i]);
wmb();
off += 4;
}
off = 0x0470; /* ctrl 0 - 3 */
for (i = 0; i < 4; i++) {
MIPI_OUTP(MIPI_DSI_BASE + off, pd->ctrl[i]);
wmb();
off += 4;
}
off = 0x0500; /* regulator ctrl 0 - 4 */
for (i = 0; i < 5; i++) {
MIPI_OUTP(MIPI_DSI_BASE + off, pd->regulator[i]);
wmb();
off += 4;
}
mipi_dsi_calibration();
mipi_dsi_lane_cfg(); /* lane cfgs */
mipi_dsi_bist_ctrl(); /* bist ctrl */
off = 0x0204; /* pll ctrl 1 - 19, skip 0 */
for (i = 1; i < 20; i++) {
MIPI_OUTP(MIPI_DSI_BASE + off, pd->pll[i]);
wmb();
off += 4;
}
if (!panel_info)
pr_err("%s: panel_info not initialized\n", __func__);
else
mipi_dsi_phy_pll_config(panel_info->clk_rate);
/* pll ctrl 0 */
MIPI_OUTP(MIPI_DSI_BASE + 0x200, pd->pll[0]);
wmb();
off = 0x0440; /* phy timing ctrl 0 - 11 */
for (i = 0; i < 12; i++) {
MIPI_OUTP(MIPI_DSI_BASE + off, pd->timing[i]);
wmb();
off += 4;
}
if (target_type == 1)
mipi_dsi_configure_serdes();
}
int mipi_dsi_phy_init(struct mipi_dsi_panel_config *pinfo)
{
struct mipi_dsi_phy_ctrl *pd;
uint32_t i, off = 0;
int mdp_rev;
mdp_rev = mdp_get_revision();
if (MDP_REV_303 == mdp_rev || MDP_REV_41 == mdp_rev) {
writel(0x00000001, DSIPHY_SW_RESET);
writel(0x00000000, DSIPHY_SW_RESET);
pd = (pinfo->dsi_phy_config);
off = 0x02cc; /* regulator ctrl 0 */
for (i = 0; i < 4; i++) {
writel(pd->regulator[i], MIPI_DSI_BASE + off);
off += 4;
}
off = 0x0260; /* phy timig ctrl 0 */
for (i = 0; i < 11; i++) {
writel(pd->timing[i], MIPI_DSI_BASE + off);
off += 4;
}
/* T_CLK_POST, T_CLK_PRE for CLK lane P/N HS 200 mV timing
length should > data lane HS timing length */
writel(0xa1e, DSI_CLKOUT_TIMING_CTRL);
off = 0x0290; /* ctrl 0 */
for (i = 0; i < 4; i++) {
writel(pd->ctrl[i], MIPI_DSI_BASE + off);
off += 4;
}
off = 0x02a0; /* strength 0 */
for (i = 0; i < 4; i++) {
writel(pd->strength[i], MIPI_DSI_BASE + off);
off += 4;
}
if (1 == pinfo->num_of_lanes)
pd->pll[10] |= 0x8;
off = 0x0204; /* pll ctrl 1, skip 0 */
for (i = 1; i < 21; i++) {
writel(pd->pll[i], MIPI_DSI_BASE + off);
off += 4;
}
/* pll ctrl 0 */
writel(pd->pll[0], MIPI_DSI_BASE + 0x200);
writel((pd->pll[0] | 0x01), MIPI_DSI_BASE + 0x200);
/* lane swp ctrol */
if (pinfo->lane_swap)
writel(pinfo->lane_swap, MIPI_DSI_BASE + 0xac);
} else {
writel(0x0001, MIPI_DSI_BASE + 0x128); /* start phy sw reset */
writel(0x0000, MIPI_DSI_BASE + 0x128); /* end phy w reset */
writel(0x0003, MIPI_DSI_BASE + 0x500); /* regulator_ctrl_0 */
writel(0x0001, MIPI_DSI_BASE + 0x504); /* regulator_ctrl_1 */
writel(0x0001, MIPI_DSI_BASE + 0x508); /* regulator_ctrl_2 */
writel(0x0000, MIPI_DSI_BASE + 0x50c); /* regulator_ctrl_3 */
writel(0x0100, MIPI_DSI_BASE + 0x510); /* regulator_ctrl_4 */
pd = (pinfo->dsi_phy_config);
off = 0x0480; /* strength 0 - 2 */
for (i = 0; i < 3; i++) {
writel(pd->strength[i], MIPI_DSI_BASE + off);
off += 4;
}
off = 0x0470; /* ctrl 0 - 3 */
for (i = 0; i < 4; i++) {
writel(pd->ctrl[i], MIPI_DSI_BASE + off);
off += 4;
}
off = 0x0500; /* regulator ctrl 0 - 4 */
for (i = 0; i < 5; i++) {
writel(pd->regulator[i], MIPI_DSI_BASE + off);
off += 4;
}
mipi_dsi_calibration(MIPI_DSI_BASE);
off = 0x0204; /* pll ctrl 1 - 19, skip 0 */
for (i = 1; i < 20; i++) {
writel(pd->pll[i], MIPI_DSI_BASE + off);
off += 4;
}
/* pll ctrl 0 */
writel(pd->pll[0], MIPI_DSI_BASE + 0x200);
writel((pd->pll[0] | 0x01), MIPI_DSI_BASE + 0x200);
/* Check that PHY is ready */
while (!(readl(DSIPHY_PLL_RDY) & 0x01))
udelay(1);
writel(0x202D, DSI_CLKOUT_TIMING_CTRL);
off = 0x0440; /* phy timing ctrl 0 - 11 */
for (i = 0; i < 12; i++) {
writel(pd->timing[i], MIPI_DSI_BASE + off);
off += 4;
}
}
return 0;
}
void mipi_dsi_phy_init(int panel_ndx, struct msm_panel_info const *panel_info,
int target_type)
{
struct mipi_dsi_phy_ctrl *pd;
int i, off;
MIPI_OUTP(MIPI_DSI_BASE + 0x128, 0x0001);
wmb();
usleep(1);
MIPI_OUTP(MIPI_DSI_BASE + 0x128, 0x0000);
wmb();
usleep(1);
MIPI_OUTP(MIPI_DSI_BASE + 0x2cc, 0x0003);
MIPI_OUTP(MIPI_DSI_BASE + 0x2d0, 0x0001);
MIPI_OUTP(MIPI_DSI_BASE + 0x2d4, 0x0001);
MIPI_OUTP(MIPI_DSI_BASE + 0x2d8, 0x0000);
#ifdef DSI_POWER
MIPI_OUTP(MIPI_DSI_BASE + 0x2dc, 0x0100);
#endif
pd = (panel_info->mipi).dsi_phy_db;
off = 0x02cc;
for (i = 0; i < 4; i++) {
MIPI_OUTP(MIPI_DSI_BASE + off, pd->regulator[i]);
wmb();
off += 4;
}
off = 0x0260;
for (i = 0; i < 11; i++) {
MIPI_OUTP(MIPI_DSI_BASE + off, pd->timing[i]);
wmb();
off += 4;
}
off = 0x0290;
for (i = 0; i < 4; i++) {
MIPI_OUTP(MIPI_DSI_BASE + off, pd->ctrl[i]);
wmb();
off += 4;
}
off = 0x02a0;
for (i = 0; i < 4; i++) {
MIPI_OUTP(MIPI_DSI_BASE + off, pd->strength[i]);
wmb();
off += 4;
}
mipi_dsi_calibration();
off = 0x0204;
for (i = 1; i < 21; i++) {
MIPI_OUTP(MIPI_DSI_BASE + off, pd->pll[i]);
wmb();
off += 4;
}
if (panel_info)
mipi_dsi_phy_pll_config(panel_info->clk_rate);
MIPI_OUTP(MIPI_DSI_BASE + 0x200, pd->pll[0]);
wmb();
}
static int mipi_dsi_probe(struct platform_device *pdev)
{
struct msm_fb_data_type *mfd;
struct fb_info *fbi;
struct platform_device *mdp_dev = NULL;
struct msm_fb_panel_data *pdata = NULL;
int rc;
resource_size_t size ;
if ((pdev->id == 0) && (pdev->num_resources >= 0)) {
mipi_dsi_pdata = pdev->dev.platform_data;
size = resource_size(&pdev->resource[0]);
mipi_dsi_base = ioremap(pdev->resource[0].start, size);
MSM_FB_INFO("mipi_dsi base phy_addr = 0x%x virt = 0x%x\n",
pdev->resource[0].start, (int) mipi_dsi_base);
if (!mipi_dsi_base)
return -ENOMEM;
mmss_cc_base = ioremap(MMSS_CC_BASE_PHY, 0x200);
MSM_FB_INFO("mmss_cc base phy_addr = 0x%x virt = 0x%x\n",
MMSS_CC_BASE_PHY, (int) mmss_cc_base);
if (!mmss_cc_base)
return -ENOMEM;
mmss_sfpb_base = ioremap(MMSS_SFPB_BASE_PHY, 0x100);
MSM_FB_INFO("mmss_sfpb base phy_addr = 0x%x virt = 0x%x\n",
MMSS_SFPB_BASE_PHY, (int) mmss_sfpb_base);
if (!mmss_cc_base)
return -ENOMEM;
rc = request_irq(DSI_IRQ, mipi_dsi_isr, IRQF_DISABLED,
"MIPI_DSI", 0);
if (rc) {
printk(KERN_ERR "mipi_dsi_host request_irq() failed!\n");
return rc;
}
disable_irq(DSI_IRQ);
mipi_dsi_calibration();
if (mipi_dsi_mxo_selected())
dsi_cc_data |= BIT(8); /* use MXO for DSI PLL clkref */
else
dsi_cc_data &= ~BIT(8); /* use PXO */
mipi_dsi_resource_initialized = 1;
return 0;
}
if (!mipi_dsi_resource_initialized)
return -EPERM;
mfd = platform_get_drvdata(pdev);
if (!mfd)
return -ENODEV;
if (mfd->key != MFD_KEY)
return -EINVAL;
if (pdev_list_cnt >= MSM_FB_MAX_DEV_LIST)
return -ENOMEM;
mdp_dev = platform_device_alloc("mdp", pdev->id);
if (!mdp_dev)
return -ENOMEM;
/*
* link to the latest pdev
*/
mfd->pdev = mdp_dev;
mfd->dest = DISPLAY_LCD;
/*
* alloc panel device data
*/
if (platform_device_add_data
(mdp_dev, pdev->dev.platform_data,
sizeof(struct msm_fb_panel_data))) {
printk(KERN_ERR "mipi_dsi_probe: platform_device_add_data failed!\n");
platform_device_put(mdp_dev);
return -ENOMEM;
}
/*
* data chain
*/
pdata = mdp_dev->dev.platform_data;
pdata->on = mipi_dsi_on;
pdata->off = mipi_dsi_off;
pdata->next = pdev;
/*
* get/set panel specific fb info
*/
mfd->panel_info = pdata->panel_info;
if (mfd->index == 0)
mfd->fb_imgType = MSMFB_DEFAULT_TYPE;
else
mfd->fb_imgType = MDP_RGB_565;
fbi = mfd->fbi;
fbi->var.pixclock = mfd->panel_info.clk_rate;
fbi->var.left_margin = mfd->panel_info.lcdc.h_back_porch;
fbi->var.right_margin = mfd->panel_info.lcdc.h_front_porch;
fbi->var.upper_margin = mfd->panel_info.lcdc.v_back_porch;
fbi->var.lower_margin = mfd->panel_info.lcdc.v_front_porch;
fbi->var.hsync_len = mfd->panel_info.lcdc.h_pulse_width;
fbi->var.vsync_len = mfd->panel_info.lcdc.v_pulse_width;
#ifdef DSI_CLK
clk_rate = mfd->panel_info.clk_max;
if (clk_set_max_rate(mipi_dsi_clk, clk_rate) < 0)
printk(KERN_ERR "%s: clk_set_max_rate failed\n", __func__);
mfd->panel_info.clk_rate = mfd->panel_info.clk_min;
#endif
/*
* set driver data
*/
platform_set_drvdata(mdp_dev, mfd);
/*
* register in mdp driver
*/
rc = platform_device_add(mdp_dev);
if (rc)
goto mipi_dsi_probe_err;
pdev_list[pdev_list_cnt++] = pdev;
mfd->pm_qos_req = pm_qos_add_request(PM_QOS_SYSTEM_BUS_FREQ,
PM_QOS_DEFAULT_VALUE);
if (!mfd->pm_qos_req)
goto mipi_dsi_probe_err;
return 0;
mipi_dsi_probe_err:
platform_device_put(mdp_dev);
return rc;
}
void mipi_dsi_phy_init(int panel_ndx, struct msm_panel_info const *panel_info,
int target_type)
{
struct mipi_dsi_phy_ctrl *pd;
int i, off;
MIPI_OUTP(MIPI_DSI_BASE + 0x128, 0x0001);
wmb();
usleep(1);
MIPI_OUTP(MIPI_DSI_BASE + 0x128, 0x0000);
wmb();
usleep(1);
MIPI_OUTP(MIPI_DSI_BASE + 0x500, 0x0003);
MIPI_OUTP(MIPI_DSI_BASE + 0x504, 0x0001);
MIPI_OUTP(MIPI_DSI_BASE + 0x508, 0x0001);
MIPI_OUTP(MIPI_DSI_BASE + 0x50c, 0x0000);
MIPI_OUTP(MIPI_DSI_BASE + 0x510, 0x0100);
MIPI_OUTP(MIPI_DSI_BASE + 0x4b0, 0x04);
pd = (panel_info->mipi).dsi_phy_db;
off = 0x0480;
for (i = 0; i < 3; i++) {
MIPI_OUTP(MIPI_DSI_BASE + off, pd->strength[i]);
wmb();
off += 4;
}
off = 0x0470;
for (i = 0; i < 4; i++) {
MIPI_OUTP(MIPI_DSI_BASE + off, pd->ctrl[i]);
wmb();
off += 4;
}
off = 0x0500;
for (i = 0; i < 5; i++) {
MIPI_OUTP(MIPI_DSI_BASE + off, pd->regulator[i]);
wmb();
off += 4;
}
mipi_dsi_calibration();
mipi_dsi_lane_cfg();
mipi_dsi_bist_ctrl();
off = 0x0204;
for (i = 1; i < 20; i++) {
MIPI_OUTP(MIPI_DSI_BASE + off, pd->pll[i]);
wmb();
off += 4;
}
if (panel_info)
mipi_dsi_phy_pll_config(panel_info->clk_rate);
MIPI_OUTP(MIPI_DSI_BASE + 0x200, pd->pll[0]);
wmb();
off = 0x0440;
for (i = 0; i < 12; i++) {
MIPI_OUTP(MIPI_DSI_BASE + off, pd->timing[i]);
wmb();
off += 4;
}
if (target_type == 1)
mipi_dsi_configure_serdes();
}
void mipi_dsi_phy_init(int panel_ndx, struct msm_panel_info const *panel_info,
int target_type)
{
struct mipi_dsi_phy_ctrl *pd;
int i, off;
MIPI_OUTP(MIPI_DSI_BASE + 0x128, 0x0001);/* start phy sw reset */
wmb();
#ifdef CONFIG_SHLCDC_BOARD /* CUST_ID_00049 */ /* CUST_ID_00082 */
mipi_sharp_delay_us(1);
#else /* CONFIG_SHLCDC_BOARD */
usleep(1);
#endif /* CONFIG_SHLCDC_BOARD */
MIPI_OUTP(MIPI_DSI_BASE + 0x128, 0x0000);/* end phy w reset */
wmb();
#ifdef CONFIG_SHLCDC_BOARD /* CUST_ID_00049 */ /* CUST_ID_00082 */
mipi_sharp_delay_us(1);
#else /* CONFIG_SHLCDC_BOARD */
usleep(1);
#endif /* CONFIG_SHLCDC_BOARD */
MIPI_OUTP(MIPI_DSI_BASE + 0x500, 0x0003);/* regulator_ctrl_0 */
MIPI_OUTP(MIPI_DSI_BASE + 0x504, 0x0001);/* regulator_ctrl_1 */
MIPI_OUTP(MIPI_DSI_BASE + 0x508, 0x0001);/* regulator_ctrl_2 */
MIPI_OUTP(MIPI_DSI_BASE + 0x50c, 0x0000);/* regulator_ctrl_3 */
MIPI_OUTP(MIPI_DSI_BASE + 0x510, 0x0100);/* regulator_ctrl_4 */
MIPI_OUTP(MIPI_DSI_BASE + 0x4b0, 0x04);/* DSIPHY_LDO_CNTRL */
pd = (panel_info->mipi).dsi_phy_db;
off = 0x0480; /* strength 0 - 2 */
for (i = 0; i < 3; i++) {
MIPI_OUTP(MIPI_DSI_BASE + off, pd->strength[i]);
wmb();
off += 4;
}
off = 0x0470; /* ctrl 0 - 3 */
for (i = 0; i < 4; i++) {
MIPI_OUTP(MIPI_DSI_BASE + off, pd->ctrl[i]);
wmb();
off += 4;
}
off = 0x0500; /* regulator ctrl 0 - 4 */
for (i = 0; i < 5; i++) {
MIPI_OUTP(MIPI_DSI_BASE + off, pd->regulator[i]);
wmb();
off += 4;
}
mipi_dsi_calibration();
mipi_dsi_lane_cfg(); /* lane cfgs */
mipi_dsi_bist_ctrl(); /* bist ctrl */
off = 0x0204; /* pll ctrl 1 - 19, skip 0 */
for (i = 1; i < 20; i++) {
MIPI_OUTP(MIPI_DSI_BASE + off, pd->pll[i]);
wmb();
off += 4;
}
#ifndef CONFIG_SHLCDC_BOARD /* CUST_ID_00005 */
if (panel_info)
mipi_dsi_phy_pll_config(panel_info->clk_rate);
#endif /* CONFIG_SHLCDC_BOARD */
/* pll ctrl 0 */
MIPI_OUTP(MIPI_DSI_BASE + 0x200, pd->pll[0]);
wmb();
off = 0x0440; /* phy timing ctrl 0 - 11 */
for (i = 0; i < 12; i++) {
MIPI_OUTP(MIPI_DSI_BASE + off, pd->timing[i]);
wmb();
off += 4;
}
if (target_type == 1)
mipi_dsi_configure_serdes();
}
void mipi_dsi_phy_init(int panel_ndx, struct msm_panel_info const *panel_info,
int target_type)
{
struct mipi_dsi_phy_ctrl *pd = NULL;
int i, off;
MIPI_OUTP(MIPI_DSI_BASE + 0x128, 0x0001);/* start phy sw reset */
wmb();
usleep(1);
MIPI_OUTP(MIPI_DSI_BASE + 0x128, 0x0000);/* end phy w reset */
wmb();
usleep(1);
MIPI_OUTP(MIPI_DSI_BASE + 0x500, 0x0003);/* regulator_ctrl_0 */
MIPI_OUTP(MIPI_DSI_BASE + 0x504, 0x0001);/* regulator_ctrl_1 */
MIPI_OUTP(MIPI_DSI_BASE + 0x508, 0x0001);/* regulator_ctrl_2 */
MIPI_OUTP(MIPI_DSI_BASE + 0x50c, 0x0000);/* regulator_ctrl_3 */
MIPI_OUTP(MIPI_DSI_BASE + 0x510, 0x0100);/* regulator_ctrl_4 */
MIPI_OUTP(MIPI_DSI_BASE + 0x4b0, 0x04);/* DSIPHY_LDO_CNTRL */
//rms
for (i = 0; i < (panel_info->mipi).dsi_phy_db_count; i++) {
pd = (panel_info->mipi).dsi_phy_db[i];
if ((panel_info->mipi).frame_rate == pd->frame) {
printk(KERN_ERR"(%s:%d) use frame_rate %d %d",
__FUNCTION__, __LINE__,
i, pd->frame);
break;
}
}
if (i >= (panel_info->mipi).dsi_phy_db_count) {
pd = (panel_info->mipi).dsi_phy_db[0];
printk(KERN_ERR"(%s:%d) cannot support %d %d %d, use default",
__FUNCTION__, __LINE__,
(panel_info->mipi).frame_rate, i, pd->frame);
}
//end
off = 0x0480; /* strength 0 - 2 */
for (i = 0; i < 3; i++) {
MIPI_OUTP(MIPI_DSI_BASE + off, pd->strength[i]);
wmb();
off += 4;
}
off = 0x0470; /* ctrl 0 - 3 */
for (i = 0; i < 4; i++) {
MIPI_OUTP(MIPI_DSI_BASE + off, pd->ctrl[i]);
wmb();
off += 4;
}
off = 0x0500; /* regulator ctrl 0 - 4 */
for (i = 0; i < 5; i++) {
MIPI_OUTP(MIPI_DSI_BASE + off, pd->regulator[i]);
wmb();
off += 4;
}
mipi_dsi_calibration();
mipi_dsi_lane_cfg(); /* lane cfgs */
mipi_dsi_bist_ctrl(); /* bist ctrl */
off = 0x0204; /* pll ctrl 1 - 19, skip 0 */
for (i = 1; i < 20; i++) {
MIPI_OUTP(MIPI_DSI_BASE + off, pd->pll[i]);
wmb();
off += 4;
}
if (panel_info) {
printk(KERN_ERR"rms:(%s:%d) clk_rate %u", __FUNCTION__, __LINE__, panel_info->clk_rate);
mipi_dsi_phy_pll_config(panel_info->clk_rate);
}
/* pll ctrl 0 */
MIPI_OUTP(MIPI_DSI_BASE + 0x200, pd->pll[0]);
wmb();
off = 0x0440; /* phy timing ctrl 0 - 11 */
for (i = 0; i < 12; i++) {
MIPI_OUTP(MIPI_DSI_BASE + off, pd->timing[i]);
wmb();
off += 4;
}
if (target_type == 1)
mipi_dsi_configure_serdes();
}
